JPH0567206A - Digital picture reduction circuit - Google Patents

Abstract

PURPOSE:To reduce the deterioration of a picture with comparatively simple constitution while a reduced picture is generated. CONSTITUTION:A frequency-dividing circuit into N-number 51 outputs one first pulse whenever N-number of clocks (b) are inputted. A frequency-dividing circuit into M-number 53 outputs one second pulse whenever M-number of line pulses (c) are inputted. A first data synthesis means outputs a prescribed value as first synthesis data when at least one of picture data fetched in one period of the first pulse takes the prescribed threshold. A second data synthesis means outputs the prescribed value as second synthesis data in respective addresses when at least one first synthesis data fetched into the respective addresses corresponding to a main scan direction position in one period of the second pulse takes the prescribed threshold. Thus, the picture can be reduced at the reduction factor of 1/N in a main scan direction and of 1/M in an auxiliary scan direction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital image reduction circuit for generating a reduced image of a digital image.

[0002]

2. Description of the Related Art In digital copying machines and facsimile machines, generation of a reduced image is one important function. Reduction of a digital image can be realized by, for example, performing conversion processing for image reduction on pixel data forming a digital image.

[0003]

However, in order to perform such conversion processing, a dedicated arithmetic unit or the like is required, which not only causes an increase in cost, but also takes a long time to obtain a reduced image. In addition, when the image data after the reduction processing is reproduced as an image, deterioration of the image often occurs, for example, a thin line is not reproduced as a continuous line.

The present invention has been made in view of the above-mentioned conventional problems, and it is an object of the present invention to provide a digital image reduction circuit capable of generating a reduced image while reducing deterioration of an image with a relatively simple structure. And

[0005]

In order to achieve the above-mentioned object, the digital image reduction circuit of the present invention has pixel data sequentially input in synchronization with a clock in the main scanning direction and 1 in the main scanning direction. A digital image reducing circuit in which a line pulse is input for each pixel data of lines, the first pulse generating means generating a first pulse when N clocks are input, and M line pulses. If at least one of the second pulse generating means for generating a second pulse when the input is inputted and the pixel data sequentially fetched during one cycle of the first pulse takes a predetermined value. In this case, the first data integrating means for outputting the predetermined value as first integrated data corresponding to one cycle of the first pulse, and the first integrated data corresponding to one line are positioned in the main scanning direction. To different addresses corresponding to When at least one of the first integrated data which is taken in and taken into each address during one cycle of the second pulse takes the predetermined value, the predetermined value is used as the second integrated data at each address. And a second data integrating means for outputting.

[0006]

In the digital image reduction circuit of the present invention, pixel data are sequentially input in synchronization with a clock, and a line pulse is input for each pixel data of one line. At this time, the first pulse generating means generates the first pulse when N clocks are input, and the second pulse generating means generates the second pulse when M line pulses are input.
Here, the first data integrating means outputs the predetermined value as the first integrated data when at least one of the pixel data taken in during one cycle of the first pulse has a predetermined value. Therefore, the first integrated data is obtained by reducing the pixel data to 1 / N in the main scanning direction for each line. Further, the second data integrating means is provided when at least one of the first integrated data taken into each address corresponding to the position in the main scanning direction takes the predetermined value during one cycle of the second pulse. Since the predetermined value is output as the second integrated data at each address, the second integrated data is obtained by reducing the pixel data to 1 / M in the sub-scanning direction.

As a result of the above, image data consisting of a large number of pixel data is reduced to 1 / N in the main scanning direction and 1 / N in the sub-scanning direction.
It is possible to reduce to M, and by changing the values of N and M, it is possible to obtain a reduced image at an arbitrary reduction ratio that is the same or different in the vertical and horizontal directions.

Further, if there is even one pixel data having a predetermined high level value, this pixel data will be stored in the pixel data in the process of the above-mentioned first and second data integration means. Since the corresponding first and second integrated data are also at the high level, the thin line does not become a discontinuous line due to the reduction processing as in the conventional example. Furthermore, the first as described above
Since the second and second pulse generating means and the first and second data integrating means can be configured by simple circuit elements such as counters and flip-flops, the digital image reducing circuit can be realized at low cost. Moreover, since the processing contents are simple, the processing can be performed at high speed.

The action of the present invention will be more apparent from the following examples of the present invention, and other actions of the present invention will be further clarified.

[0010]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 shows a digital image reduction circuit which is an embodiment of the present invention. In this circuit, as shown in the timing chart of FIG. 2, pixel data of the original image given as input data a in the main scanning direction, a clock b synchronized with the input data, and one line in the main scanning direction. And the line pulse c corresponding to the horizontal synchronizing signal of the television.

In FIG. 1, the digital image reduction circuit is
N divider counter 5 constituting an example of the first pulse generating means
1, a timing generator 52, and a M frequency dividing counter 53 which constitutes an example of a second pulse generating means.

The N divider counter 51 is for dividing the clock b by an arbitrary natural number N. In this embodiment, as shown in the timing chart of FIG. (N = 10) One pulse is output each time it is input. On the other hand, the timing generator 52 outputs a pulse having the same cycle as the output signal d to the FIFO (first in first out) memory 11 as a write signal e.

The M divider counter 53 is for dividing the line pulse c by an arbitrary natural number M. In this embodiment, one counter is provided every 10 line pulses c (M = 10). Output a pulse. The output of the counter 53 and the output signal d of the counter 51 are ANDed by the AND circuit 12, and the result is given to the memory 11 and the flip-flop 8 as a signal f.

In FIG. 1, the digital image reducing circuit further includes an OR circuit 9 constituting an example of the first data integrating means,
The flip-flops 4 and 6 are provided with an OR circuit 10, a FIFO memory 11 and a flip-flop 8 which constitute an example of the second data integrating means.

The OR circuit 9 and the flip-flop 4 constitute a circuit for reducing in the main scanning direction. The input data a is input to one input terminal of the OR circuit 9, and the other input terminal is connected to the output terminal of the flip-flop 4. The output terminal of the OR circuit 9 is connected to the data input terminal of the flip-flop 4. The clock b is input to the clock input terminal of the flip-flop 4, and the counter 5 is applied to the clear terminal through the inverting circuit 12.
The output signal d of 1 is input.

The flip-flop 6 is the flip-flop 4
The data input terminal is connected to the output terminal of the flip-flop 4, and the output signal d of the counter 51 is input to the clock input terminal.

The OR circuit 10 and the memory 11 constitute a circuit for reducing in the sub-scanning direction. One input terminal of the OR circuit 10 is an output terminal of the flip-flop 6 and the other input terminal is a memory 11. Connected to the output terminals,
The output terminal is connected to the input terminal of the memory 11. The memory 11 increments the address in synchronization with the write signal e and sequentially writes the data from the OR circuit 10 to each address. When the signal f is input, the stored contents are cleared.

The flip-flop 8 is for holding the data read from the memory 11, its data input terminal is connected to the output terminal of the memory 11, and the signal f is input to its clock input terminal. ..

Next, the operation of the digital image reducing circuit configured as described above will be described. The input data a is given to the flip-flop 4 through the OR circuit 9 and taken into the flip-flop 4 in synchronization with the clock b. When the input data a is given as shown in FIG. 3, the flip-flop 4 is turned on at the rising edge of the fourth clock b.
Takes high level data and sets its output to high level. After that, the input data becomes low level after the fifth clock b, but since the high level output is input to the flip-flop 4 through the OR circuit 9, the flip-flop 4 maintains the output at the high level. To do. Then, when the tenth clock b is input and the counter 51 outputs a pulse as the output signal d, it is given to the flip-flop 4 through the inverting circuit 12, and the flip-flop 4 is reset. Therefore, its output returns to low level. However, flip-flop 4
Before the output of the flip-flop 6 becomes low level, the flip-flop 6 takes in the output data of the flip-flop 4 at the rise of the output signal d, so that the output becomes high level. Since the input data a is at the low level for the next 10 cycles of the clock b, the output of the flip-flop 4 also maintains the low level, and the data at the low level is further flipped at the rising edge of the next output signal d. Is taken into.

That is, when one or a plurality of high-level input data a are input during 10 cycles of the clock b, they are integrated as the first integrated data and output as one high-level data. To be done. Therefore, 1 in the main scanning direction
A reduction of / 10 will be made.

The data output from the flip-flop 6 is input to and stored in the memory 11 via the OR circuit 10. As shown in FIG. 4, the memory 11 increments the address each time the write signal e having the same cycle as the output signal d is input, fetches the data from the flip-flop 6 at the timing of the write signal e, and outputs each data. It is stored as pixel data after image reduction.

The increment of the address in the memory 11 continues until the next line pulse is input. When the line pulse is input, the address is returned to the initial value, and the address is incremented again to fetch and store the data.
However, when writing data, if high-level data is already stored at the address, the data is output from the memory 11 through the OR circuit 10 to the memory 11
Therefore, even if the output data of the flip-flop 6 is low level, high level data is written in the memory 11. That is, as shown in the timing chart of FIG. 5, when high level data is first written to the (n + 1) th address, even if no high level data is given from the flip-flop 6 thereafter, the (n + 1) th address is High level data is retained. After that, when high level data is written to the n + 2th address as shown in the figure, thereafter, even if high level data is not given from the flip-flop 6, the high level data is held at the n + 2th address. To be done. The high-level data stored in the memory 11 is held until the signal f is input and the stored contents are cleared. As shown in FIG. 6, the flip-flop 8 fetches and holds the output data of the memory 11 at the timing of the signal f and outputs it as reduced image data.

That is, in the memory 11, ten main scanning lines are included.
High level data at the same position on the main scanning line will be integrated as the second integrated data in units of lines,
Reduction of 1/10 in the sub-scanning direction is performed.

[0024]

As described in detail above, according to the digital image reducing circuit of the present invention, the first pulse generating means is N
When the clocks are input, the first pulse is generated and the second pulse is generated.
The pulse generating means generates a second pulse when M line pulses are input. Here, the first data integrating means outputs the predetermined value as the first integrated data when at least one of the pixel data taken in during one cycle of the first pulse has a predetermined value. Therefore, the first integrated data
The data is obtained by reducing the pixel data to 1 / N in the main scanning direction for each line. Further, the second data integrating means is arranged such that at least one of the first integrated data taken into each address corresponding to the position in the main scanning direction takes the predetermined value during one cycle of the second pulse. Since the predetermined value is output as the second integrated data at each address, the second integrated data is obtained by reducing the pixel data to 1 / M in the sub-scanning direction.

As a result, the image data consisting of a large number of pixel data is reduced to 1 / N in the main scanning direction and 1 / N in the sub scanning direction.
It is possible to reduce to M, and by changing the values of N and M, it is possible to obtain a reduced image at an arbitrary reduction ratio that is the same or different in the vertical and horizontal directions.

If there is at least one pixel data having a predetermined high level value, this pixel data will be stored in the pixel data in the process of the first and second data integration means. Since the corresponding first and second integrated data are also at the high level, the thin line does not become a discontinuous line due to the reduction processing as in the conventional example. Furthermore, the first as described above
Since the second and second pulse generating means and the first and second data integrating means can be configured by simple circuit elements such as counters and flip-flops, the digital image reducing circuit can be realized at low cost. Moreover, since the processing contents are simple, the processing can be performed at high speed.

As a result, according to the present invention, it is possible to realize an inexpensive digital image reduction circuit which can quickly generate a reduced image while reducing image deterioration.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a digital image reduction circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing signals and data input to the digital image reduction circuit of FIG.

FIG. 3 is a timing chart for explaining a reduction operation in the main scanning direction in the digital image reduction circuit of FIG.

FIG. 4 is a timing chart for explaining a reduction operation in the sub-scanning direction in the digital image reduction circuit of FIG.

5 is another timing chart for explaining the reduction operation in the sub-scanning direction in the digital image reduction circuit of FIG.

FIG. 6 is a timing chart showing an operation of an output unit which constitutes the digital image reduction circuit of FIG.

[Explanation of symbols]

 4, 6, 8 Flip-flop 9, 10 OR circuit 11 FIFO memory 12 Inversion circuit 51 N divider counter 52 Timing generator 53 M divider counter

Claims (1)

[Claims] 1. A digital image reduction circuit in which pixel data is sequentially input in order in the main scanning direction in synchronization with a clock, and a line pulse is input for each pixel data of one line in the main scanning direction. A first pulse generating means for generating a first pulse when N clocks are input, a second pulse generating means for generating a second pulse when M line pulses are input, and the pixel When at least one of the pixel data captured during one cycle of the first pulse has a predetermined value, the predetermined value corresponds to the first cycle of the first pulse. First data integrating means for outputting as integrated data and the first integrated data corresponding to the one line are sequentially fetched at different addresses corresponding to the position in the main scanning direction, and one of the second pulses is fetched. To each address during the cycle Second data integration means for outputting the predetermined value as second integrated data at the respective addresses when at least one of the first integrated data fetched takes the predetermined value. Digital image reduction circuit characterized by.