JPS60189583A - Shift circuit of digital picture - Google Patents

Abstract

PURPOSE:To enable a picture having plural picture elements in real-time by reading contents in memory to a latch circuit in the 1st section of one picture element clock frequency and then by writing a picture signal input in a memory address in the 2nd section. CONSTITUTION:Since a memory 42 becomes a write mode when a picture element clock is in a high level section, a memory output becomes high impedance. As a result, data DU will not be outputted, and instead of the data DU a buffer circuit 45 becomes the enable condition in this section and outputs an input picture signal DL to the memory 42. Said picture signal DL is written in an address A of the memory 42 due to a rise of a picture element clock. When an address counter 41 is reset by means of a horizontal synchronizing signal after the counter 41 scans an arbitrary one line (picture), picture data of one line are stored in the memory 42. Then, while the address counter 41 is counting up again, picture element data of one line are outputted at every one picture element clock and those of the next one line are written in the memory 42. Thus a switching buffer and a multiplexer become unnecessary; therefore real- time processing can be possible with simple constitution.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention processes images obtained from a TV left camera,
The present invention relates to a digital image shift circuit used in an image processing device that recognizes qualitative characteristics such as the type and position of an object shown therein.

[Conventional example]

FIG. 1 is an explanatory diagram for explaining digital image shifting, and FIG. 2 is a connection diagram showing an example of a conventional digital image shifting circuit.

In the above-mentioned image processing apparatus, as shown in FIG. A new image is created by scanning the mask MA over the image and performing calculations between each pixel. Conventionally, circuit means as shown in FIG. 2 has been used to perform such image shifting. This circuit is
This is a case where a 3×3 mask consisting of elements AB...X is used, and the n-bit shift register 8R1, S has the same number of bits as the number of horizontal pixels of the image.
Requires R2.

However, the number of bits in a shift register is usually a power of 2, and when the number of pixels in the horizontal direction increases, for example 64 or more, it is not easy to prepare a shift register with a corresponding number of bits. , there is also the problem that it is expensive. If there is no shift register corresponding to the number of pixels, a plurality of shift registers with a small number of bits will be used in parallel.

FIG. 3 is a basic block diagram of a conventional digital image shift circuit (Japanese Patent Application No. 163585/1985) which has a relatively simple configuration and can handle images with a large number of pixels. However, since this circuit uses two sets of RAMs (M1 and M2), buffers 1 to 4 and a multi-7° lexer (not shown) are required for switching outputs. Furthermore, since the write operation and the shift operation are separate, two scans are required to shift one line of the image, making real-time processing impossible.

[Purpose of the invention]

The present invention has been made to solve the above problems, and aims to realize a digital image shift circuit that can process images with a large number of pixels in real time with a simple configuration. Overview] The digital image shift circuit of the present invention includes an address counter that counts pixel clocks and is set to an initial state by an image horizontal synchronization signal, and an address counter that counts pixel clocks and that
The memory includes a memory whose address is specified by the output from the memory, and a latch circuit which inputs the readout output of this memory.
The content of the memory at the address is read to the latch circuit in a first period of one cycle of the pixel clock, and then the image signal input is written to the address of the memory in the period of cylinder 2. shall be.

〔Example〕

The present invention will be described in detail below using the drawings.

FIG. 4 is a block diagram showing an embodiment of the digital image shift circuit according to the present invention. 41 is an address counter that counts pixel clocks and is reset (set to an initial state) by an image horizontal synchronization signal; 42 is a counter 41;
43 latch circuits (transparent latch) that hold the data output of the memory 42, 44 are connected to the output terminal of the circuit 43. 45 is an output terminal for taking out the delayed output to the outside, and 45 is an input terminal 461C for inputting an image signal added to the memory 42.
A three-state buffer circuit 47 is a bidirectional data bus that connects the memory 42 and the latch circuit 45 and buffer circuit 45. As the address counter 41, the number of pixels in the horizontal direction of the image is, for example, 32.
When the pixel is 0 (in the case of the NTSC system), a binary counter of 9 bits or more may be used. In this case, pixel black,
The frequency is approximately 614 MHz and the period is 165 ns.

FIG. 5 is a time chart for explaining the operation of the digital image shift circuit configured as described above. The address counter 41 is incremented by +1 after a certain time delay due to the rise of the pixel clock ('r), and the address A of the memory 42 is accessed (time chart) (O)).

Since the memory 42 is in the read mode during the period when the pixel clock is at H level, the data D is read after a certain read time delay.
Output U to data bus 47 (time chart (c)
). This data output DU is input to the latch circuit 43,
It is latched at the falling edge of the pixel clock and held until the rising edge of the next pixel clock (as shown in the time chart). The output of this latch circuit 43 becomes a delayed output. memory 42
is in the write mode during the period in which the pixel clock is at L level, so the memory output becomes high impedance and no data DU is output. Instead, in this section, the buffer circuit 45 is enabled, and the input image signal DL
is output to the memory 42 (time chart (c)). This image signal is input to the address AK- of the memory 42 at the rising edge of the pixel clock. When the address counter 41 is reset by a horizontal synchronizing signal after scanning an arbitrary one (pixel@) line, the pixel data of the one line is stored in the memory 42. Next, when the address counter 41 is counted up again, the next line of pixel data is written into the memory 42 while outputting the one line of pixel data every pixel clock. That is, terminal 4
The pixel data output from 4 corresponds to the pixel one line above the currently input pixel on the image, so a one-line shift register (digital image shift circuit) has been realized. . The length and number of bits of this shift register are the number of stages of the counter 41 and the number of stages of the memory 42.
If the word length is set to a sufficient value, it can be made to correspond to the number of horizontal scanning clocks (the number of pixels in the horizontal direction of the image). Also memory 42
By appropriately selecting the word width and the number of latch circuits 43 and buffer circuits 45, the number of bits of image data can be set to any value of 1 or more.

According to the digital image shift circuit configured as described above, compared to the conventional digital image shift circuit, the RAM is 1
By using common and inexpensive parts such as switching buffers, multi-touch buffers, and transparent latches,
It can achieve the same functionality as an expensive shift register.

Furthermore, by changing the period of the (horizontal) synchronization signal, it can operate as a shift register with any number of bits depending on the period, which is a function not found in normal shift registers. This is especially advantageous when the number of required shift register bits is large or when the number of bits in the shift register is odd, other than 2n.

FIG. 6 shows the second part of the digital image shift circuit according to the present invention.
FIG. 2 is a block diagram illustrating a configuration that performs n-line shifting in an embodiment of the present invention. 61 is an address counter, 62 is a memory that is addressed by the output of this address counter 61, 631 to 63n are latch circuits that hold the output from this memory 62, and 651 to 65n are input image signals from the input terminal 66 or the above. Latch circuits 631 to 65 (
64 is a buffer circuit for adding the delayed output from the latch circuit 63n to the memory 62;
This is an output terminal that takes out the line delay output to the outside. Buffer circuits 651-65n and latch circuits 631-63n
are connected to each other in cascade. The pixel clock, horizontal synchronization signal, etc. are omitted in the figure. The memory 62 needs to have a capacity sufficient to store n247 worth of image information.

The operation in each cycle of the pixel clock is the same as in the first embodiment, and the latch circuit-6 is operated in the same manner as in the first embodiment.
The one-line delayed output outputted from the latch circuit 631 is again applied to the memory 62 via the buffer circuit 652 and stored therein, and then taken out from the latch circuit 632 as a two-line delayed output. By repeating the same procedure, the silatch circuit 63n
An n-line delay output can be obtained from .

FIG. 7 (similar to FIG. 6, pixel clocks and horizontal synchronization signals are omitted) is a configuration block diagram showing a third embodiment of the digital image shift circuit according to the present invention. In the embodiment shown in FIG. 4, a separate input/output type memory 72 is used instead of the memory 42.
(Input section DI and output section.

By using a separate memory), the buffer circuit 45 can be omitted and the configuration can be further simplified.

〔Effect of the invention〕

As described above, according to the present invention, a digital image shift circuit capable of processing images with a large number of pixels in real time can be realized with a simple configuration.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram for explaining a digital image shift circuit, Fig. 2 is a connection diagram showing an example of a conventional digital image shift circuit, and Fig. 3 is a block diagram showing another example of a conventional digital image shift circuit. 4 is a block diagram showing an embodiment of the digital image shift circuit according to the present invention, FIG. 5 is a time chart explaining the operation of the circuit in FIG. 4, and FIG. 6 is a block diagram showing an embodiment of the digital image shift circuit according to the present invention. FIG. 7 is a block diagram showing a second embodiment of the digital image shift circuit, and FIG. 7 is a block diagram showing a third embodiment of the digital image shift circuit according to the present invention. 41, /+1...address counter, 42.62.7
2...Memory, 43,631-63n...Latch circuit, A...Address, DU...Memory contents, DL
...Image signal input. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] An address counter that counts pixel clocks and is set to an initial state by an image horizontal synchronization signal, a memory whose address is specified by the output from this address counter, and a latch circuit that inputs the readout output of this memory. The content of the memory at the address is read to the latch circuit in a first period of one cycle of the pixel clock, and then the image signal input is written to the address of the memory in a second period. A digital image shift circuit characterized by: