JP2595280B2 - Image processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image processing apparatus that generates a digital video signal by sampling and quantizing an analog video signal.

[Prior Art] An image digitizing configuration in a conventional image processing apparatus will be described with reference to FIG.

First, a value for determining a sampling frequency for quantizing a video signal in the H direction (horizontal direction) and the V direction (vertical direction) is supplied to the H-direction frequency generator 50 and the V-direction frequency generator 51 by the CPU. And so on. These generators 50 and 51 generate signals of fundamental frequencies suitable for the H and V directions by an internal PLL (Phase Locked Loop) circuit or the like, and the generated signals are output from a timing generator.
Sent to 56. The timing generator 56 controls the H address counter 52 according to the video synchronization signals (HSYNC, VSYNC).
, V address counter 53, frame memory 54, A /
The D converter 55, the H-direction frequency generator 50, and the V-direction frequency generator 51 generate respective timing signals. As described above, each time the number of samplings in the H direction and the V direction changes, the sampling frequency in the H direction and the V direction must be changed, so that an expensive circuit configuration such as a PLL circuit is required.

[Problems to be Solved by the Invention] In the above-mentioned conventional technology, a large-scale circuit called a frequency generator in the H direction and the V direction is required, so that the video signal can be reduced by the same circuit, and the XY aspect ratio can be reduced. Or could not be easily realized.

SUMMARY An advantage of some aspects of the invention is to provide an image processing apparatus that can sample a video signal at an arbitrary interval.

[Means for Solving the Problems] In order to solve the above-described problems, a first image processing apparatus of the present invention samples an analog video signal in a vertical direction and a horizontal direction, respectively, and quantizes the digital video signal. An image processing apparatus for generating a signal, wherein the analog-to-digital conversion converts the analog video signal into the digital video signal.
A converter, a frame memory for storing the digital video signal generated by the A / D converter, a vertical counter for counting the number of pulses of a horizontal synchronization signal of the analog video signal, and a vertical direction for the analog video signal. A vertical sampling interval storage unit that stores the sampling intervals of the analog video signal in the vertical direction when the count value of the vertical counter matches the vertical sampling interval read from the vertical sampling interval storage unit. Outputting a first coincidence signal indicating the sampling timing of, and updating the vertical address of the frame memory and the address of the vertical sampling interval storage unit with the first coincidence signal, resetting the vertical counter, Thereby, the analog data written to the frame memory is obtained. Characterized by comprising a first comparator for determining the vertical sampling timing of the video signal.

Further, the second image processing apparatus of the present invention is arranged such that the first image processing apparatus has a horizontal counter for counting the number of pulses of a horizontal dot clock signal and a horizontal sampling interval of the analog video signal. A horizontal sampling interval storage unit for storing as an array, and when the count value of the horizontal counter matches the horizontal sampling interval read from the horizontal sampling interval storage unit, the horizontal sampling timing of the analog video signal is set. A second coincidence signal is output, and in accordance with the second coincidence signal, the analog video signal is converted into the digital video signal in the A / D converter and written into the frame memory, and the horizontal address of the frame memory is written. And the address of the horizontal sampling interval storage unit are updated. Counter is reset, and thereby, a second comparator for determining a horizontal sampling timing of the analog video signal to be written into the frame memory, with the addition of a.

[Operation] When the vertical address of the frame memory and the address of the vertical sampling interval storage section are updated by the first match signal, the vertical address of the frame memory becomes the next address value for storing the digital video signal, and The next vertical sampling interval is read from the sampling interval storage unit. When the vertical counter is reset by the first coincidence signal, counting of the number of pulses of the horizontal synchronization signal is newly started. Then, when the count value of the vertical counter matches the next vertical sampling interval, the above operation is performed again. Therefore, the digital video signal is written to the same vertical address in the frame memory until the count value of the vertical counter and the vertical sampling interval match, but when they match, the vertical address is updated and the digital video signal is written to the next vertical address. Is written. As a result, the video signal of the line corresponding to the accumulated value of the vertical sampling interval is sequentially written to the frame memory. For example, the vertical sampling interval array SVIN
When T [] is 2, 2, 2,..., The video signals of the second, fourth, sixth, etc. lines are sequentially written to the frame memory. Also, an array S of vertical sampling intervals
If VINT [] is 2,3,2 ..., the second,
The video signals of the fifth, seventh,... Lines are sequentially written to the frame memory. Therefore, the image written in the frame memory is reduced in the vertical direction, and the reduction ratio is equal to the reciprocal of the average value of the vertical sampling intervals.

In the horizontal direction, A-D in accordance with the second match signal
A converter converts the analog video signal into a digital video signal and writes the digital video signal to a frame memory. When the horizontal address of the frame memory and the address of the horizontal sampling interval storage unit are updated according to the second match signal, the horizontal address of the frame memory becomes the next address value for storing the digital video signal, The next horizontal sampling interval is read from the horizontal sampling interval storage unit. When the horizontal counter is reset by the second coincidence signal, the counting of the number of pulses of the dot clock signal is newly started. When the count value of the horizontal counter matches the next horizontal sampling interval, the above operation in the horizontal direction is performed again. Therefore, the digital video signal is written to the same horizontal address in the frame memory until the count value of the horizontal counter and the horizontal sampling interval match, but when they match, the horizontal address is updated and the digital video signal is written to the next horizontal address. Is written. As a result, in each line, the video signal at the pixel position corresponding to the accumulated value of the horizontal sampling interval is sequentially written to the frame memory. For example, when the array SHINT [] of the horizontal sampling intervals is 2, 2, 2,..., The video signals at the second, fourth, sixth,... Pixel positions are sequentially written to the frame memory. When the array SHINT [] of the horizontal sampling intervals is 2, 3, 2,..., The video signals at the second, fifth, seventh,... Pixel positions are sequentially written to the frame memory. Therefore, the image written in the frame memory is reduced in the horizontal direction, and the reduction ratio is equal to the reciprocal of the average value of the horizontal sampling intervals. When the first coincidence signal is not output while sampling is being performed by the second coincidence signal, the video signal is overwritten at the same address in the frame memory, so that the video is reduced in the vertical direction.

FIG. 1 is a block diagram showing an image processing apparatus according to an embodiment of the present invention. This image processing apparatus includes an SVmax storage unit 1 for storing the number of samplings in the V direction, an SHmax storage unit 2 for storing the number of samplings in the H direction, and a SHINT storage for storing the number of sampling intervals (horizontal sampling interval) in the H direction. Unit 7, a SHINT address counter 3 for counting addresses in the SHINT storage unit 7, an SVINT storage unit 8 for storing the number of sampling intervals (vertical sampling intervals) in the V direction, and an SVINT address for counting addresses in the SVINT storage unit 8. And a counter 4. The contents stored in these storage units 1, 2, 7, 8 can be rewritten under the control of an external CPU or the like.

The image processing apparatus further includes an F frame memory 15 for storing sampled image data, an FH address count 10 and an FV address counter 14 for designating a horizontal address and a vertical address of the F frame memory 15, respectively.
And Further, an ADC 18 for converting an analog value of video data from the outside into a digital value is provided, and the converted image data is written into the F frame memory 15. Further, a delay unit 22 for avoiding a back porch of the horizontal synchronization signal HSYNC is provided, and the horizontal synchronization signal output from the delay unit 22 is latched by an FF (flip-flop circuit) 23. Output signal from FF23 is NAND gate 19
Is input to The other input of the NAND gate 19 is connected to the output of the clock generator 24. The output of the clock generator 24 is generally called a dot clock, and is a clock signal indicating the timing of updating pixels in the horizontal direction.

The output of the NAND gate 19 is sent to a CH counter 16 as a horizontal counter. The count value obtained by the CH counter 16 is sent to the (SHINT: CH) comparator 11 for comparison with the value read from the SHINT storage unit 7. The count value obtained by the CV counter 17 as a vertical counter is sent to the (SVINT: CV) comparator 12 for comparison with the value read from the SVINT storage unit 8.
The above configuration is based on the horizontal sampling number SHmax and the vertical sampling number SVmax, and the array SHI of the horizontal sampling intervals obtained from FIGS. 2 and 3 described below.
Array SVINT of NT [] and the number of vertical sampling intervals
The operation is performed based on [], and the operation will be described after the description of FIGS. 2 and 3.

FIG. 2 is a flowchart showing a method of creating the number SHINT of horizontal sampling intervals to be written into the SHINT storage unit 7.

First, in step 30, the horizontal sampling number SHmax
Is written into the SHmax storage unit 2, and in step 31, the value of the maximum horizontal sampling number Hmax is read. The maximum horizontal sampling number Hmax is the maximum number of images in the horizontal direction when the video signal is sampled, and corresponds to the number of pixels in the horizontal direction of the image area of the frame memory 15. In this example, it is assumed that Hmax = 640. The horizontal sampling number SHmax is the actual sampling number in the horizontal direction when sampling the video signal, and takes a value equal to or less than the maximum horizontal sampling number Hmax. In this embodiment, SHmax = 32
The case of 0 will be described.

In step 32, the value of Hmax ÷ SHmax is subjected to floating calculation, and the result is substituted into a variable IH. In this embodiment, since Hmax = 640 and SHmax = 320, IH = 2.0.
In step 33, the parameter n used as a subscript of the array SHINT [] is initialized to 0, and the variable ALL is also initialized to 0. In step 34, the array element SHINT [n] of the number of horizontal sampling intervals is set to (IH * (n
+1) -ALL). Since the number of horizontal sampling intervals must be an integer, the integer part of the calculation result is assigned to the array element SHINT [n]. Then, in step 35, the variable ALL is set to SHIN
Add T [n] and assign the result to the variable ALL. n
When = 0, SHINT [0] = 2 and ALL = 2.

In step 36, the parameter n is incremented by one.

In step 37, it is determined whether or not the parameter n is equal to the horizontal sampling number SHmax, and the processes in steps 34 to 36 are repeatedly executed until n ≧ SHmax. Then, in step 38, the array SHINT [] of the completed number of horizontal sampling intervals is written in the SHINT storage unit 7.

In this embodiment, since Hmax = 640, SHmax320, and IH = 2.0, all the values in the array SHINT [] are 2. Also,
For example, when Hmax = 640 and SHmax = 256, IH = 2.5, and the values of the array SHINT [] obtained according to the procedure of FIG. 2 are 2, 3, 2, 3,... That is, each integer value of the array SHINT [] is determined such that the average value of the values of the array SHINT [] is equal to IH.

FIG. 3 is a flowchart showing a method for creating the number of vertical sampling intervals SVINT to be written into the SVINT storage unit 8.

First, in step 40, the vertical sampling number SVmax
Is written into the SVmax storage unit 1, and in step 41, the value of the vertical maximum sampling number Vmax is read. The maximum number of vertical samplings Vmax is the maximum number of scanning lines in the vertical direction when sampling a video signal.
Corresponds to the number of scanning lines of the image area. In this embodiment, it is assumed that Vmax = 200. Vertical sampling number SVmax
Is the actual sampling number in the vertical direction when sampling the video signal, and the maximum sampling number in the vertical direction Vm
Take a value less than or equal to ax. In this embodiment, a case where SVmax = 100 will be described.

In step 42, the value of Vmax ÷ SVmax is subjected to floating calculation, and the result is substituted for a variable IV. In this embodiment, since Vmax = 200 and SVmax = 100, IV = 2.0.
In step 43, the parameter n used as a subscript of the array SVINT [] is initialized to 0, and the variable ALL is also initialized to 0. In step 44, the array element SVINT [n] of the number of vertical sampling intervals is set to (IV * (n
+1) -ALL). Since the number of vertical sampling intervals must be an integer, the integer part of this calculation result is assigned to the array element SVINT [n]. Then, in step 45, the variable ALL is set to SVIN
Add T [n] and assign the result to the variable ALL. n
When = 0, SVINT [0] = 2 and ALL = 2.

In step 46, the parameter n is incremented by one.

In step 47, it is determined whether or not the parameter n is equal to the vertical sampling number SVmax, and the processes in steps 44 to 46 are repeatedly executed until n ≧ SVmax. Then, in step 48, the array SVINT [] of the completed number of vertical sampling intervals is written to the SVINT storage unit 8.

In this embodiment, Vmax = 200, SVmax = 100, IV = 2.0, so all values in the array SVINT [] are 2. Also,
For example, if Vmax = 200 and SVmax = 80, then IV = 2.5, and the values of the array SVINT [] obtained according to the procedure in FIG. 3 are 2, 3, 2, 3,. As a result, each integer value of the array SVINT [] is determined such that the average of the values of the array SVINT [] is equal to IV.

Now, the operation of the entire block will be described with reference to FIG. In this embodiment, as described above, SVmax = 100, SHma
x = 320 and all values in the arrays SHINT [] and SVINT [] are 2.

First, the FV address counter 14 is reset through the NOR gate 13 by the VSYNC signal, and the CV counter 17 is reset through the NOR gate 21.

Next, the FH address counter 10 and the SHINT address counter 3 are reset through the NOR gate 9 by the HSYNC signal, and the CH counter 16 is reset through the NOR gate 20. The HSYNC signal is further sent to the CV counter 17 as a clock, and causes the CV counter 17 to count up.

The HSYNC signal is held in the FF 23 after being delayed in the delay unit 22 to avoid the back porch area time zone,
An H-level output is supplied to the NAND gate 19. Then
The dot clock signal of the clock generator 24 is output from the NAND gate 19 and sent to the CH counter 16 as a count-up signal. When two pulses of the dot clock signal are sent to the CH counter 16, the count value of the CH counter 16 matches the value of the address 0 in the SHINT storage section, SHINT [0] = 2. Then, a coincidence signal is output from the (SHINT: CH) comparator 11, and the video signal is quantized by the ADC 18 and written to the F frame memory 15 in response to the coincidence signal. Comparator 11
Causes the FH address counter 10 and the SHINT address counter 3 to count up and resets the CH counter 16 through the NOR 20. As described above, each time the number of pulses of the dot clock signal is equal to the number of horizontal sampling intervals SHINT [], the video signal is quantized to F
The data is written to the frame memory 15. As a result, the array SHI
The video signal at the pixel position corresponding to the accumulated value of NT [] is sequentially written to the F frame memory 15. For example, if the array SHINT [] is 2,2,2 ...
The video signals at the second, fourth, sixth,... Pixel positions are sequentially written to the F frame memory 15. Also, the array SHINT
If [] is 2, 3, 2,..., The video signals at the second, fifth, seventh,... Pixel positions are sequentially written to the frame memory. Therefore, the image written in the frame memory is reduced in the horizontal direction, and the reduction rate is equal to the reciprocal of the average value of the array SHINT [] of the number of horizontal sampling intervals. As described above, the average value of the array SHINT [] determined according to the procedure of FIG.
(= Hmax / SHmax). Therefore, the F frame memory
The video written in 15 is reduced by a factor of 1 / IH in the horizontal direction.

When the above operation is repeated the number of times of the horizontal sampling number SHmax, the count value of the FH address counter 10 matches the horizontal sampling number SHmax. Then, (SHmax: F
H) The match signal is output from the comparator 6, and the FF 23 is reset to stop the output of the dot clock signal from the NAND gate 19. The coincidence signal of the comparator 6 further resets the FH address counter 10 and the SHINT address counter 3 through the NOR gate 9.

When the next HSYNC signal is input in this state, the above operation is repeated within the same address of the F frame memory 15. Although this does not cause a serious problem, if the operation is to be stopped for reasons such as power consumption, the operation may be stopped.

The operation in the vertical direction is as follows. HSYNC signal is C
When two pulses are sent to the V counter 17, the count value of the CV counter 17 is changed to the value SVINT [0] of the address 0 in the SVINT storage unit.
2 matches. Then, a match signal is output from the (SVINT: CV) comparator 12, and the FV address counter 14 and the SVINT
The address counter 4 counts up. The coincidence signal from the comparator 12 further resets the CV counter 17 through the NOR gate 21. Thus, HSYNC
Each time a signal pulse is generated by the number of pulses equal to the array SVINT [] of the number of vertical sampling intervals, the vertical address of the F frame memory 15 is updated. As a result, the video signal of the line corresponding to the accumulated value of the array SVINT [] is sequentially written to the F frame memory 15. For example, when the array SVINT [] is 2, 2, 2,..., The video signals of the second, fourth, sixth, etc. lines are sequentially written to the F frame memory 15. If the array SVINT [] is 2, 3, 2,..., The video signals of the second, fifth, seventh, etc. lines are sequentially written to the frame memory. Therefore, the image written in the frame memory is reduced in the vertical direction, and the reduction rate is an array SVINT [] of the number of vertical sampling intervals.
Equal to the reciprocal of the mean of In addition, as described above, the third
The average value of the array SVINT [] determined according to the procedure in the figure is equal to IV (= Vmax / SVmax). Therefore, the image written to the F frame memory 15 is reduced to 1 / IV times in the vertical direction. When the above operation is repeated the number of times of the vertical sampling number SVmax, the count value of the FV address counter 14 matches the vertical sampling number SVmax. Therefore,
(SVmax: FV) A match signal is output from the comparator 5, and the FV address counter 14 and the SVINT address counter 4 are reset through the NOR gate 13.

As described above, by changing the vertical sampling number SVmax and the horizontal sampling number SHmax, the array SVINT [] of the number of vertical sampling intervals and the array SHINT [] of the number of horizontal sampling intervals are changed as shown in FIGS. , And writing these in the respective storage units 1, 2, 8, and 7, the image can be sampled at arbitrary intervals in the vertical and horizontal directions. As a result, within the range of the image area of the frame memory 15, the image is enlarged /
Can be reduced. Further, the above-described image processing apparatus can be configured with only relatively simple and inexpensive circuit elements without using expensive circuit elements such as a PLL circuit.

[Effects of the Invention] As described above, according to the first image processing apparatus of the present invention, a video signal can be sampled at an arbitrary interval in the vertical direction. That is, there is an effect that the video signal of the line corresponding to the accumulated value of the vertical sampling interval can be sequentially written to the frame memory.

Further, according to the second image processing apparatus of the present invention, the video signal can be sampled at arbitrary intervals in the vertical and horizontal directions. That is, the video signal of the line corresponding to the accumulated value of the vertical sampling interval can be sequentially written to the frame memory, and the video signal of the pixel position corresponding to the accumulated value of the horizontal sampling interval in each line is stored in the frame memory. Has the effect that data can be sequentially written to

[Brief description of the drawings]

FIG. 1 is a block diagram in an embodiment of the present invention. FIG. 2 is a flow chart for creating the number of horizontal sampling intervals. FIG. 3 is a flow chart for creating the number of vertical sampling intervals. FIG. 4 is a block diagram according to a conventional example. 1 ... SVmax storage unit 2 ... SHmax storage unit 3 ... SHINT address counter 4 ... SVINT address counter 5 ... (SVmax: FV) comparator 6 ... (SHmax: FH) comparator 7 ... SHINT storage unit 8: SVINT storage unit 10: FH address counter 11: (SHINT: CH) comparator 12: (SVINT: CV) comparator 14: FV address counter 15: F frame memory 16: CH counter 17 ... CV counter 18 ... ADC 22 ... Delay section 23 ... Flip-flop 24 ... Clock generator 30 ... SHmax writing 31 ... Hmax reading 32 ... IH ← Hmax ÷ SHmax 33 ... n ← 0 , ALL ← 0 34... SHINT [n] ← IH * (n + 1) −ALL 35... ALL ← ALL + SHINT [n] 36... N ← n + 1 37... ] Write 40 ... Write SVmax 41 ... Read Vmax 42 ... IV ← Vmax ÷ SVmax 43 ... n ← 0, ALL ← 0 44 ... SVI NT [n] ← IV * (n + 1) −ALL 45... ALL ← ALL + SVINT [n] 46... N ← n + 1 47... N: SVmax comparison 48... Frequency generator 51… V direction frequency generator 52… H address counter 53… V address counter 54… Frame memory 55… A / D converter 56… Timing generator

Claims (2)

(57) [Claims] An image processing apparatus for generating a digital video signal by sampling and quantizing an analog video signal in a vertical direction and a horizontal direction, respectively, wherein the analog video signal is converted into the digital video signal. An A / D converter, a frame memory for storing the digital video signal generated by the A / D converter, a vertical counter for counting the number of pulses of a horizontal synchronization signal of the analog video signal, and the analog video signal A vertical sampling interval storage unit that stores the vertical sampling intervals as an array, and when the count value of the vertical counter matches the vertical sampling interval read from the vertical sampling interval storage unit, the analog video signal And outputs a first coincidence signal indicating the vertical sampling timing of
The first match signal updates a vertical address of the frame memory and an address of the vertical sampling interval storage unit, resets the vertical counter, and thereby updates the analog video signal written to the frame memory. An image processing apparatus comprising: a first comparator that determines a sampling timing in a vertical direction. 2. An image processing apparatus for generating a digital video signal by sampling and quantizing an analog video signal in a vertical direction and a horizontal direction, respectively, wherein the analog video signal is converted into the digital video signal. An A / D converter, a frame memory for storing the digital video signal generated by the A / D converter, a vertical counter for counting the number of pulses of a horizontal synchronization signal of the analog video signal, and the analog video signal A vertical sampling interval storage unit that stores the vertical sampling intervals as an array, and when the count value of the vertical counter matches the vertical sampling interval read from the vertical sampling interval storage unit, the analog video signal And outputs a first coincidence signal indicating the vertical sampling timing of
The first match signal updates a vertical address of the frame memory and an address of the vertical sampling interval storage unit, resets the vertical counter, and thereby updates the analog video signal written to the frame memory. A first comparator for determining a vertical sampling timing, a horizontal counter for counting the number of pulses of a horizontal dot clock signal, and a horizontal sampling interval storage for storing the horizontal sampling intervals of the analog video signal as an array And a second coincidence signal indicating a horizontal sampling timing of the analog video signal when a count value of the horizontal counter matches a horizontal sampling interval read from the horizontal sampling interval storage unit. And
According to the second coincidence signal, the analog video signal is converted into the digital video signal in the A / D converter and written into the frame memory, and the horizontal address of the frame memory and the address of the horizontal sampling interval storage unit are stored. And a second comparator that resets the horizontal counter and thereby determines the horizontal sampling timing of the analog video signal written to the frame memory. apparatus.