JPH06311397A - Picture signal processing unit - Google Patents

Abstract

PURPOSE:To eliminate the need for a 1H line memory in the picture processing unit applying picture processing to picture data with picture data at an interval of 1H. CONSTITUTION:Picture data are read in zigzag over two horizontal lines by an R/W control circuit 2 from a picture memory 1. Then read picture data are picture data delayed by 1H on two horizontal lines. The picture data are fed to a latch circuit 3 and latched therein and the picture data outputted from the latch circuit 3 and the picture data read from the picture memory 1 are applied simultaneously to a picture processing circuit 4 to apply picture processing to the photocoupler data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for performing various image processing using image data read out from an image memory, and particularly to image data processing which does not require real-time image processing. It is suitable for application to processing.

[0002]

2. Description of the Related Art FIG. 9 shows an example of a block diagram of a conventional image processing apparatus, and FIG. 8 shows the sequence of reading image data from an image memory at this time. In FIG. 9, 101 is an image memory for writing / reading one frame of image data, 102 is an R / W control circuit for controlling writing / reading of the image memory 101, and 103 is delaying the image data by one horizontal line period. 1H delay circuit, 104
Is an image processing circuit for performing various image processing by performing signal processing of the data read from the image memory 101 and the image data delayed by one horizontal line period.

The R / W control circuit 102 of the image processing apparatus shown in this figure sequentially reads out image data from each pixel area of the image memory 101 in the horizontal line direction as shown in FIG. Then, the read image data is delayed by the 1H delay circuit 103 for one horizontal period, and the image memory 1
Image processing circuit 1 together with the image data read from 01
04 is applied.

In the image processing circuit 104, for example, the processing for enhancing the contour of the image is performed, and the processed image data is output. The 1H delay circuit that delays the image data by one horizontal period is composed of, for example, a one-line memory composed of a DRAM, and this one-line memory is an NTS.
In the case of the C method, a 910-stage DRAM is usually used.

Next, the principle of image processing for carrying out edge enhancement from two image data will be described with reference to the waveform diagram of FIG. In this figure, (a) is image data A read from the image memory, (b) is image data B delayed by one horizontal period,
(C) shows data C obtained by subtracting image data B from image data A, and (d) shows image data D obtained by adding data C to image data A.

As shown in FIG. 10, when the image data B is subtracted from the image data A, the edge of the image data A can be detected. The data of this edge is the data of C shown in FIG. 7C, and when this data C is added to the image data A, the image data D in which the edge portion of the image data A, that is, the contour is emphasized is obtained. Therefore, when image processing is performed with such a 1H delay, vertical aperture correction can be performed. In order to emphasize the contour of the image, the processing can be performed by using the two pieces of image data as described above, but if the three pieces of image data are used, a more preferable contour emphasis processing can be performed.

FIG. 11 shows an image processing apparatus using three image data, and its operation waveform is shown in FIG. In FIG. 11, 101 is an image memory for writing / reading image data, and 102 is a writing / reading of the image memory 101.
An R / W control circuit for controlling reading, 103-1 is a 1H delay circuit for delaying image data for one horizontal line period, 10
3-2 is a 1H delay circuit that delays the image data cascade-connected to the 1H delay circuit 103-1 for one horizontal period, and 104 is the input data read from the image memory 101 and 1
An image processing circuit that performs image processing using a total of three pieces of image data delayed by horizontal line periods.

The R / W control circuit of the image processing apparatus shown in FIG. 11 sequentially reads the image data in the horizontal line direction as shown in FIG. This read image data is sequentially delayed by 1H delay circuits 103-1 and 103-2,
The image data output from the delay circuit 103-2 is delayed from the image data read from the image memory 101 by two horizontal line periods.

The delayed image data is shown in FIGS. 12 (a) to 12 (c). That is, (a) is the image data A read from the image memory 101, and (b) is 1H.
The image data B and (c) output from the delay circuit 103-1 delayed by one horizontal line period are the 1H delay circuit 103-
2 shows image data C delayed by two horizontal line periods output from No. 2.

In this way, the delayed image data A,
When B and C are applied to the image processing circuit 104, the image processing circuit 104 subtracts the image data A from the image data A, and the data D shown in FIG. The data E shown in (e) is calculated. Then, the calculated data D and E are added to the image data A to obtain the image data F shown in FIG. As shown in FIG. 12, the image data F is edge-enhanced so that both the rising edge and the falling edge of the image data have the same waveform. Therefore, according to the image processing apparatus shown in FIG. This means that contour enhancement is performed better than that of the image processing apparatus shown in FIG.

[0011]

There is a system for transferring an image processed by the image processing apparatus as described above to, for example, a personal computer or the like. However, when transferring the image to a personal computer or the like, the operation of the image processing apparatus is temporarily stopped. Image data needs to be transferred. However, since the above-described image processing apparatus is premised on real-time operation, if the 1H delay circuit is composed of, for example, a 910-stage DRAM or the like, the image in the 1H delay circuit is temporarily stopped when the operation of the image processing apparatus is stopped. There was a problem that the data was lost and the image data had to be input again.

Further, since the 1H delay circuit has a scale of 910 stages, there is a problem that the number of gates is increased when the image processing apparatus is integrated into an IC and a problem is likely to occur. Therefore, it is an object of the present invention to provide an image processing apparatus which does not need to be re-inputted with image data even if the operation of the image processing circuit is temporarily stopped and does not increase in size even if the image processing circuit is integrated.

[0013]

In order to achieve the above object, the image processing apparatus of the present invention eliminates the need for a 1H line memory and reads image data from the image memory in a zigzag pattern over a plurality of horizontal lines. However, the read image data is held by a latch circuit including a flip-flop, for example.

[0014]

[Operation] Since the image data can be read in a zigzag pattern from the image memory across a plurality of horizontal lines,
The 1H delay circuit composed of the 1H line memory can be dispensed with simply by adding the latch circuit. Therefore,
Even if the image processing is interrupted midway, the image data being delayed is not lost. Further, since the 1H line memory having a large number of gates can be dispensed with, the circuit scale of the image processing circuit can be reduced, which is advantageous in terms of cost, power consumption, mounting area and IC.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an example of the order of reading image data from the image memory 1 in the image processing apparatus of the present invention.
In the present invention, for example, as shown in FIG. 1, each pixel of the image memory 1 is read in zigzag image data across two horizontal lines. When the image data is read from the image memory 1 in this way, the image data is 1
It can be seen that the data is read every horizontal line.

Therefore, the image data thus read is held by using a latch circuit for latching the data for one clock period, so that two image data for every one horizontal line are obtained. FIG. 2 shows a block diagram of an image processing apparatus of the present invention which performs such an operation. In this figure, 1 is an image memory in which 1 field or 1 frame of image data is stored, 2 is an R / W control circuit for controlling writing / reading of the image memory 1, and 3 is an image when a clock is input. A latch circuit that holds data, for example, a flip-flop, 4 is an image processing circuit that receives two image data every other horizontal line and performs image processing, and 5 is an R / W control circuit 2, a latch circuit 3, and an image processing circuit. Clocks CK0, CK1, CK2 applied to the circuit 4
Is a timing generator that generates

Image data is read from the image memory 1 of the image processing apparatus shown in FIG. 2 by the R / W control circuit 2 at the timing of the clock CK0 as shown in FIG.
The read image data is applied to the latch circuit 3 corresponding to the number of bits of the image data, which is composed of, for example, a plurality of flip-flops, and is held at the timing of the clock CK1. The image data held by the latch circuit 3 and the image data read from the image memory 1 are applied to the image processing circuit 4, and the image processing is performed at the timing of the clock CK2 different from the clock CK1. This timing is shown in FIG. 4, and the arrangement of the read data on the image memory 1 is shown in FIG.

In FIG. 3, the first raster of the image memory 1 is
In the image data a₁ , A₂ , A₃ ... is horizontal
Image data on the second line.
Data b1, b2, b₃ Are arranged in the horizontal line direction
ing. Further, the image data c is added to the third line.₁ ，
c₂ , C₃ ... are arranged in the horizontal line direction.
 From such an image memory 1 as shown in FIG.
The R / W control circuit 2 shows
When the image data is read in zigzag as shown in 1,
Image data a as shown in FIG.₁ , B₁ , A₂ ，
b₂ , A₃ , B ₃ ... and the first line and the second
The image data with the line is read alternately.

Then, the clock CK1 shown in FIG.
Image data a ₁ , a of the _first line at the timing of
_{When 2} , ₂ , a ₃ ... Are held in the latch circuit 3, the held data are image data a ₁ , a as shown in FIG.
₂ , a ₃ ... At the timing of the clock CK2, the image data b ₁ , b ₂ , b ₃ ... Are read from the image memory 1 and the image is read from the latch circuit 3 as shown by the dotted line in FIG. Data a ₁ , a ₂ , a ₃
... is output, the image processing circuit 4 that captures image data at the timing of the clock CK2
Image data a ₁ and b ₁ , image data a ₂ and b _2, ...

Therefore, first, the image processing circuit 4 fetches the image data a ₁ and the image data b ₁ which are equivalent to the case of delaying by one horizontal line, and the image data of the edge emphasis image processing as shown in FIG. Image processing circuit 4 applied to
Is output from. Next, the image processing circuit 4 takes in the image data a ₂ and the image data b ₂ and performs similar image processing. Such image processing is performed one after another to process one field or one frame of image data.

The timing generator 5 delays the clock pulse of the clock CK0 generated from, for example, a crystal oscillator by 180 degrees and distributes the delayed clock pulse for each one to generate the clock CK1 and the clock C.
K2 has occurred. In the image processing apparatus shown in FIG. 2, even if the image processing is interrupted due to data transfer or the like during processing, the 1H line memory is not used and the image data being delayed is lost. There is nothing to do. After the interruption, the R / W control circuit 2 regenerates the necessary image data from the image memory 1 to the image data shown in FIG.
It is sufficient to read out and perform image processing as shown in FIG.

Next, FIG. 5 shows a block diagram of another image processing apparatus for performing the edge enhancement as shown in FIG. 12, for example, using the three image data. In this figure, 1 is an image memory in which image data of 1 field or 1 frame is stored, 2 is an R / W control circuit for controlling writing / reading of the image memory 1, and 3-1 and 3-2 are pixels. Latch circuit for holding minute image data, 4 is an image processing circuit for receiving three image data every other horizontal line and performing image processing, 5 is R / W control circuit 2 and latch circuits 3-1 and 3
-2 and clocks CK0 and CK applied to the image processing circuit
1 is a timing generator for generating CK2.

In this embodiment, for example, as shown in FIG. 6, the image data is read from the image memory 1 in a zigzag pattern over three horizontal lines. It can be seen that when the image data is read from the image memory 1 in this way, the image data is read every other horizontal line. Therefore, the image data thus read is held by the two latch circuits 3-1 and 3-2, respectively, so that three pieces of image data for every one horizontal line are obtained.

A timing chart of such operation is shown in FIG. In this figure, (a) is the clock CK0 applied to the R / W control circuit generated from the timing generator 5, and (b) is the R / W of the image data arranged in the image memory 1 as shown in FIG. Image data read by the control circuit 2, (c) is a clock CK1 which is a timing at which the latch circuits 3-1 and 3-2 hold the image data,
(D) is the image data held in the latch circuit 3-1, (e) is the image data held in the latch circuit 3-2, and (f) is the timing at which the image processing circuit 4 performs image processing. The clock CK2 is shown.

Image data is read from the image memory 1 of the image processing apparatus shown in FIG. 5 by the R / W control circuit 2 as shown in FIG. The read image data is applied to the latch circuit 3-1 and held at the timing of the clock CK1. The image data read next is applied to the latch circuit 3-1 and held at the timing of the clock CK1. At the same time, the image data held in the latch circuit 3-1 is held by the latch circuit 3-2. Become so. The image data held by the latch circuit 3-1 and the latch circuit 3-2 and the image data read from the image data are applied to the image processing circuit 4, and a clock CK1 generated from the timing generator 5 is generated. Image processing is performed at the timing of the clock CK2 at different timing.

That is, when the R / W control circuit 2 reads the image data in zigzag form from the image memory 1 in which the image data is arranged as shown in FIG. 3,
As shown in FIG. 7B, image data a ₁ , b ₁ , c ₁ ,
a ₂ , b ₂ , c ₂ , ... And one image data from the first line, the second line and the third line,
It is sequentially read at the timing of the clock CK0 shown in FIG.

Then, the clock CK1 shown in FIG.
The latch circuit 3-1 holds the first read image data a ₁ at the timing of, and the latch circuit 3-1 holds the next read image data b ₁ at the timing of the next clock CK1. To do. At this time, since the clock CK1 is also applied to the latch circuit 3-2, the latch circuit 3-2
Holds the image data a ₁ which is the output held by the latch circuit 3-1.

As shown in FIG. 3C, the clock CK1 is generated from the timing generator 5 at the timing of outputting two and resting one, so that the latch circuit 3
-1 indicates the image data a ₁ , b as shown in FIG.
₁ , a ₂ , b ₂ ... Are sequentially held. Since the latch circuit 3-2 holds the image data held by the latch circuit 3-1 with the clock CK1 delayed by one clock,
Image data a _1, which holds the output from 1 clock CK1 delayed latch circuit _{3-1, b 1, a 2,} b sequentially made to hold the ₂ ....

Further, at the timing of the clock CK2, as shown by the dotted line in FIG. 7, the image data c ₁ , c _2, ... Are read from the image memory 1, and the latch circuit 3-1 is used. Output image data b ₁ , b ₂ , ... And further, the latch circuit 3-2 outputs the image data a.
_1, a _2, since ... is outputted, the image processing circuit 4 for taking an image data at the timing of the clock CK2, the image data a ₁ and b ₁ and c ₁ at the timing of the first clock CK2, Image data a ₂ , b ₂ and c ₂ are simultaneously captured at the timing of the next clock CK2.

Therefore, the image data a ₁ , the image data b _1, and the image data c ₁ which are equivalent to being delayed by one horizontal line are fetched into the image processing circuit 4, for example, as shown in FIG.
The image processing of contour enhancement as shown in (1) is applied to the image data and output from the image processing circuit 4. Next, the image processing circuit 4
Includes image data a ₂ , image data b _2, and image data c _2.
And are captured and similar image processing is performed. Such image processing is performed one after another to process one field or one frame of image data. Latch circuit 3-
1, 3-2 are composed of a plurality of flip-flops corresponding to the number of bits of image data, for example. In addition,
The image processing performed on the image data by the image processing circuit 4 is not limited to edge enhancement, but may be horizontal line interpolation processing or processing for softening the image.

[0031]

Since the present invention is configured as described above, it is possible to read image data from the image memory in a zigzag pattern over a plurality of horizontal lines, so that a 1H line memory is used only by using a latch circuit. The 1H delay circuit can be dispensed with. Therefore, even if the image processing is interrupted midway, the image data being delayed is not lost. Further, since the 1H line memory having a large number of gates can be dispensed with, the circuit scale of the image processing circuit can be reduced, which is advantageous in terms of cost, power consumption, mounting area and IC.

[Brief description of drawings]

FIG. 1 is a diagram showing an order of reading image data from an image memory in the present invention.

FIG. 2 is a block diagram of an image processing apparatus of the present invention.

FIG. 3 is a layout diagram of image data in an image memory.

FIG. 4 is a timing diagram of the image processing apparatus of the present invention.

FIG. 5 is a block diagram of another image processing apparatus of the present invention.

FIG. 6 is a diagram showing another order of reading image data from the image memory in the present invention.

FIG. 7 is a timing diagram of another image processing apparatus of the present invention.

FIG. 8 is a diagram showing a conventional order of reading image data from an image memory.

FIG. 9 is a block diagram of a conventional image data processing device.

FIG. 10 is an operation waveform diagram in which edge enhancement is performed by the image processing circuit.

FIG. 11 is another block diagram of a conventional image data processing device.

FIG. 12 is an operation waveform diagram in which contour enhancement is performed by another image processing circuit.

[Explanation of symbols]

 1,101 Image memory 2,102 R / W control circuit 3,3-1,3-2 Latch circuit 4,104 Image processing circuit 5 Timing generator 103,103-1,103-21 1H delay circuit CK0, CK1, CK2 clock

Claims (4)

[Claims] 1. An image memory, an R / W control circuit for controlling writing / reading of the image memory, and at least one holding circuit for sequentially holding image data of one pixel read from the image memory. The image data read from the image memory and the image data held by the holding circuit are input, and an image processing circuit that processes the image data is provided, and the R / W control circuit is the image memory. By reading the above pixel data in a zigzag pattern over at least two horizontal lines, a plurality of image data input to the image processing circuit is made image data having a correlation in each horizontal line period. An image signal processing device characterized in that. 2. The holding circuit is one, and the R / W
2. The image signal processing apparatus according to claim 1, wherein the control circuit reads the image data from the image memory in a zigzag pattern across two horizontal lines. 3. The R / W, wherein the number of holding circuits is two.
The image signal processing apparatus according to claim 1, wherein the control circuit reads the image data from the image memory in a zigzag pattern over three horizontal lines. 4. The image processing circuit according to claim 1, wherein the image processing circuit uses the input image data delayed by one horizontal line period to perform edge enhancement processing on the image. The image signal processing device according to.