JPH0282791A - Video signal processor - Google Patents

Abstract

PURPOSE:To execute a processing without the phase disorder of a chrominance signal in a dynamic mode as well by discriminating the coincidence/ noncoincidence between the phase information of the chrominance signal of a previously processed frame and the phase information of a frame to be supplied, and controlling the frame to be processed. CONSTITUTION:A means 10, which stores the phase information of the chrominance signal of the previously processed frame and determines the phase to be next processed, and a means 11, which discriminates the phase of the chrominance signal of the frame supplied at the time of the completion of the processing and processes the frame when the phase is coincident to the determined phase or processes the next frame at the time of noncoincidence, are provided. Further, the coincidence/noncoincidence between the phase information of the chrominance signal of the previously processed frame and the phase information of the frame to be supplied is discriminated, and the frame to be processed is controlled. Thus, the processing without the phase disorder of the chrominance signal can be executed even in the dynamic mode.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal processing device that digitizes a video signal and performs various processing.

[Summary of the invention]

The present invention relates to a video signal processing device, and relates to a video signal processing device that determines the phase of a color signal of a frame to be processed when processing an NTSC signal, controls the next frame to be processed, and discontinuities in the color signal of the processed signal. This is to prevent this from occurring.

[Conventional technology]

The applicant of this application first proposed a video signal (information) processing device that digitizes video signals and performs various processing (Japanese Patent Laid-Open No. 6
2-109179, JP-A-62-118486, etc.).

In such devices, processing is performed, for example, for each frame of the video signal, but the processing time is divided into a fixed mode that is estimated and set in advance, and a dynamic mode that processes the next frame every time processing is completed. Broadly classified.

In dynamic mode processing, the timing of capturing the next frame to be processed (writing it to memory) is undefined, but a circuit as shown in Figure 3 has been considered as a means of controlling this. . In the figure, (31)
<32) is a D flip-flop, and these flip-flops (31) and (32) are connected in series, and the power supply voltage Vc is connected to the D input of the flip-flop (31).
c is supplied, and a signal OK indicating the end of processing in a processing circuit (not shown) is supplied to the clock input. Further, the reset input of the flip-flop (31) is supplied with a signal FRL that is at a low potential only for one horizontal period at the beginning of each frame, and the clock input of the flip-flop (32) is supplied with a signal FLID that is inverted for each field. .

Therefore, in this circuit, when the signals shown in FIGS. 4A to 4D are supplied, the waveforms of each part are as shown in FIG. 4E.

As shown in F, a signal Q2 corresponding to one frame after the OK signal is taken out from the Q output of the flip-flop (32). This signal Q2 is then transmitted to the signal generation circuit (33
) for alternately writing captured frames as shown in FIG. 1 to two memories (not shown). WE2 and a signal R3 for starting processing to the processing circuit are generated.

[Problem to be solved by the invention]

By the way, in a so-called NTSC system color video signal, the phase of the color signal in the video signal returns to its original state every 2 frames=4 fields.

So, looking at the above circuit, when compared with the signal FMID (see Figure 4B) which is inverted every frame, the captured signal is rQJ rQJ rQJrl,...
+ ro'', and the phases that should originally be alternate are disturbed. Therefore, even if such a signal is processed, when it is supplied to a receiver, there is a risk that the colors will be distorted (colors will not appear).

Note that in fixed mode processing, the processing time is 1.
3, 5, 7... It is possible to maintain the continuity of the phase of the color signal by using frames, but since the processing time is unstable in dynamic mode processing, it is possible to mechanically maintain the continuity of the phase. Can't keep it.

This application was filed in view of these points.

[Means to solve the problem]

The present invention provides means for storing phase information of the color signal of the previously processed frame and determining the phase to be processed next when digitizing and processing an NTSC color video signal frame by frame. Then, the phase of the color signal of the frame supplied at the end of the above processing is determined, and when this phase matches the determined phase, that frame is processed, or when it does not match, the next frame is processed. The video signal processing apparatus is provided with means OD for performing the following steps.

[Effect]

According to this, since the frame to be processed is controlled by determining whether the phase information of the color signal of the previously processed frame and the phase information of the supplied frame match or do not match, the phase of the color signal even in dynamic mode. Processing can be performed without any disturbance.

〔Example〕

In FIG. 1, (1) to (5) are D flip-flops, of which flip-flops (1) to (3) are connected in cascade, and the D flip-flop of flip-flop (1) is connected in series.
A power supply voltage Vcc is supplied to the input, and a signal OK indicating the end of processing in a processing circuit (not shown) is supplied to the clock input. Furthermore, the reset input of the flip-flop (1) is supplied with a signal FRL that is at a low potential only for one horizontal period at the beginning of each frame, and the clock input of the flip-flops (2) and (3) is supplied with a signal FLID that is inverted for each field.
At the same time, a reset signal IBRDY for the entire device is supplied to the reset terminals of the flip-flops (2) and (3).

Further, the D input of the flip-flop (4) is supplied with a signal FMID that is inverted every frame and indicates the phase information of the color signal, and the inverted output signal Q of the flip-flop (1) is supplied to the D input of the flip-flop (4) and (5). Supplied to clock input. Furthermore, the above-mentioned signal tBRDY is connected to the flip-flop (4
)(5), and the output signal Q5 of the flip-flop (5) is fed back to the D input.

Therefore, in this circuit, when the signals shown in Figure 2A-H are supplied, the waveforms of each part become as shown in Figures F-J, and the Q output of the flip-flop (2) < i) is The signal Q2.corresponds to one frame after the signal OK and the next one frame, respectively. Q3 is taken out. Also, from the Q output of the flip-flop (4), a signal Q4 indicating the phase of the signal FMID of the frame after the signal OK is taken out, and the Q output of the flip-flop (5) is inverted at the beginning of the frame after the signal OK. A signal Q5 is taken out.

Therefore, these signals Q4. Q5 is exclusive (E
X) By being supplied to the OR circuit (6), the circuit (6
) is taken out as a signal SEL which becomes high potential when the phases do not match, as shown in K in the figure. - force signal Q2. Q3
is supplied to the selector (7), and this selector (7) is switched by the above-mentioned signal SEL, so that the selector (7) outputs a frame in which the phase of the signal PMIO is alternately inverted as shown in the figure. A corresponding signal 0 is taken out.

By supplying this signal 0 to the signal generating circuit (8), the captured frames are transferred to two memories (not shown) as shown in M to 0 in the figure.

Write control signals WEI and WE2 for writing to the memory and a signal R3 for starting processing to the processing circuit are generated.

In this way, according to the above-mentioned device, since the frame to be processed is controlled by determining whether the phase information of the color signal of the previously processed frame and the phase information of the supplied frame match or do not match, the color signal even in the dynamic mode is controlled. signal phase,
Processing can be performed without any disturbance.

That is, a processing frame determining means side is provided, and by providing a means 00 for controlling the frame to be taken in by a signal from this means (II), a memory (not shown) stores frames in which the phase of the color signal is sequentially inverted. The phase of the color signal after being captured and processed is continuous.

C. Effects of the invention] According to the invention, since the frames to be processed are controlled by determining whether the phase information of the color signal of the previously processed frame and the phase information of the supplied frame match or do not match, the dynamic mode Also, processing can be performed without disturbing the phase of color signals and signals.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an example of the present invention, FIG. 2 is a diagram for explaining the same, and FIGS. 3 and 4 are diagrams for explaining the conventional technology. (1) to (5) are D flip-flops, (6) is an exclusive OR circuit, (7) is a selector, and (8) is a signal generation circuit.

Claims (1)

[Claims] When digitizing and processing an NTSC color video signal frame by frame, means for storing phase information of the color signal of the previously processed frame and determining the phase to be processed next; means for determining the phase of the color signal of the frame supplied at the end, and controlling the frame to be processed if the phase matches the determined phase, or to process the next frame if the phase does not match the determined phase; A video signal processing device is provided.