JP2000295634A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processor that starts a loopback from an optional position in the case of a color difference signal configuring a 4:1:1 signal and outputs a normal mirror image where left and right colors around the loopback position are not inverted. SOLUTION: This image processor has mirror processing circuits 99, 100 that respectively apply mirror processing to a luminance signal and color difference signals configuring a 4:1:1 signal. The mirror processing circuit 99 and 100 is provided with a storage means 101 that stores the received color difference signal, a constant generating means 108 that produces a constant required for distributing the color difference signal, an interpolation arithmetic means 107 applies an interpolation arithmetic operation to the color difference signal depending on the constant, means 102, 103 that respectively generate a write address and a read address to the storage means 101 respectively, a means 105 that sets a write range of the color difference signal to be stored in the storage means 101, and a read direction control means 104 that controls increase/decrease in the address generated from the address generating means 103.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generates an image in which one half of an image is folded back to the other half, that is, a mirror-symmetric image (hereinafter, referred to as a mirror image) as one of editing processes for image data. The present invention relates to an image processing apparatus for performing the above.

[0002]

2. Description of the Related Art As one of image editing processes for obtaining a special effect, there is image processing for generating a mirror image (hereinafter, referred to as a mirror process). In this mirror process,
For example, mirror processing is performed on the image shown in FIG. 15A to obtain a mirror image having a mirror image of right and left mirror symmetry as shown in FIG.

Conventionally, as an image processing apparatus for performing such mirror processing, for example, there is one having a configuration as shown in FIG. 16 (see, for example, JP-A-61-73485 and JP-A-4-329777). ).

A conventional image processing apparatus for performing a mirror process shown in FIG. 16 uses, for example, a 4: 1: 1 signal obtained by digitizing an analog video signal obtained by interlaced scanning or sequential scanning from a solid-state image sensor. Mirror processing is performed on the component signal called.

As shown in FIG. 17, the above 4: 1: 1 signal is composed of a luminance signal (open circles in the figure) and each of the color difference signals Cr (black circles in the figure) and Cb (braided in the figure). Color difference signals (Cr, Cb) for digitizing analog video signals
The sampling frequency of is as shown in FIGS.
Since it is set to 1/4 of the sampling frequency for the luminance signal (therefore, the color difference signal for the luminance signal
(The sampling period of (Cr, Cb) is four times.) In order to compensate for the lack of the data amount of the chrominance signal with respect to the luminance signal, as shown in FIG. The signal S1 is multiplexed alternately and generated as a set of four pixels (see FIG. 19B).

[0006] Such a 4: 1: 1 signal is input to the image processing apparatus shown in FIG. 16 in a form separated into a luminance signal S3 and a color difference signal S1.

Therefore, the conventional image processing apparatus shown in FIG. 16 includes a circuit 9 for performing a mirror process on an input luminance signal S3 and a circuit 10 for performing a mirror process on an input color difference signal S1. Are juxtaposed.

Each of the mirror processing circuits 9 and 10 has basically the same configuration, and both circuits 9 and 10 have a line memory 11, a write address generation circuit 12, a read address generation circuit 13, and a read operation. A direction control circuit 14 is provided. When the number of pixels for one line of the image shown in FIG. 15A is “n”, the line memory 11 allocates an address space from “0” to “m−1” (n <m). have.

FIG. 18 is an explanatory diagram of the operation of the write address generation circuit 12 and the read address generation circuit 13 described above.

First, in the first one scanning period, the write address generation circuit 12 increases the write address from the initial value “0” to “(n / 2) −1”, and FIG.
Is stored in the line memory 11 in the left half of one line.
To memorize.

In the next one scanning period, the read address generating circuit 13 gradually increases the read address from the initial value "0", and the read address is written one scan period (1H period) earlier in FIG. Data a1 in the left half of the image is read from the line memory 11.

Then, the read direction control circuit 14 calculates the read address generated by the read address generating circuit 13 and the address at the end of writing (= n / 2) 1H period earlier.
-1), and when they match, thereafter, the read address generation circuit 13 performs control so as to decrease the read address. Therefore, the read address gradually decreases from (n / 2) -1 to the initial value (= 0). As a result, the right half of one line is an image obtained by folding the left half.

During the above-described read operation, the write address generating circuit 12 increases the write address from the initial value (n / 2) to (n-1) in parallel with the read operation, and sets the write address to the left of the next line. The half data a2 is written into the line memory 11.

FIG. 19 is a timing chart showing the state of each signal associated with the above-described data write and read operations. Here, for ease of understanding, a case where n = 16 is described, but n is actually a larger value (for example, n = 1024).

Assuming that the turning position of the mirror processing is P ₁ and the luminance signal S 3 and the color difference signal S 1 are inputted as shown in FIGS.
,.., 7 are generated from the write address generation circuit 12 as shown in FIG. Also, from the read address generation circuit 13, as shown in FIG.
.., 1 and 0 are generated.

Therefore, the mirror processing circuit 9 for the input luminance signal S3 outputs, as shown in FIG.
The luminance signal S3 is Y0, Y1,... Y7, Y7, Y6,.
It is mirrored and output as Y0. Similarly, from the mirror processing circuit 10 for the input color difference signal S1, the color difference signal S2 is changed to Cr0, Cb0,
.., Cr4, Cb4, Cb4, Cr4,..., Cb0, Cr0 are mirror-processed and output.

The chrominance signal S2, which has been mirror-processed by the mirror processing circuit 10, is processed by a chrominance signal extraction pulse as shown in FIG. The color difference signal is extracted,
As shown in FIGS. 17 (b) and 17 (c), by distributing them at positions separated by four pixels, a colored mirror image as shown in FIG. 15 (b) is obtained.

[0018]

As described above, FIG.
In the conventional image processing apparatus shown in FIG. 1, both mirror processing circuits 9 and 10 have the same configuration, and the input color difference signal S
1 is also subjected to mirror processing of exactly the same content as the input luminance signal S3.

For this reason, when an image is colored based on the color difference signal, the color of the right half image is displayed differently from the color of the left half image, or the image is not colored according to the outline of the image based on the luminance signal. In some cases, a normal mirror image is not displayed, for example, a shift occurs between the outline and the color. Hereinafter, the reason will be described with reference to FIG.

The luminance signal S input to the mirror processing circuit 9
3 is entered in units of one pixel, and, because it is displayed in even one pixel unit luminance signal S4 after the mirror treatment, as can be seen from FIG. (E), the luminance symmetrically around a folding position P ₁ The signals are arranged, and a mirror image having an outline that does not cause any trouble even when an image based on the luminance signal is displayed is obtained.

On the other hand, the color difference signal S1 (see FIG. 3B) input to the mirror processing circuit 10 is a signal in which a Cr signal and a Cb signal are alternately multiplexed and four pixels are set. Has been generated as. For this reason, when coloring an image based on the color difference signal S2 (see (f) in the figure) output after the mirror processing, such a luminance signal and a color difference signal of 4:
In order to maintain a sampling frequency ratio of 1: 1 as described above, a processing circuit (not shown) at a subsequent stage
The respective color difference signals of Cr and Cb are extracted in units of four pixels by the color difference signal extraction pulse shown in FIG.

[0022] That is, the color difference signal extraction pulse color difference signals Cr, Cb are extracted in the period of the high level, the result is compared with the and the color difference signal S2 a luminance signal S4 which is mirrored, from the return position P ₁ Also the left luminance signal Y
Corresponding to the position of 0 Cr0 and Cb0 and are extracted, Cr4 and the Cb4 corresponding to the position of Y4 is extracted, also, than return position P ₁ corresponding to the positions of the right of the luminance signal Y7 Cb4 And Cr4 are extracted, and C3 corresponding to the position of Y3 is extracted.
b0 and Cr0 are extracted. Moreover, the extraction sequence in this case, C Cr component in the preceding on the left side than the turning point P ₁
b0 component there later, whereas, on the right side than the return position P _1, Cb component is in later Cr component in the previous.

[0023] Here, when focusing on the relationship of the color difference signals to each other in the left and right equidistant from the return position P _1, a position from the return position P ₁ away four pixels to the left, that is, the position of the luminance signal Y4 is Cr4, a Cb4 the extraction pulse is present, a position from the return position P ₁ away four pixels to the right, i.e. the folded position of the luminance signal Y4 is
There is no chrominance signal extracting pulses, further 1 pixel right, i.e. in a position away 5 pixels from the return position P ₁ Cb0, C
There is an extraction pulse of r0. And this Cb0,
Components of Cr0 from return position P ₁ it becomes the same as the Cb0, Cr0 the component corresponding to the luminance signal Y0 away 8 pixels to the left, not the prorated value according to the distance between pixels. That is, not disposed is substantially a signal having the same chrominance component at a position apart by substantially the same number of pixels to the left and right from the folding position P _1, Therefore, the shift to the contours and coloring of the image based on the luminance signal generated .

Further, as described above, the turning position P ₁
The extraction order of the chrominance signal is reversed between left and right. That is, while Cr is extracted after Cb is extracted on the left, Cr is extracted after Cb is extracted on the right. The Cb pixel is located at the position of the pixel, and the color in the right half is inverted from the color in the left half.

Further, in the mirror process is not intended to return position is fixed to the P ₁ position, there is also a demand to be able to arbitrarily change the return position.

[0026] In the case in order to respond to this request, for example, a folded position was changed to P _2, the folded position P ₂ is,
It is not the position of the break of the color difference signal that is a set of four pixels,
It is set at a position in the middle of four pixels as one set. In this case, the write address generation circuit 12 and the read address generation circuit 13 generate addresses as shown in FIGS. 3 (g) and 3 (h), so that the color difference signal S2 which is mirror-processed and output by the mirror processing circuit 10 is The result is as shown in FIG.

In this case, signals having substantially the same color difference components are arranged at positions substantially the same number of pixels to the left and right from the turning position P _2, but the turning position is set to P.
As if set to _1, the extraction order of the color difference signals at the left and right folding position P ₂ are reversed, folding start position P ₂
Since the addition of color is reversed in the right and left, and the color difference signals before and after the turn-back start position P ₂ is extracted subsequently with CR8 → CR8, color difference signal having a Cb component is not extracted,
The ratio 4: 1: 1 of the sampling frequency of the luminance signal and the color difference signal (Cr, Cb) is lost.

As described above, in the conventional image processing apparatus, the folding position cannot be arbitrarily set variably in units of one pixel.

In order to eliminate the above-mentioned inconvenience, for example, it is conceivable to configure a circuit that performs mirror processing on each of the Cr component signal and the Cb component signal without multiplexing the color difference signals. With such a configuration,
Since a processing circuit is required for each system, the circuit scale unnecessarily increases, which is not preferable.

The present invention is to solve the above-mentioned conventional problem, and it is possible to start folding back a color difference signal constituting a 4: 1: 1 signal from an arbitrary position. It is an object of the present invention to provide an image processing apparatus capable of outputting a normal mirror image in which the left and right colors around the image are not inverted.

[0031]

According to the present invention, there is provided an image processing apparatus for performing a mirror process on an input 4: 1: 1 signal as follows.

That is, according to the present invention, there is provided a mirror processing circuit for individually performing mirror processing on a luminance signal and a color difference signal constituting a 4: 1: 1 signal. The circuit includes a storage unit for storing the input color difference signal, a constant generation unit for generating a constant for distributing the color difference signal, and an interpolation operation corresponding to the constant generated by the constant generation unit for the color difference signal. , A write address generation means for generating a write address for the storage means, a read address generation means for generating a read address for the storage means, and a setting of a color difference signal writing range to be stored in the storage means A write range setting means for controlling the increase and decrease of addresses generated by the read address generation means. Reading direction control means, wherein the constant generating means generates a constant according to a range of an input video signal to be stored in the storage means and an address increase / decrease control of the reading direction control circuit for the read address generating circuit. Like that.

As a result, 4:
When a color difference signal of 1: 1 signal is read, data read control linked to the writing range and interpolation calculation for the read data are performed. On the other hand, it is possible to output an appropriate mirror image that can start folding from an arbitrary position, does not invert the color of the right half, and does not cause a shift between the outline and the coloring of the image based on the luminance signal. it can.

[0034]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a basic configuration of a main part of an image processing apparatus according to an embodiment of the present invention.

This image processing apparatus performs a mirror process on the input luminance signal S3, and executes the processed luminance signal S3.
4 and a circuit 100 that performs a mirror process on the input color difference signal S1 and outputs the processed color difference signal S2.

In this embodiment, the mirror processing circuit 99 for the input luminance signal S3 includes a mirror processing circuit 9 having the same configuration as the conventional one shown in FIG. 4T delayed by clock
And a delay circuit 15.

On the other hand, the mirror processing circuit 100 for the input color difference signal S1 has a configuration substantially different from that of the conventional circuit 10.

That is, in FIG. 1, 101 is a line memory as storage means for storing the input video signal S1, and 102 is a write address generation circuit as write address generation means for generating a write address for the line memory 101. , 103 are line memories 10
A read address generation circuit as a read address generation means for generating a read address for 1;
Reference numeral 4 denotes a read direction control circuit as read direction control means for controlling whether the read address generation circuit 103 increases or decreases the read address.

Reference numeral 105 denotes a write range setting circuit as write range setting means for setting a range of write addresses generated by the write address generation circuit 102;
06 is a read range setting circuit that sets a range of read addresses generated by the read address generation circuit 108;
107, an interpolation operation circuit as an interpolation operation means for performing an interpolation operation on the output from the line memory 101; 108, information on a write range set by the write range setting circuit 105; and a read address determined by the read direction control circuit 104 Is a constant generation circuit as constant generation means for generating a constant corresponding thereto based on the information on the increase / decrease direction of the data. Then, the above-described units are connected to the clock signal CLK.
It operates in synchronization with.

FIG. 2 shows an example of the configuration of the write address generation circuit 102.

In the figure, reference numeral 401 denotes a clock signal CL.
A divide-by-4 circuit that outputs a divide-by-4 pulse with respect to the input of K,
Reference numeral 402 denotes a divide-by-2 circuit that outputs a divide-by-2 pulse in response to the input of the clock signal CLK, and 403 denotes an address generation counter that counts up the divide-by-4 pulse generated by the divide-by-4 circuit 401. Both the divide-by-2 circuit 402 and the address generation counter 403 operate only during the period when the write range setting signal Hss is at the high level. Reference numeral 404 denotes a bit combination circuit for combining the bits generated by the address generated by the address generation counter 403 and setting the output generated by the divide-by-2 circuit 402 as lower bits, and outputting the result.

FIG. 3 shows a configuration example of the read address generation circuit 103.

In the figure, reference numeral 601 denotes a divide-by-4 circuit;
2 is a divide-by-2 circuit, 603 is an address generation counter, 60
4 is a bit combination circuit.

The address generation counter 603 performs a count-up operation, a count-down operation, and a hold operation according to a control signal from the read direction control circuit 104. The divide-by-2 circuit 602 and the address generation counter 603 Means that only the read range setting signal Hen operates during the high level period.

The other configuration and operation are the same as those of write address generating circuit 102 shown in FIG. 2, and therefore, detailed description thereof will be omitted.

FIG. 4 shows an example of the configuration of the interpolation operation circuit 107.

The interpolation operation circuit 107 performs a linear interpolation process. In FIG.
A 4T delay circuit 704 for delaying the color difference signal Sa read from 1 by 4 clocks, 704 is a two-time weighting coefficient k,
702a, 702b are the output Sa of the line memory 101 and the 4T delay circuit 701
Multiplier 703 multiplies the output signal Sb by the weighting coefficient powers k and 1-k calculated by the coefficient calculation circuit 704, and 703 adds the output signals of the multipliers 702a and 702b to obtain an interpolation calculation result S
This is an adder that outputs a × k + Sb × (1-k) as a color difference signal S2 after mirror processing.

The operation of the image processing apparatus according to this embodiment configured as described above will be described below.

Here, as the mirror processing, (A)
The number of pixels of the luminance signal in the left half of the mirror image is 4n (n = 1,
(B) when the number of pixels of the luminance signal in the left half of the mirror image is 4n + 1 (n = 0, 1, 2, 3,...), (C) when the mirror image is left The number of pixels of the half luminance signal is 4
When n + 2 (n = 0, 1, 2, 3,...), (D) the number of pixels of the luminance signal in the left half of the mirror image is 4n + 3 (n = 0, 1,
2, 3,...) Will be described.

(A) The mirror image is turned back at P _A ,
That is, the number of pixels of the luminance signal in the left half of the mirror image is 4n.
(n = 1, 2, 3,...) In this case, in order to facilitate understanding, n = 2, that is, the number of pixels of the luminance signal in the left half of the mirror image is 8 The operation will be described on the assumption that there are (= 4 × 2) pixels.

FIG. 5 is a timing chart showing the operation of the write address generation circuit 102, and FIG. 6 is a timing chart for explaining the operation of each circuit when the image processing apparatus performs the mirror processing.

As shown in FIG. 6B, the mirror processing circuit 9
Are input in pixel units such as Y0, Y1, Y2,... For each clock signal CLK, and the mirror-processed luminance signal S4 is also shown in FIG.
As shown in, only 4 are clocks wide delays the color-difference signal S3 is input, the luminance signal symmetrically about the return position P _A is located, a conventional and are well mirrored The image of the contour is obtained.

On the other hand, the write range setting circuit 105 constituting the mirror processing circuit 100 receives the input color difference signal S1.
From the head pixel Cr0 only four pixels than the return position P _A extra Cb8 component outputs a write range setting signal Hss only high-level period resulting in.

The address generation counter 403 constituting the write address generation circuit 102 operates as shown in FIG. 5B in response to the clock CLK input shown in FIG. 402 operates as shown in FIG. 3C, and as a result, the write address output from the bit combination circuit 404 is generated as shown in FIG.
Therefore, of the write addresses, the first start address is "0" and the end address is "5". Then, the write address generated by the write address generation circuit 102 is given to the read direction control circuit 104, and among the write addresses, the first start address (in this case, “0”) and the last end address (this In this case, “5”) is given to the read address generation circuit 103.

Here, "0" is set as the write address.
And "1" alternately twice, "2" and "3" alternately twice,
The reason that "4" and "5" are alternately output twice, respectively, is as follows.

As shown in FIG. 6, the input chrominance signal S1 constituting the 4: 1: 1 signal is generated as a set of four pixels by alternately multiplexing the Cr signal and the Cb signal. Therefore, using the regularity, for example, the color difference signal of the Cr0 component is overwritten at the address “0”, and
This is because if the color difference signal of the Cb0 component is overwritten on the address "1", the data amount can be substantially reduced without changing the content of the color difference signal to be stored in the line memory 101. Further, the folded position despite what is set to P _A, the write address is "4"
And "5" are alternately generated twice, a total of four clocks, from the turn-back position P _{A. The} extra data required for the interpolation calculation by the interpolation calculation circuit 107 described later is secured in advance. It is to keep.

On the other hand, read address generation circuit 103
Starts the generation of the read address one scanning period after the write address generation circuit 102 starts generating the write address.

Also, the read direction control circuit 104
Write end address before scanning period (here "5")
Is compared with the current read address. Control is performed so that the address generation counter 603 included in the read address generation circuit 103 counts up until both match, and counts down after both match.

Therefore, read address generation circuit 1
As shown in FIG. 6 (g), the read address where 03 occurs is in a period in which the write range setting signal Hss is at the high level.
That is, the line memory 101 is sequentially increased from 0, 1, 0, 1, 2, 3, 2, 3, 4, 5, 4, 5 to 4 clocks after the turn-back position P _A , and the line memory 101 is accessed. It gradually decreases as 2,3,2,3 ...

As a result, the color difference signal Sa is output from the line memory 101 as shown in FIG.

The constant generation circuit 108 generates a read address generated by the read address generation circuit 103 based on a logical sum of a control signal from the read direction control circuit 104 and a write range setting signal Hss from the write range setting circuit 105. Is constant, the constant k = 0
Is a constant when the read address changes in a decreasing trend.
k = 1/4 is output. Then, these constants k (= 0,
1/4) is given to the interpolation operation circuit 107.

The interpolation operation circuit 107 includes a constant generation circuit 10
8 using the given constant k from line memory 1
An interpolation operation is performed between the output Sa of No. 01 and the signal Sb obtained by delaying the output Sa by 4T by the 4T delay circuit 701.

In this interpolation operation, a linear interpolation operation is performed from the output of the line memory 101 in FIG. 6H, the output of the 4T delay circuit 401 in FIG. 6I, and the output of the constant generation circuit 108 in FIG. From the adder 703, Sa × k + Sb ×
(1-k) is output. This output is the color difference signal S2 after the mirror processing.

The color difference signal S2 after the mirror processing is shown in FIG.
As shown in (k), on the left side of the folding position P _A , the content is the same as that of the input color difference signal S1 and is totally delayed by four clocks. This is because the constant k output from the constant generation circuit 108 is k = 0 for the color difference signals Cr0 to Cb4 read from the line memory 101, so that only the output Sb of the 4T delay circuit 701 is provided. On the other hand, on the right side of the turning position P _A , the constant ４ (= 1-1 / 4) for the output Sa from the line memory 101 and the constant ／ (= 1−1１ ／) for the output Sb of the 4T delay circuit 701 After multiplication, both are added.

The output signal S2 of the interpolation operation circuit 107 is supplied to a subsequent processing circuit (not shown) by a color difference signal extraction pulse as shown in FIG.
It is extracted in units of four pixels.

Accordingly, when the output chrominance signal S2 obtained by the interpolation operation circuit 107 is compared with the luminance signal S4 after the mirror processing, the result is as shown in FIG.

That is, the luminance signal S4 is, as in the prior art,
An output that has undergone mirror processing is obtained as shown in FIG. In contrast, the color difference signal S2, FIG. (E), (f), the at the left side than the return position P _A, the color difference signals Cr0 and Cb0 to correspond to the position of the luminance signal Y0, luminance Signal Y4
Is the color difference signals Cr4 corresponding to the position of the and Cb4 are respectively extracted, and in the right side from the return position P _A, the luminance signal and color difference signals of 4: 1: 1 in order to keep the sampling frequency ratio, luminance signal Color difference signals are extracted at positions corresponding to the positions of Y7 and Y3. In this case, the luminance signal Y
The color difference signal corresponding to the position 7 is (Cr4 + 3Cr8) / 4.
(Cb4 + 3Cb8) / 4, and the output color difference signal corresponding to the position of the luminance signal Y3 is (Cr0 + 3Cr4) / 4.
(Cb0 + 3Cb4) / 4.

[0069] Here, attention is focused on the relationship between the color difference signals to each other in the same right and left distance from the return position P _A. Now, in the position distant 4 pixels to the left from the return position P _A is present Cr4, Cb4, Cr, a color difference signal Cb is not present at a position distant four pixels to the right, the one further right adjacent, that is, a position from the return position P _a spaced 5 pixels to the right (Cr0 + 3Cr4) / 4 and (Cb0 + 3Cb4) / 4 that is present.

[0070] Now, the color difference signal Cr component corresponding to the luminance signal Y3 of the position from the return position P _A spaced 5 pixels to the right, Cr4 corresponding to the left side of the luminance signal Y4 of the turn-back position P _A and the Y0 and Cr0 (Cr0 + 3)
Cr4) / 4; also, the color difference signals Cb component corresponding to the luminance signal Y3 of the position from the return position P _A spaced 5 pixels to the right, corresponding to the left side of the luminance signal Y4 of the turn-back position P _A and the Y0 Cb4 and Cb0 are proportionally distributed (Cb4
0 + 3Cb4) / 4.

From this, the interpolation operation circuit 107 performs an interpolation operation from the preceding and following color difference signals Cr4, Cb4 and Cr0, Cb0, and obtains and outputs a color difference signal corresponding to the Y3 position of the luminance signal.

[0072] Then, by performing such interpolation calculation, for the color difference signal S2, but not completely symmetrical as luminance signals S4, when around the return position P _A, its return position P _A (Here, (Cr4 + 3Cr8) / 4 corresponding to the luminance signal Y7)
Except for (Cb4 + 3Cb8) / 4 color difference components), signals having substantially the same color difference components are arranged at positions separated by the same number of pixels on the left and right.

Further, as in the prior art, the turning position P _A
The order in which the color difference signals are extracted is not reversed between the left and right sides of the mirror image. can get.

As a result, the right half color is not inverted with respect to the left half color, and the output luminance signal S
A normal mirror image with no color shift is output for No. 4.

(B) When the mirror image is turned back at P _B ,
That is, the number of pixels of the luminance signal in the left half is 4n + 1 (n = 0,
Here, in order to facilitate the understanding, n = 2, that is, the number of pixels of the luminance signal in the left half of the mirror image is 9 (= 4). × 2 +
1) The operation will be described assuming a pixel.

FIG. 8 is a timing chart for explaining the operation of each circuit when performing mirror processing.

FIG. 8 is different from FIG. 6 in that the first point is that the read direction control circuit 10
4, when the folding position is set to P _B, from the time when one scanning period before the write-end address and both addresses by comparing the current read address matches, further four periods of the clock, the read address generator Circuit 103
Is stopped, the output of the address generation counter 603 is stopped and its output is held, and the control is performed so that the address generation counter 603 counts down after elapse of four clocks. Therefore, the read address generation circuit 103
From, as the read address, as shown in FIG.
... Even after the write range setting signal Hss becomes low level after increasing to 2, 3, 4, 5, 4, 5, the values are repeated to 4, 5, 4, 5 and thereafter, 2, 3, 2 , 3, ... decrease.

As a second point, the constant generation circuit 108 configures the read address generation circuit 103 based on the logical sum of the control signal from the read direction control circuit 104 and the write range setting signal Hss from the write range setting circuit 105. The constant k = 0 is output until the address generation counter 603 starts counting down, and the constant k = 3/4 is output from the start of down counting. That is, the constant generation circuit 108 outputs a constant k = 0 at first, but the read address is 4, 5, 4, 5 as shown in FIG.
, From 2, 3, 2, 3,..., K = 3/4 is output thereafter.

The other operations are the same as those in the case of FIG. 6 of (A) described above, and a detailed description thereof will be omitted.

Therefore, the output signal S2 of the interpolation operation circuit 107 is as shown in FIG.

Then, the color difference signal S2 is extracted in four-pixel units by a color difference signal extraction pulse as shown in FIG.

Therefore, when the output color difference signal S2 obtained by the interpolation operation circuit 107 is compared with the luminance signal S4 after the mirror processing, the result is as shown in FIG.

That is, the luminance signal S4 is, as in the prior art,
An output that has undergone mirror processing is obtained as shown in FIG. In contrast, the color difference signal S2, FIG. (E), (f), the at the left side than the turning point P _B, the color difference signals Cr0 and Cb0 to correspond to the position of the luminance signal Y0, luminance Signal Y4
Color difference signals Cr4 corresponding to the position of the and Cb4 are extracted respectively and the color difference signals Cr8 and Cb8 corresponding to the positions of the luminance signal Y8, also in the right side of the turn-back position P _B,
In order to maintain the 4: 1: 1 sampling frequency ratio between the luminance signal and the color difference signal, the color difference signals (Cr8 + 3Cr4) / 4 and (Cb8 + 3Cb4) / 4 correspond to the position of the luminance signal Y5. The color difference signal (Cr4 + 3
(Cr0) / 4 and (Cb4 + 3Cb0) / 4 are extracted.

[0084] Here, attention is focused on the relationship between the color difference signals to each other in the same right and left distance from the folded position P _B. Now, in the position away 5 pixels to the left from the return position P _B is present Cr4, Cb4, Cr, a color difference signal Cb is not present at a position away 5 pixels to the right, the left neighbor, i.e. folded position from P _B at a distance of four pixels to the right (CR8
+ 3Cr4) / 4 and (Cb8 + 3Cb4) / 4. Further, in the position distant 9 pixels to the left from the return position P _B is present Cr0, Cb0, Cr, a color difference signal Cb is not present at a position distant 9 pixels to the right, the left neighbor, i.e. folded position from P _B to 8 pixels away on the right side (Cr4 + 3Cr0) / 4 and (Cb4 + 3Cb0) / 4
Will exist.

[0085] Now, turn-back positions of each color difference signal Cr component and Cb component corresponding to the luminance signal Y5 from P _B position spaced four pixels to the right, left of the luminance signal Y of the turn-back position P _A
(Cr8 + 3Cr4) / 4, (Cb8 + 3Cb) obtained by proportionally distributing Cr8, Cb8 and Cr4, Cr0 corresponding to 8 and Y4.
4) / 4. Each color difference signals Cb and Cr components corresponding the folded position P _B to the luminance signal Y1 of the position apart eight pixels to the right corresponds to the left side of the luminance signal Y4 of the turn-back position P _A and the Y0 Cb4, A value (Cr4 + 3Cr0) / 4 obtained by proportionally distributing Cr4 to Cb0 and Cr0, (Cb4 + 3C
b0) / 4.

Then, the interpolation operation circuit 107 performs such an interpolation operation, whereby the color difference signal S2 is
When around the turn-back position P _B, although not completely symmetrical as luminance signals S4, in its folded position that the close proximity of P _B (here corresponding to the luminance signal Y8 C
Except for the color difference components of r8 and Cb8), signals having substantially the same color difference components are arranged at positions separated by substantially the same number of pixels on the left and right. In addition, since the color difference signal S2 outputs all the Cr signals at the position of the Cr pixel in the right half of the mirror image and all the Cb signals at the position of the Cb pixel, the color inversion of the right half of the mirror image is performed. A normal mirror image having no color shift with respect to the output luminance signal is output.

(C) The mirror image is turned back at P _C ,
That is, the number of pixels of the luminance signal in the left half of the mirror image is 4n.
+2 (n = 0, 1, 2, 3,...) In this case, in order to facilitate understanding, in order to facilitate understanding, n = 2, that is, the pixel of the luminance signal in the left half of the mirror image The number is 10 (= 4 × 2
+2) The operation will be described assuming a pixel.

FIG. 10 is a timing chart for explaining the operation of each circuit when performing the mirror processing.

The operation of FIG. 10 differs from that of FIG.
The first point is that the read direction control circuit 104 compares the write end address one scanning period ago with the current read address, and when the two addresses match, the read address generation circuit 10 is further operated for four clock periods.
The operation of the address generation counter 603 constituting No. 3 is stopped, its output is held, and after the elapse of four clocks, the address generation counter 603 is controlled to count down. Therefore, the read address generation circuit 10
3, the read address is increased to 2, 3, 4, 5, 4, 5 as shown in FIG. 10 (g), and the write range setting signal Hss becomes 4, 5 , 4,
The value is repeated as 5, and thereafter, decreases as 2, 3, 2, 3,.

As a second point, the constant generation circuit 108 configures the read address generation circuit 103 based on the logical sum of the control signal from the read direction control circuit 104 and the write range setting signal Hss from the write range setting circuit 105. Until the address generation counter 603 to start the hold operation (in other words, the write range setting signal Hss).
During the hold state, a constant k = 0 is output.

The other operations are the same as those in the case of FIG. 6 of (A), and a detailed description will be omitted.

Accordingly, the output signal S2 of the interpolation operation circuit 107 is as shown in FIG.

Then, the color difference signal S2 is extracted in four-pixel units by a color difference signal extraction pulse as shown in FIG.

Therefore, when the output chrominance signal S2 obtained by the interpolation operation circuit 107 is compared with the luminance signal S4 after the mirror processing, the result is as shown in FIG.

That is, the luminance signal S4 is, as in the prior art,
An output that has undergone mirror processing is obtained as shown in FIG. In contrast, the color difference signal S2, FIG. (E), (f), the at the left side than the folded position P _C, the color difference signals Cr0 and Cb0 to correspond to the position of the luminance signal Y0, luminance Signal Y4
Color difference signals Cr4 corresponding to the position of the and Cb4 are extracted respectively and the color difference signals Cr8 and Cb8 corresponding to the positions of the luminance signal Y8, also in the right side of the turn-back position P _B,
In order to maintain the 4: 1: 1 sampling frequency ratio between the luminance signal and the chrominance signal, the chrominance signals (3Cr8 + Cr4) / 4 and (3Cb8 + Cb4) / 4 correspond to the position of the luminance signal Y7. The color difference signal (3Cr4 +
(Cr0) / 4 and (3Cb4 + Cb0) / 4 are extracted.

[0096] Therefore, for the color difference signal S2, when the center of the turn-back position P _C, although not completely symmetrical as luminance signals S4, the return position P
_In the immediate vicinity of _C (here, Cr corresponding to the luminance signal Y8)
8 and Cb8), signals having substantially the same color difference components are arranged at positions separated by substantially the same number of pixels on the left and right.

Further, since the color difference signal S2 outputs all the signals of Cr at the position of the Cr pixel in the right half of the mirror image, and outputs all the signals of Cb at the position of the Cb pixel, the color difference signal S2 has the right half. A normal mirror image with no color inversion and no color shift with respect to the output luminance signal is output.

(D) The turning position of the mirror image is P _D ,
That is, the number of pixels of the luminance signal in the left half of the mirror image is 4n.
+3 (n = 0, 1, 2, 3,...) In this case, in order to facilitate understanding, in order to facilitate understanding, n = 2, that is, the pixel of the luminance signal in the left half of the mirror image The number is 11 (= 4 × 2
+3) The operation will be described assuming a pixel.

FIG. 12 is a timing chart for explaining the operation of each circuit when performing the mirror processing.

The operation of FIG. 12 differs from that of FIG.
The constant generation circuit 108 counts down the address generation counter 603 constituting the read address generation circuit 103 based on the logical sum of the control signal from the read direction control circuit 104 and the write range setting signal Hss from the write range setting circuit 105. Until the operation is started (in other words, the period during which the write range setting signal Hss is at the high level), the constant k = 0 is output, and after the countdown is started, the constant k = 3/4 is output.

The other operations are the same as those in the case of FIG. 6 of (A), and a detailed description thereof will be omitted.

Therefore, the output signal S2 of the interpolation operation circuit 107 is as shown in FIG.

Then, the color difference signal S2 is extracted by a color difference signal extraction pulse as shown in FIG. 7 (m) in units of four pixels in a subsequent processing circuit (not shown).

Therefore, when the output chrominance signal S2 obtained by the interpolation operation circuit 107 is compared with the luminance signal S4 after the mirror processing, the result is as shown in FIG.

That is, the luminance signal S4 is, as in the prior art,
An output that has undergone mirror processing is obtained as shown in FIG. In contrast, the color difference signal S2, FIG. (E), (f), the at the left side than the folded position P _D, the color difference signals Cr0 and Cb0 to correspond to the position of the luminance signal Y0, luminance Signal Y4
Color difference signals Cr4 corresponding to the position of the and Cb4 are extracted respectively and the color difference signals Cr8 and Cb8 corresponding to the positions of the luminance signal Y8, also in the right side of the turn-back position P _D,
In order to maintain a 4: 1: 1 sampling frequency ratio between the luminance signal and the chrominance signal, the chrominance signals (Cr12 + 3Cr8) / 4 and (Cb12 + Cb8) / 4 correspond to the position of the luminance signal Y9.
Corresponds to the position of the luminance signal Y5 and the color difference signal (Cr8 +
3Cr4) / 4 and (Cb8 + 3Cb4) / 4 are extracted.

Therefore, the color difference signal S2 is not completely symmetrical with respect to the folded position P _D as in the luminance signal S4, but has substantially the same color difference components at positions separated by substantially the same number of pixels on the left and right, as with the luminance signal S4. Will be arranged.

Further, since the color difference signal S2 outputs all the Cr signals at the position of the Cr pixel in the right half of the mirror image and outputs all the Cb signals at the position of the Cb pixel, the color difference signal S2 A normal mirror image without color inversion and without color shift with respect to the output luminance signal S2 is output.

As can be seen from the above description of each of the operations (A) to (D), the number of pixels of the luminance signal in the left half of the mirror image is (A) to (D).
In any case of (D), in other words, even when the folding start position is set arbitrarily, a normal mirror image can be obtained for the color difference signal. Further, the storage capacity of the line memory required for performing the mirror processing is half that of the conventional image processing apparatus that performs the mirror processing.

The interpolation operation circuit 107 of this embodiment
Are the two multipliers 702a and 702a as shown in FIG.
14B, six bit shifters 1401a to 1401f and two adders 1402a, 1 are used instead of the multipliers 702a, 702b as shown in FIG.
402b and two selectors 1403a, 1403b
And a selector 14 according to a control signal from the constant generation circuit 108 in accordance with each of the above cases (A) to (D).
It is also possible to configure so as to switch the outputs 03a and 1403b.

In the configuration shown in FIG. 14, since it is not necessary to perform digital multiplication, the circuit scale can be reduced.

The linear interpolation method is used as the interpolation calculation method performed by the interpolation calculation circuit 107 shown in FIG.
The present invention is not limited to this. For example, a cubic convolution interpolation method may be used.

[0112]

According to the image processing apparatus of the present invention, read control for reading out a color difference signal constituting a 4: 1: 1 signal in accordance with the turn-back position of mirror processing, and interpolation calculation for the read data are performed. Therefore, the turning position can be set arbitrarily, and a normal mirror image in which the left and right colors around the turning position are not inverted can be output. Further, the storage capacity of the line memory required for performing the mirror processing is half that of the conventional image processing apparatus.

[Brief description of the drawings]

FIG. 1 is a block diagram of an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram of a write address generation circuit in the image processing apparatus of FIG. 1;

FIG. 3 is a block diagram of a read address generation circuit in the image processing apparatus of FIG. 1;

FIG. 4 is a block diagram of an interpolation operation circuit in the image processing apparatus of FIG. 1;

FIG. 5 is a timing chart for explaining operation timing of the write address generation circuit of FIG. 2;

The image processing apparatus 6 1, a timing chart for the folded position to the description of the mirroring operation when set to P _A

FIG. 7 is a schematic diagram showing a mirror processing result based on the timing chart of FIG. 6;

The image processing apparatus 8 Figure 1, a timing chart for the folded position to the description of the mirroring operation when set to P _B

FIG. 9 is a schematic diagram showing a mirror processing result based on the timing chart of FIG. 8;

The image processing apparatus 10 is a diagram 1, a timing chart for the folded position to the description of the mirroring operation when set to P _C

FIG. 11 is a schematic diagram showing a mirror processing result based on the timing chart of FIG. 10;

[12] The image processing apparatus of FIG. 1, a timing chart for the folded position to the description of the mirroring operation when set to P _D

FIG. 13 is a schematic diagram showing a mirror processing result based on the timing chart of FIG.

FIG. 14 is a block diagram illustrating another configuration example of the interpolation operation circuit.

FIG. 15 is an explanatory diagram showing images before and after a mirror process.

And FIG. 16 is a block diagram showing a main configuration of a conventional image processing apparatus.

FIG. 17 is a schematic diagram illustrating a 4: 1: 1 component signal in a conventional image processing apparatus.

FIG. 18 is an explanatory diagram for explaining a write operation and a read operation for a line memory in a conventional image processing apparatus.

FIG. 19 is a timing chart for explaining an operation of mirror processing in a conventional image processing apparatus.

[Explanation of symbols]

99, 100: mirror processing circuit, 101: line memory, 102: write address generation circuit, 103: read address generation circuit, 104: read direction control circuit, 105: write range setting circuit, 106: read range setting circuit, 107 ... Interpolation calculation circuit, 108: constant generation circuit.

Claims (3)

[Claims] 1. An image processing apparatus for performing a mirror process on an input 4: 1: 1 signal, wherein the mirror process individually performs a mirror process on a luminance signal and a color difference signal constituting the 4: 1: 1 signal. A mirror processing circuit that performs a mirror process on the color difference signal, a storage unit that stores an input color difference signal, a constant generation unit that generates a constant for distributing the color difference signal, Interpolation calculating means for performing an interpolation calculation on the color difference signal according to the constant generated by the constant generating means, write address generating means for generating a write address for the storage means, and reading for generating a read address for the storage means Address generation means, writing range setting means for setting a writing range of a color difference signal to be stored in the storage means, Reading direction control means for controlling an increase or decrease of an address generated by the output address generating means, wherein the constant generating means comprises: a range of an input video signal to be stored in the storage means; and the read address of the read direction control circuit. An image processing apparatus for generating a constant in accordance with an address increase / decrease control for a generation unit. 2. An image processing apparatus according to claim 1, wherein the addresses generated by said write address generation means and read address generation means repeat increasing and decreasing at a constant cycle. 3. A constant generated by the constant generating means,
3. The image processing apparatus according to claim 2, wherein the image processing is 0, 1/4, 3/4.