JPS631589B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display data generation device, and more particularly, to a display data generation device for converting serial display data for a display device that does not perform interlace scanning into a serial display data signal for a display device that performs interlace scanning. The present invention relates to a display data creation device that performs control.

Control methods for CRT display devices include methods that perform interlacing and methods that do not perform interlacing. Therefore, the display data creation device A for an interlaced display device and the display data creation device B for a non-interlaced display device differ in the timing of data transfer to the display device. Specifically, for a display device with 525 scanning lines, the synchronization signal in the even field or odd field of the serial display data output from the display data creation device A is 1/1/1 in time from that of the display data creation device B. It is off by 2H. Therefore, conventionally, display data created by display data creation device B could not be displayed on an interlaced display device. For this reason, it has not been possible to perform multiple display in which data created by display data creation devices A and B are overlapped and displayed on one display device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display data creation device that controls the timing of display data created for a non-interlaced display device and converts it into display data for an interlaced display device.

The present invention has a storage means for temporarily storing field data that is not synchronized with interlaced display data among display data that is not for interlaced display, and a storage means for temporarily storing field data that is not synchronized with interlaced display data. It has means for correcting the data so as to be synchronized and reading it out from the storage means, and output means for outputting the resulting synchronized data to a display device.

An embodiment of the present invention will be described in detail below based on the drawings.

A serial display data signal 8 created for a display device that does not use an interlace method is an input terminal.
IN, the signals are controlled to be sequentially input to shift register 1. A dot clock 9 from a non-interlaced display device is input from a terminal CLOCK to a timing generation circuit 6, which outputs a shift in clock for reading a serial display data signal 8 to a shift register 1. shift register 1
The serial display data signal 8 read (shifted in) becomes the parallel display data signal 10 and is output to the data input terminal of the storage element 2. On the other hand, the timing generation circuit 6 provides a control signal to the write control circuit (line controller) 4 and outputs a write control signal 13 to the storage element 2 every time the serial display data signal is converted to parallel display data.
As a result, the display data stored in the shift register 1 is sequentially stored in the storage element 2 as parallel display data. On the other hand, the synchronization signal generation circuit 15 receives a dot clock 9 and a horizontal synchronization signal (HSYNC1) 17 from a non-interlaced display device, and a horizontal synchronization signal (HSYNC2) 18 from an interlaced display device. Among the even or odd fields of the input serial display data signal 8, the field is detected and synchronized with the even or odd fields of the interlaced display device. not, i.e. 1/2
A multiplex signal 16 is output indicating the field which is shifted by H. When this multiplex signal 16 is output, the timing generation circuit 6 outputs 1/
Count the clocks for a period corresponding to 2H, and calculate 1/2H.
After the elapse of time, a control signal is output to the read control circuit 5 to output the read control signal 14. As a result, the parallel display data stored in the storage element 2 is read out with a timing shift of 1/2H and set in the shift register 3. Timing generation circuit 6 outputs a shift out clock to shift register 3, causing shift register 3 to perform a shift operation. As a result, the serial display data signal 12 of the unsynchronized field is outputted from the shift register 3 in synchronization with the corresponding field of the interlace display data. In this way, the display data of fields that are synchronized with the field of display data created for interlacing is passed through the serial display data signal line 8, and the display data of fields that are not synchronized is serially displayed data under timing control. are input to the multiplexer 7 through the signal line 12, and each selected output 19 corresponds to the field synchronization of the display data for interlacing.
is taken out from the output terminal (OUT).

In other words, by using this device, it is possible to convert a serial display data signal that is not created for interlaced use into a serial display data signal that can be applied to an interlaced display device, so the display function is greatly improved compared to the conventional one. can do. Furthermore, since the timing-controlled output 19 is synchronized with the field of interlaced display data, multiple display is possible by adding the two and inputting the result to an interlaced display device. Furthermore, the ability to convert a non-interlaced video signal to an interlaced video signal means that even display data that was not created for interlacing will not flicker on the display screen. This has the effect that it is possible to perform a display without any information.

In FIG. 1, the synchronization signal generation circuit 15 that detects the field to be corrected in timing uses a horizontal synchronization signal 18 used in an interlaced display device and a horizontal synchronization signal 18 used in a non-interlaced display device. Although the signal 17 is compared to detect coincidence or mismatch, it is clear that the vertical synchronization signals may be compared in other ways.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1, 3...Shift register, 2...Storage element,
4...Write control circuit, 5...Read control circuit,
6... Timing generation circuit, 7... Multiplexer, 8, 12, 19... Serial display data signal, 9
...Dot clock, 10, 11...Parallel display data signal, 13...Write control signal, 14...Read control signal, 15...Synchronization signal generation circuit, 16
...Multiplex signal, 17...Horizontal synchronization signal 1, 18...Horizontal synchronization signal 2, 19...Output signal.

Claims (1)

[Claims] 1. A storage means for temporarily storing field data that is not synchronized with display data for interlaced display among display data not for interlaced display to be displayed on a display screen, and a storage means for temporarily storing data of fields that are not synchronized with display data for interlaced display, and for storing the stored data in the interlaced display. means for reading out the display data from the storage means with time correction so as to be synchronized with a corresponding field of the display data for interlaced display, and output means for outputting the display data not for interlaced display that has been synchronized as a result of the synchronization correction to the display device. A display data creation device comprising: