JPS5719840A - Display data generation device - Google Patents

Display data generation device

Info

Publication number
JPS5719840A
JPS5719840A JP9254180A JP9254180A JPS5719840A JP S5719840 A JPS5719840 A JP S5719840A JP 9254180 A JP9254180 A JP 9254180A JP 9254180 A JP9254180 A JP 9254180A JP S5719840 A JPS5719840 A JP S5719840A
Authority
JP
Japan
Prior art keywords
display data
shift register
interlaced scanning
timing
generation device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9254180A
Other languages
Japanese (ja)
Other versions
JPS631589B2 (en
Inventor
Akira Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9254180A priority Critical patent/JPS5719840A/en
Publication of JPS5719840A publication Critical patent/JPS5719840A/en
Publication of JPS631589B2 publication Critical patent/JPS631589B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Television Systems (AREA)
  • Digital Computer Display Output (AREA)

Abstract

PURPOSE: To elevate a display function, by timing-controlling a display data which does not adopt an interlaced scanning system.
CONSTITUTION: A series display data signal 8 which does not adopt an interlaced scanning system is read by a shift register 1, becomes a parallel display data signal 10, and is stored in a memory element 2. This stored data is timing-shifted by 1/2H, and is set to a shift register 3. In the shift register 3, the data is shifted by a shift-out clock from a timing generating circuit 6, and a series display data signal 12 of a field which is not synchronized is synchronized with a field corresponding to a display data for interlaced scanning, and is outputted from the shift register 3. Accordingly, an output 19 which has coincided with synchronization of a field of the display data for interlaced scanning is outputted from a multiplexer 7.
COPYRIGHT: (C)1982,JPO&Japio
JP9254180A 1980-07-07 1980-07-07 Display data generation device Granted JPS5719840A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9254180A JPS5719840A (en) 1980-07-07 1980-07-07 Display data generation device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9254180A JPS5719840A (en) 1980-07-07 1980-07-07 Display data generation device

Publications (2)

Publication Number Publication Date
JPS5719840A true JPS5719840A (en) 1982-02-02
JPS631589B2 JPS631589B2 (en) 1988-01-13

Family

ID=14057233

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9254180A Granted JPS5719840A (en) 1980-07-07 1980-07-07 Display data generation device

Country Status (1)

Country Link
JP (1) JPS5719840A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6045341A (en) * 1983-08-22 1985-03-11 株式会社島津製作所 Ultrasonic diagnostic apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6045341A (en) * 1983-08-22 1985-03-11 株式会社島津製作所 Ultrasonic diagnostic apparatus

Also Published As

Publication number Publication date
JPS631589B2 (en) 1988-01-13

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