JPS6045341A - Ultrasonic diagnostic apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Industrial Application Field The present invention relates to an ultrasonic diagnostic apparatus, and in particular to a digital scan converter (hereinafter referred to as DSC) used to display an image of an echo signal obtained from a transducer. Regarding.

(B) Prior art In general, the display method for diagnostic images in ultrasound diagnostic equipment is to input ultrasound echoes obtained by a transducer directly into an X-Y monitor of a CRT in the form of an analog signal, and synchronize each scan. The analog scan converter (hereinafter referred to as ASC) method is used to capture and display ultrasonic echoes, and the ultrasonic echoes are converted into, for example, 4-bit digital data through an A/D converter, and this digital data is converted into image data before being output to a CRT. There is a DSC method that searches the memory of memory elements such as G-C. The former has a simpler control system than the latter, but is inferior in terms of attached functions such as a caliper display function, a character display function, and a rare image processing function. In addition, the X-Y monitor tube requires periodic adjustment, has a short lifespan, and is expensive, making it difficult to maintain.

Since it is inferior in terms of reliability and economy, the latter type, ie, the SC type, has been widely adopted in recent years, except for special purposes.

By the way, there is one shown in FIG. 1 as a conventional DSC type ultrasonic diagnostic apparatus. The DSCl of this ultrasound diagnostic device is
Image memory 2, A/
D converter 4 and image memory 2 and A/D converter 4
It is mainly composed of two buffer memories 6.8 provided between. Now, when an ultrasonic echo is received by the transducer, this ultrasonic echo is converted into an analog echo signal by the preprocessing circuit, and is sequentially input to the A/D converter 4 from the input terminal 10. The echo signal input to the A/D converter 4 is converted into 4-bit digital data as shown in FIG. The converted digital data is sequentially written into one buffer memory 6 according to timing signals from the write address counter 18 and the control circuit 12. In parallel with this write cycle, the contents already stored in the other buffer memory 8 are sequentially read out and transferred to the image memory 2 by timing signals from the read address counter 20 and the control circuit 12. Then, the image memory 2 performs a data write cycle, that is, the TV
During the retrace period of scanning, the transfer data from the buffer memory 6 is sequentially written into the image memory 2 over the data write cycle period by timing signals from the image memory write address counter 22 and the control circuit 12. Next, if the image memory 2 is in the display period of TV scanning during the data read cycle, the image memory read address color/reference circuit 24 and the control circuit 12 (!:
The 4-bit image data already stored is sequentially output to the parallel-to-serial conversion register 26 by the timing signal. The 4-bit image data inputted in parallel to the parallel-to-serial conversion register 26 is serially converted from the output of the oscillator 28 by a clock pulse of an appropriate frequency, for example, 12.24 MHz, obtained by the counter 30, and is output from the output terminal 32 to the DS.
It is output to the CRT as a C output. Figure 3 shows the conventional DS
This is an example of a display of a CRT scanning screen by Ci, where R,, R3°...R113 indicated by solid lines in the same figure are scanning lines at the array pitch interval of the transducer, and R,... R113 indicated by broken lines in the same figure.
R, . . . R114 is a scanning line obtained by shifting the array pitch of the transducer by half, and
The image is displayed with a total of 114 scanning lines per screen.

At around 7, in the conventional ultrasound diagnostic equipment DSCl,
To transfer image data continuously to Image Memo'J2 2
It is necessary to alternately use the two buffer memories e for writing ax and for continuous writing.

For example, digital data for one scan of an ultrasound echo,
As mentioned above, when data is being written to one buffer memory 6, the stored contents of the other buffer memory 8 are read out, and when only the reading of the buffer memory 8 is completed (d), the contents of the next ultrasound scan are stored in this buffer anomaly 8. data is written, and the previously written data from the other buffer memories 6 is sequentially transferred to the image memory 2. Therefore, for this purpose, address counters 18 and 20 are also used for write addresses and for read addresses. Also, when the image data stored in the image memory 2 is being read out to the CRT (when data is written from the d buffer memory 6 or 8 to the image memory 2), Therefore, writing to the image memory 2 is limited to the horizontal and vertical retrace times of TV scanning and the image idle time.Therefore, data cannot be written to the image memory 2 from the buffer memory 6 or 8 during all of the above time. However, since the transfer time at this time is short, the data must be transferred in small increments. A complicated control is required between the measurement timings.Therefore, a complex and advanced circuit configuration using circuits with high-speed characteristics is required, and the number of parts used increases, making it expensive.Furthermore, regarding the display image, transducers are required. There is a time lag between the scanning line and the TV display image line, or as a result of this lag repeating in a slow cycle, noise is generated or mixed in the preprocessing circuit that converts ultrasound echoes into analog values. , A, C power lines, etc., and ripple noise contained in the stabilized DC power supply, causing problems such as a noticeable phenomenon in which striped patterns appear on the display screen and slowly move.

Furthermore, when providing an enlarged image display function, the conventional device is further provided with an adder (not shown), and the arithmetic average of the output of the A/D converter 4 and the read data of the buffer memory 6 or 8 is calculated using this adder. The calculated and arithmetic averaged data is transferred to the image memory 2, and the transducer scanning image data and the arithmetic averaged image data are alternately output to the CRT for each TVI scan to obtain a smooth enlarged image. .

However, for this purpose, the image memory 2 must always have a storage capacity that is twice the storage capacity normally required for image formation, resulting in a disadvantage that the apparatus becomes more expensive.

(C) Purpose The present invention has been removed in view of the above-mentioned problems,
To increase the degree of parallelism of echo signal data, increase the amount of data transferred per time to an image memory, increase the amount of data written to and read from the image memory per time, and provide a margin for the cycle time of the image memory. By reducing the number of transducer scans required to form a screen and reducing the total number of data written to the image memory, the storage capacity of the image memory can be reduced, and the control circuit can be simplified and slowed down. The purpose is to reduce power consumption and power consumption.

B) Structure In order to achieve such an object, the present invention provides an image memory that stores echo signal data from a transducer as image data, and has a write-only section and a read-only section. The exclusive section and the read-only section are alternately switched at predetermined time intervals, and writing of the echo signal data to the write-only section and reading from the read-only section can be performed in parallel. is provided with a latch circuit that latches unit data of the echo signal data digitized by the A/D converter at regular intervals,
A buffer memory is provided downstream of the image memory to store image data corresponding to the TVI scanning line read from the image memory.

(E) Examples Hereinafter, the present invention will be explained in detail with reference to Examples from FIG. 4 to FIG. 6.

FIG. 4 is a block diagram of the DSC in the ultrasonic diagnostic apparatus of this embodiment. In the figure, 50 is a DS of the ultrasonic diagnostic apparatus, and C152 is an image memory that stores echo signal data as image data. This image memory 5
2 is a write-only section 52a (t or 52b) and a read-only section 5
2b (or 52a) or the like for a predetermined time, in this example, the TVI screen formation time, and write image data to this write-only section 52a (or 52b).
The reading from the read-only section 52b (also 52a) is configured to be operable in parallel. A launch circuit 56 is provided upstream of the image memory 52 for latching unit data of the echo signal data digitized by the Id A/D converter 54 for a fixed period of time. Further, at the subsequent stage of the image memory 52, there is a buffer memory 58 that stores image data corresponding to the TVI scanning line segment read out from the image memory 52, and a buffer memory 58 that stores image data read out from the image memory 52 and corresponding to the image data read out from the image memory 58. an adder 60 that adds and averages image data to obtain scan average image data; and an image memory 5.
A multiplexer 62 is provided for alternately switching and outputting the image data read from 2 and the scanning amount average image data output from the adder 60 for each TVI scanning line.

In addition, 64 is a control circuit that performs timing control of the entire D'sc-50, 66 is an oscillator, 68 is a counter that counts the output pulses of the oscillator 66, and 70 is a signal synchronized with TV scanning after receiving the output of the counter 68. 72 is an image memory write address counter that specifies the write address position for the write-only section 52a (or 52b) of the image memory 52; 74 is an image memory write address counter that specifies the write address position; An image memory read address counter that specifies the read address position for the read-only section 52b (or 52a), and 76 is a parallel-to-serial conversion shifter that converts the image data output in parallel from the multiplexer 62 into a serial data string. It is a register.

Next, the fifth section describes the operation of each part when displaying a diagnostic image on a CRT screen using the DSC5Q having the above configuration.
This will be explained with reference to the time chart shown in the figure. In addition, as an example of transducer specifications and measurement conditions at that time, measurement depth D: 19'7.5InIn + scanning width W-
A case where the number of vibrators is set to 831n1n and the number of vibrators -5'7 will be described below.

The ultrasonic echoes received by the transducer are sequentially converted into analog echo signals (A, N) by a preprocessing circuit (all not shown) and input to the A/D converter 54 from the input terminal 78. Emission of ultrasonic waves is controlled by the control circuit 64, and a drive signal is output from one output terminal 80 to a transducer drive circuit (not shown) to excite the transducer. Further, initialization for starting scanning of the transducer is performed by outputting a transducer initialization signal from another output terminal 82 of the control circuit 64 to a multiplexer (not shown). The echo signal A input to the A/D converter 54 is converted into digital data in units of 4 bits. Average sound velocity in human body C≠1.543mm/μG
, one scan line of the transducer (e.g. LN
) measurement time T is T = end = 2 X l 9 '7
．． 5/1.543 = 256 ps. Now, the conversion cycle time of the A/D converter 54 is set to 0.5.
If it is μs, the number of digitally converted data per measurement time T is 256/0.5:512.

In other words, the echo signal A and N for one scanning line of ultrasonic echoes
is successively converted into 512 pieces of digital data by the A/D converter 54. The bit-by-bit digital data converted by the A/D converter 54 is output to the image memory 52 and the launch circuit 56. The clock pulse input terminal CKK' of the latch circuit 56 (since the clock pulse CL○cK with twice the period of the conversion cycle time of the A/D converter 54 is input from the d control circuit 64,
Digital data is held in the latch circuit 56 every other 4-bit unit, and two unit data, ie 1, 2, 3, are held in the latch circuit 56.
and 4 degrees... 511 and 512, the current write-only section 5 of the image memory 52 is written every 8 bits of data.
2a as image data. At that time, the address specification is the clock pulse CLoc of the control circuit 64.
This is done by an address designation signal from the image memory write address counter 72 synchronized with K. Therefore, one write cycle time to the image memory 52 is 1 μs, and 2
By writing 56 times, 512 pieces of image data are written. In this way, the write-only section 52aK
Image data corresponding to two transducer scanning lines 5' necessary for screen formation are sequentially stored.

In parallel with the above operation, 8-bit image data corresponding to 42 chises is sequentially read out from the current read-only section 52b of the image memory 52 for each readout. Therefore, 512 pieces of data are read 256 times. Note that the address specification of the read-only section 52b is performed by the controller 6.
This is performed by an address designation signal output from the image memory read address counter 74 based on the control signal from the image memory read address counter 74. The image data in 8-bit units read from the image memory 52 is input to the buffer memory input terminal 3 and the adder 6.
0 input terminal D3 and input terminal A of multiplexer 62, respectively. The buffer memory 58 is switched between a write state and a read state for each pTVI scanning line by a control signal from a control circuit 64. At the same time, the multiplexer 62 also controls the TVI by the control circuit 640 control signal.
Connections between input terminals A and B and output terminal S are switched for each scanning line. Therefore, when the buffer memory 58 is currently in the writing state, the multiplexer 62
An input terminal A directly connected to the output terminal S is connected to the output terminal S thereof. Therefore, the image data for 512 TVI scanning lines read out from the image memory 52 is written to the buffer memory 58 and output to the parallel-to-serial conversion shift register via the multiplexer 62, where it is connected to the control circuit 64. The data is sequentially converted into a serial data string according to the timing of the counter 68, and is output from the output terminal 84 to the CRT as the output of the DSC 7. On the other hand, when the buffer memory 5B is in the read state, the multiplexer 62 is connected to the adder 6.
．． The input terminal B is directly connected to the output terminal Z of 0, or the output terminal S thereof. In this state, the image data for T1 scanning lines sequentially read out from the output terminal portion of the buffer memory 58 is inputted to one input terminal D2 of the adder 60.

At that time, at the same time, the image memory 52 is read out from the image memory 52 to the next display designated by the image memory read address counter 74.
Image data for Tv1 scanning line is output.

This image data is input to the other input terminal D3 of the adder 60. Then, the adder adds the image data from the buffer memory 5B and the image data from the image memory 52, calculates the arithmetic average of the two, uses the average value as scan amount average image data, and sends it to the parallel-to-serial conversion register via the multiplexer 62. 76. The parallel-to-serial conversion/ft register 76 similarly converts the input scan amount average image data into a serial data string and outputs it to the CRT. In this way, the image data read out from the image memory 52 as it is and the scan average image data obtained by the adder 60 are alternately stored on the CRT.
are output to form a single TV picture. FIG. 6 shows an example of a CR4 scanning screen displayed in this manner, and R1, R2, and R57 indicated by solid lines in the figure are TVI scanning lines when image data read from the image memory 52 is displayed. M, Mi2.・・・
Block A is a TVI scanning line when the scanning amount average image data output from the adder 60 is displayed. Therefore, in effect, the 5'7 scanning lines of the transducer require 114
The data for the TV scan line of the book will be obtained.

In this case, the measurement time for the image data required to form the TVI screen is 256 x 114 = 29184 μs, but the time required to form the TVI screen is about 33333.3 μs, so writing to the image memory 52 is shorter than reading it. It's time.

After displaying the scanned image of the TVI screen as described above, the image memory 52 changes from the write-only section 52a to the read-only section under control and signals from the control circuit 64.
2a, the read-only T4B5211) is switched to the write-only section 52b, and this switched read-only section 5
The image data stored in 2a is sequentially read out. In parallel with this, echo signal data is successively written into the write-only section 521). In this way, the read-only section and the write-only section are alternately switched each time one TV screen is formed.

(f) Effects As described above, according to the present invention, the image memory has a write-only section and a read-only section that are switched alternately, and is provided so that writing and reading of both sections can be performed in parallel. , it is no longer necessary to transfer the echo signal data digitally processed by an A/D converter to the image memory via a buffer memory at high speed as in the past, and therefore complex timing control using high-speed processing is no longer necessary. No circuit is required. Moreover,
Since the launch circuit is provided before the image memory, the amount of data written to and read from the image memory per unit of time is increased, and the cycle time of the image memory is increased.

In addition, a buffer memory is provided after the image memory so that writing and reading can be performed alternately.
Where 2V2O4 is required, only half the storage capacity is required. Therefore, the storage capacity of the entire DSC is smaller than that of the conventional one. Therefore, the number of parts of the device is reduced, and power consumption is also reduced, resulting in substantial cost reductions. Furthermore, even in the case of displaying an enlarged image, there is no need to particularly increase the storage capacity of the image memory, and in this respect as well, an excellent practical effect can be obtained in that it is advantageous in reducing costs.

[Brief explanation of drawings]

1 to 3 show a conventional example, and FIGS. 4 to 6 show an embodiment of the present invention, respectively. The figure is a time chart for explaining the operation of the device in Figure 1, and Figure 3 is an explanatory diagram showing a display example of a TV scanning screen.
Figure 4 shows the digital scan controller (-
Figure 5 is an explanatory diagram showing an example of the display of the lock system shown in Figure 5. It is. 50...Digital scan converter of ultrasonic diagnostic equipment, 52...Image memory, 52aI 52b° write and read only section, 54...A/D converter, 56...Launch circuit, 58...Buffer memory. Applicant: Shimadzu Corporation Agent: Kazuhide Okada, Patent Attorney

Claims (1)

[Claims] (1) An image memory that stores echo signal data from a transducer as image data has a write-only section and a read-only section, and the write-only section and read-only section are arranged at predetermined intervals. At the same time, writing of the echo signal data to the write-only section and reading from the read-only section are provided so that the echo signal data can be operated in parallel. Image data corresponding to the TVI scanning line read from the image memory is stored in the rear stage of the image memory, which is provided with a launch circuit that latches unit data of the echo signal data at fixed time intervals. An ultrasonic diagnostic device characterized by being provided with a buffer memory.