JP3036210B2 - Image processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing circuit for displaying image data input from a symbol generator.

[0002]

2. Description of the Related Art As an image processing circuit for processing image data input from a symbol generator and displaying the processed image data on an image display device, a conventional circuit as shown in FIG. The switching of the frame memory and the reading of the display data are started by using the signal as a trigger.

In FIG. 1, reference numeral 1 denotes a timing controller which separates a synchronizing signal from input image data and sends it to a write control circuit 2 to control the operation timing. The write control circuit 2 inputs a memory switching signal to the data selector 3 and the control signal selector 4 based on the timing signal from the timing controller 1 to switch each selector. Further, a write control signal is generated based on the timing signal, and writing is performed in synchronization with the frame frequency of the image data.

[0004] The read control circuit 5 is
A read control signal is output using the frame end signal from the as a trigger. The memory A6 and the memory B7 alternately input image data by switching the data selector 3, and
By switching the control signal selector 4, a write control signal and a read control signal are alternately input, and writing and reading of image data to and from the memory A6 or the memory B7 are alternately performed. The read control signal starts reading of image data by using a frame end signal as a trigger. In this conventional device, the display frequency for displaying an image on the display device 9 is usually 60 Hz, and the frequency (display frame frequency) for reading display data from the memories A6 and B7 is the frame frequency of the received image data. However, the frame frequency of the received image data does not always have an integer ratio relationship with the frame frequency of the image data. On the other hand, in order to display a good image, it is necessary to select a display frame frequency that is optimal for a display device (LCD, PDP, etc.).

[0005]

The conventional apparatus having the above configuration has the following disadvantages. (A) The display data reading frequency (display frame frequency) must be an integral multiple of the frame frequency of the received image data, and the display device (LCD, PDP)
Etc.) may not be able to be set to the optimal frame frequency. (B) Since the display frame frequency follows the fluctuation of the frame frequency of the received data, if the fluctuation is large, the display quality deteriorates.

[0006] The present invention has been made in view of the above points, and an object thereof is to enable display at a display frame frequency independent of a frame frequency of received image data.
Another object of the present invention is to realize an image processing circuit which is not affected by fluctuations in the frame frequency of received data.

[0007]

In order to solve the above-mentioned problems, the present invention provides a first memory (6) and a second memory (7).
An image display circuit comprising a plurality of memories, wherein writing of received image data to the memory and reading of the written image data are performed alternately and displayed, a write control signal based on a frame frequency of the input received image data. When a write control circuit for outputting a data pause signal indicating a data pause period between said received image data frame (11), than the frequency of the data pause signal
A read control circuit (12) that oscillates a signal of a frequency that can be arbitrarily changed to generate a horizontal scanning signal and a read control signal of the frequency, and the data pause of the output of the write control circuit (11) A signal and the horizontal scanning signal output from the readout control circuit (12) are input, and a switching signal generation circuit (1) outputs a memory switching signal.
3) a data selector (3) for switching and inputting image data to the first memory (6) and the second memory (7) according to the memory switching signal; and the write control signal according to the memory switching signal. And a control signal selector (4) for alternately switching and inputting the read control signal to the first memory (6) and the second memory (7).

[0008]

The write control circuit forms and outputs a data pause signal from the data pause period of image data. Further, the read control circuit generates a unique frequency signal and outputs a horizontal scanning signal of the frequency. The switching signal generating circuit generates a memory switching signal based on a horizontal scanning signal during an input data pause period based on the data pause signal, switches between a data selector and a control signal selector, and performs writing and reading of the first memory and the second memory. Let them alternate. The write control signal output from the write control circuit is synchronized with the frame frequency of the input image data, but the read control signal output from the read control circuit controls reading from the memory at a frequency related to the display frame frequency. I do.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention. In the figure, the same parts as those in FIG. 5 are denoted by the same reference numerals. In the figure, reference numeral 11 denotes a write control circuit which receives a part of image data, detects a data pause period and outputs a data pause signal, and outputs a write control signal to the control signal selector 4.

Reference numeral 12 denotes a read control circuit which generates a signal of a unique frequency, outputs a horizontal scan signal of that frequency, and outputs a read control signal of the frequency to the control signal selector 4. Reference numeral 13 denotes a switching signal generation circuit that receives a data pause signal from the writing control circuit 11 and a horizontal scanning signal from the reading control circuit 12 and outputs a memory switching signal to the data selector 3 and the control signal selector 4.

Next, the operation of the apparatus of the embodiment configured as described above will be described with reference to the waveform diagrams of FIGS. 2, 3 and 4. Image data is input to the writing control circuit 11.
FIG. 2 shows the waveform of this image data. In the figure, 21
Is the waveform of the image data, 22 is the data for one frame,
The image data actually used and the data pause period 23 are included in the data for one frame.

The write control circuit 11 generates a write control signal based on the input image data, inputs the write control signal to the control signal selector 4, and inputs a data pause signal indicating a data pause period 23 to the switching signal generation circuit 13. .

The read control circuit 12 independently oscillates at the display frame frequency, and inputs a horizontal scanning signal of the display frame frequency shown in FIG.
In the figure, reference numeral 24 denotes a horizontal scanning signal composed of pulses, and a horizontal scanning period 25 corresponds to a display frame frequency. The horizontal scanning period 25 is the same as the data pause period 23.
Shall be smaller than

The switching signal generating circuit 13 generates a memory switching signal according to the input data pause signal and horizontal scanning signal. FIG. 4 is a time chart showing the relationship between the signals. In the figure, the same reference numerals are given to parts equivalent to those in FIGS. In the figure, reference numeral 26 denotes a switching signal generation circuit 13.
Is a memory switching signal that occurs. Switching signal generation circuit 1
3 inverts the memory switching signal 26 in synchronization with the pulse of the first horizontal scanning signal 24 among the horizontal scanning signals shown in FIG. .

The data selector 3 and the control signal selector 4 are switched by inverting the memory switching signal 26. For example, data is written to the memory A6 and the memory B7
, The data is read from the memory A6, and the data is written to the memory B7.

The output data selector 8 is interlocked with the control signal selector 4, and the data read from the memory B7 is displayed on the display device 9 in the state shown in FIG. When each selector is switched by the memory switching signal, the memory A6
Is displayed on the display device 9.

As described above, according to this embodiment, the writing to the memory is performed at the frame frequency of the input image data, but the switching of the memory and the reading of the data from the memory are performed in the display frame. Image is obtained.

In this embodiment, the oscillation frequency in the read control circuit is equal to the display frame frequency. However, any frequency may be used as long as its ratio to the display frame frequency is an integer. Further, if the oscillation frequency of the read control circuit can be changed, it is possible to respond to a display device having a different display frame frequency.

Further, even if the frame frequency fluctuates in the received data, the display frame frequency is independently and stably generated, so that the display quality can be prevented from deteriorating.

[0020]

As described above in detail, according to the present invention, it is possible to display a received image data at a display frame frequency independent of the frame frequency.
Further, the image quality can be improved irrespective of the fluctuation of the frame frequency of the received image data, and the practical effect is great.

[Brief description of the drawings]

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.

FIG. 2 is a waveform diagram of received image data.

FIG. 3 is a waveform diagram of a horizontal scanning signal generated by a read control circuit.

FIG. 4 is a time chart showing a relationship between a pause period of image data, a horizontal scanning signal, and a memory switching signal.

FIG. 5 is a block diagram of a conventional image processing apparatus.

[Explanation of symbols]

 3 Data selector 4 Control signal selector 6, 7 Memory 11 Write control circuit 12 Read control circuit 13 Switching signal generation circuit

Claims (1)

(57) [Claims] 1. A first memory (6) and a second memory (7).
An image display circuit comprising two memories, wherein writing of received image data to the memory and reading of the written image data are performed alternately and displayed, wherein input received image data is written at a frame frequency. A write control circuit (11) for outputting a control signal and a data pause signal indicating a data pause period between frames of the received image data; and a frequency of the data pause signal.
A read control circuit (12) that oscillates a signal having a frequency that can be arbitrarily changed and generates a horizontal scanning signal and a read control signal at the frequency, and an output of the write control circuit (11). A switching signal generating circuit (13) that receives a data pause signal and the horizontal scanning signal output from the read control circuit (12) and outputs a memory switching signal; A data selector (3) for switching input to the first memory (6) and the second memory (7), and the write control signal and the read control signal by the memory switching signal to the first memory (6). And a control signal selector (4) for alternately switching and inputting the data to the second memory (7).