JPH08286638A - Liquid crystal display device - Google Patents

Abstract

PURPOSE: To provide a liquid crystal display device capable of performing an optimum image display for various computers with simple constitution. CONSTITUTION: A horizontal start signal STH of a high level is outputted to a liquid crystal panel 8 always for six horizontal scanning periods from a horizontal start signal forming circuit 9E in a vertical blanking period. Further, a switch 9j selects a second vertical shift clock signal forming circuit 91 in the vertical blanking period, and a second vertical shift clock VCP of a frequency of 80 times of a horizontal synchronizing signal is outputted to the liquid crystal panel 8 only three times. At this time, for the second period of the second vertical shift clock signal VCP, a vertical start signal SHV from a vertical start signal forming circuit 9F is a high level always, and further, an upper/lower shift control signal VMC from an upper/lower shift control signal forming circuit 9G inverts from the high level to a low level. Thus, the image data of a sufficient black level are displayed on 80 lines of the lower side of the liquid crystal panel 8, and the optimum image is displayed answering to various computers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device for displaying an image, and more particularly to a liquid crystal display device for appropriately displaying an image regardless of the number of line data of input image signals.

[0002]

2. Description of the Related Art In a liquid crystal display device, an image is displayed by synchronizing one dot of dot data included in an image signal with one pixel of a liquid crystal panel in one horizontal period.
In addition, line data of one line (one scanning line) in an arbitrary number of line data (scanning line data) that the image signal has within one horizontal period is displayed in correspondence with one line in the vertical direction on the display panel. To be done. This line data is a set of dot data.

In such a liquid crystal display device, an image is displayed according to an image signal output from a computer.

In recent years, computers having various specifications have been manufactured. These computers often have different characteristics of image signals when they are of different types. Therefore, a liquid crystal display device that is connected to a computer and displays an image is required to have versatility that is compatible with many types of computers.

Now, for example, when an image signal from a computer having a total number of lines of 440 (of which 400 is an effective image data period) is displayed on a liquid crystal panel having 480 display lines, the liquid crystal panel is displayed. Since the number of display lines (480) is larger than the total number of image signal lines (440), the image of 1 to 40 lines of the image signal of the next field is also applied to the lower 40 lines of the liquid crystal panel. It will be displayed.

Therefore, the applicant of the present application has proposed Japanese Patent Application No. 6-163828 as a technique for solving this problem.

This technique, as shown in FIG.
L circuit 1, second PLL circuit 2, microcomputer (hereinafter abbreviated as microcomputer) 3, A / D conversion circuit 4, memory 5, D / A conversion circuit 6, signal processing circuit 7, liquid crystal panel 8, and signal It is composed of a generating circuit 9.

Then, the line data of the image signal PS is written in the memory 5 in response to the write clock signal WC from the first PLL circuit 1 and the read clock signal RC from the second PLL circuit 2 is written. In response, data is read from memory 5.

If the number of lines of data written or written in one vertical period is smaller than the number of pixels of the liquid crystal panel 8 in the vertical direction, dummy data is read out based on the read reset signal RR.

Therefore, even if the number of line data in one vertical period is smaller than the number of pixels in the vertical direction of the liquid crystal panel 8, the number of line data for displaying an optimum image can be secured.

[0011]

However, in the above-mentioned conventional technique, the A / D conversion circuit 4, the memory 5, and the D / A conversion circuit 6 are separately required, which complicates the circuit configuration and increases the cost. It was.

The present invention has been made in view of the above-mentioned drawbacks, and an object thereof is to obtain a liquid crystal display device capable of optimally displaying an image on various computers with a simple structure. .

[0013]

According to the present invention, a liquid crystal display means for inputting an image signal to display an image, a microcomputer for outputting a discrimination signal according to a connected computer, and a discrimination from the microcomputer. PLL means for inputting a signal and a horizontal synchronizing signal and creating a sampling clock signal and a comparison target signal having the same period as the horizontal synchronizing signal;
Horizontal start signal creating means for creating a horizontal start signal for starting the horizontal scanning of the liquid crystal display means based on the sampling clock signal and the comparison target signal from the LL means and the discrimination signal from the microcomputer. A horizontal shift clock signal generating means for generating a horizontal shift clock signal corresponding to the horizontal pixels of the liquid crystal display means, and a vertical start signal for starting the vertical scanning of the liquid crystal display means. A vertical start signal creating means for creating a vertical shift clock signal for creating a vertical shift clock signal corresponding to a vertical pixel of the liquid crystal display means, and controlling vertical scanning of the liquid crystal display means. Timing pulse generation having vertical shift control signal generating means for generating vertical shift control signal A liquid crystal display device, characterized in that it consists of a stage.

[0014]

In FIG. 3, during the period from T1 to T2, A40
The image data of 1 (black level) is written in the 401 line of the liquid crystal panel 8.

During the period from T2 to T3, the image data of A402 (black level) is sequentially written from the 402th line to the 480th line of the liquid crystal panel 8 in the writing time of 1/80 of the normal time.

In the period of T3 to T4, the image data of A402 written in the liquid crystal panel 8 in the previous period of T2 to T3 is held as it is.

During the period from T4 to T5, the image data of A404 (black level) is sequentially written from the 480th line to the 401th line of the liquid crystal panel in a writing time of 1/80 of the normal time.

During the period from T5 to T6, the image data (black level) of A405 is 4 to 401 lines of the liquid crystal panel 8.
It is always written in 80 lines for 1 fH period.

During the period of T6 to T7, the image data of A406 (black level) is sequentially written from the 401st line to the 480th line of the liquid crystal panel in the writing time of 1/80 of the normal time.

In the period of T7 to T8, the image data of A406 written in the liquid crystal panel 8 in the previous period of T6 to T7 is held as it is.

In this way, the writing operation for one screen is completed, and the liquid crystal panel 8 having 480 lines has one
The input effective image information is displayed on lines 400 to 400, and black is displayed on lines 401 to 480.

Then, when the vertical start signal STV changes from low level to high level, scanning of the next field is started.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the liquid crystal display device of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a liquid crystal display device according to the present invention. In FIG. 1, the liquid crystal display device outputs a sampling clock signal SC synchronized with a horizontal synchronizing signal HSS from a PLL circuit 1 and a PLL circuit 1. A timing pulse generation circuit 9 that receives the sampling clock signal SC, the comparison target signal FH, and the vertical synchronization signal VSS and outputs various control signals, and a data signal of the computer according to the type of the connected computer (not shown) PLL
The microcomputer 3 for outputting to the circuit 1, the polarity inversion circuit 10 for inverting the image signal PS from the computer by the polarity control signal VT from the timing pulse circuit 9, and the polarity inversion image signal PSS in which the polarity is inverted at a constant period are displayed. It is composed of a liquid crystal panel 8.

The timing pulse generating circuit 9 is
The comparison target signal FH from the L circuit 1 and the vertical synchronization signal V
A line counter 9A that receives SS, a data comparison circuit 9B that receives the count value LV by the line counter 9A, and the second data signal D2 from the microcomputer 3;
A polarity control signal creation circuit 9C that receives the comparison target signal FH from the PLL circuit 1, a horizontal shift clock signal creation circuit 9D that receives the sampling clock signal SC from the PLL circuit 1, and a sampling clock from the PLL circuit 1. The horizontal start signal generation circuit 9E, which receives the signal SC and the comparison target signal FH and the first comparison signal DET1 from the data comparison circuit 9B, and the comparison target signal FH from the PLL circuit 1 and the first comparison signal from the data comparison circuit 9B. 2 Vertical start signal generation circuit 9 which receives the comparison signal DET2
F and the third comparison signal DET3 from the data comparison circuit 9B
Up and down shift control signal generating circuit 9G which receives
A sampling clock signal SC from the L circuit 1 and a first vertical shift clock generation circuit 9H to which the comparison target signal FH is input, a sampling clock signal SC from the PLL circuit 1, a third data signal D3 from the microcomputer 3, and data. A second vertical shift clock generation circuit 9I which receives the fourth comparison signal DET4 from the comparison signal 9B, and a first vertical shift clock signal and a second vertical shift clock signal generation from the first vertical shift clock signal generation circuit 9H. The switch 9J selectively switches the second vertical shift clock signal from the circuit 9I and the fourth comparison signal DET4 from the data comparison circuit 9B.

The liquid crystal panel 8 is, as shown in FIG.
Horizontal start signal S from the timing pulse generation circuit 9
The TH and the horizontal sampling clock signal HCP are input, and the horizontal driver 8A composed of 640 shift registers, the vertical start signal STV from the timing pulse generation circuit 9, and the vertical sampling clock signal V
CP, and vertical shift control signal VMC are input, and a vertical driver 8B composed of a shift register, a plurality of liquid crystal cells 8C, a plurality of control transistors connected to the liquid crystal cells 8C, and an output from the horizontal driver 8A. It is composed of a plurality of switching transistors 8D which control the supply of the polarity inversion image signal PSS to the liquid crystal cell 8C based on the above.

Further, the PLL circuit 1 has a frequency dividing circuit (not shown), and the first data signal D from the microcomputer 3 is supplied.
The frequency division ratio of the frequency dividing circuit is changed by 1 to change the frequency of the sampling clock signal SC according to the type of computer.

In the PLL circuit 1, since the horizontal synchronizing signal HSS is input as the phase synchronizing reference signal, the dot data of the sampling clock signal SC and the image signal PS is generated by the first data signal D1 from the microcomputer 3. It is set to a value that synchronizes in a one-to-one correspondence.

Next, the operation of the liquid crystal display device of the present invention will be described.

The polarity of the input image signal PS is inverted line by line by the polarity reversing circuit 10 based on the polarity control signal VT from the polarity control signal creating circuit 9C, and the polarity is reversed in this polarity reversing image. The signal PSS is input to the liquid crystal panel 8.

In addition to the image signal PSS, the liquid crystal panel 8 has a horizontal shift clock HCP and a horizontal start signal ST.
H, vertical start signal STV, vertical shift clock VC
P and the vertical shift control signal VMC are also input,
An image is displayed according to these signals.

Here, the horizontal start signal STH is a signal that has the same period as the horizontal synchronization signal HSS and a phase different from that of the horizontal synchronization signal HSS supplied from the computer. The phase, pulse width, level, etc. are adjusted and output to the liquid crystal panel 8.

The horizontal shift clock signal HCP is
This signal is for sequentially selecting pixels on the same line from left to right, and is supplied to the horizontal driver 8A.

As a result, in the liquid crystal panel 8, the horizontal scanning on the screen is started by the horizontal start signal STH, and thereafter, the pixels on the same line are sequentially selected from the left to the right by the horizontal shift clock HCP, and one line of the line is selected. The image signal is written in each liquid crystal cell 8C.

On the other hand, the vertical start signal STV is based on the vertical synchronizing signal VSS supplied from the computer,
It is a signal that has the same period as the vertical synchronization signal VSS and may have a different phase, and is output after the phase, pulse width, level, etc. have been adjusted by the vertical start signal generation circuit 9F.

The vertical shift clock signal VCP is
This is a signal for sequentially selecting lines on the liquid crystal panel from top to bottom (or from bottom to top), and the vertical driver 8B
Is supplied to.

As a result, the liquid crystal panel 8 starts scanning in the vertical direction on the screen by the vertical start signal STV, and thereafter the lines of the liquid crystal panel 8 are moved from top to bottom (or from bottom to top) by the vertical shift clock signal VCP. ) Sequentially selecting and writing the image signal of one field into the liquid crystal cell 8C.

The vertical shift control signal VMC is a signal for controlling the vertical scanning direction of the liquid crystal panel 8. When the vertical shift control signal VMC is high, scanning is performed from top to bottom, and when it is low, scanning is performed from bottom to top. .

Hereinafter, assuming that the number of pixels in the horizontal direction is 640,
A case of using a liquid crystal panel having 480 vertical pixels will be described with reference to FIG.

The specifications of the input image signal from the computer are as follows: horizontal frequency fH, vertical frequency fV, 1
It is assumed that the total number of pixels in the horizontal scanning period is Tdot (800 pixels), the total number of lines in the vertical scanning period (TL) is 440 lines, and the number of effective image lines in the vertical scanning period (DL) is 400 lines.

In FIG. 3, A1, A2, ..., A4
Reference numerals 40 respectively indicate lines corresponding to the line data of the image signal PS, A1 to A400 are effective image lines, and A401 to A440 are vertical blanking periods (fixed to the pedestal level). .

During the period from A1 to A400, the vertical shift control signal is set to a high level signal to move the vertical scanning direction from top to bottom, the information of A1 is displayed on the first line of the liquid crystal panel 8, and A2 is displayed. Information is displayed on the second line of the liquid crystal panel 8 and the vertical scanning direction of the liquid crystal panel 8 is shifted from the top to the bottom (from d1 to d400 in FIG. 2) by 1: 1 for proper display. There is.

That is, the vertical scanning is started by the vertical start signal STV given before the supply of A1 and thereafter, f
It is shifted by the first vertical shift clock signal VCP from the first vertical shift clock signal generation circuit 9H of H period and scans the first line of the liquid crystal panel 8 when A1 data is input (control transistor G (1,1 in FIG. ) ~ G
(1,640) is made conductive. ), The second line of the liquid crystal panel 8 is scanned when A2 data is input, and the third line of the liquid crystal panel 8 is scanned when A3 data is input.
The liquid crystal panel 8 is sequentially scanned up to 400 lines in a cycle.

Here, the line counter 9A is a circuit that counts the number of input comparison target signals FH (the same frequency signal as the horizontal synchronization signal HSS) using the vertical synchronization signal VSS as a reset signal. A value corresponding to the line number of the image signal PS input at an arbitrary time is output as counter data LV and supplied to the data comparison circuit 9B.

Then, in the data comparison circuit 9B, the second data signal D2 supplied from the microcomputer 3 is compared with the counter data LV, and the high / low first comparison signals DET1 to DET4 according to the match / mismatch. The comparison signal DET4 is output.

For example, in the period of A1 to A400, the fourth comparison signal DET4 outputs a high level, and the switch 9J which is switched by this selects the first vertical shift clock generating circuit 9H, and the vertical shift clock is generated. It operates so as to be supplied to the liquid crystal panel 8 as the signal VCP.

Next, in the vertical blanking period (= 40H) of A401 to A440, the number of lines of the remaining liquid crystal panel 8 is 80 in comparison with 40H of the vertical blanking period in the scanning method similar to the above-mentioned effective image period. Since the book is larger, the effective image data of the next field is supplied before the bottom 480th line of the liquid crystal panel 8 is scanned.
The information for the first 40 lines of the effective image data of the next field is also displayed on the lower 40 lines of the liquid crystal panel 8.

Therefore, in the technique of the present invention, the following driving method is used for the purpose of writing black on the lower 80 lines of the liquid crystal panel 8 in a short time.

In this embodiment, the horizontal start signal ST
H is a signal which is always high level during the period A401 to A406 (period T1 to T7), and the vertical start signal STV.
Is a signal which is always at a high level during the period A404 to A405 (period T4 to T6), and the vertical shift clock signal V
CP is A402 period (T2-T3 period) and A404
Period (T4 to T5 period) and A406 period (T6 to
During the period T7, the clock signal of 80 fH and the vertical shift control signal VMC are set in the periods A404 to A405 (T4 to T6).
During the period), a low level signal is output.

The vertical shift clock signal is created as follows.

In FIG. 1, the vertical shift clock signal V
CP is the first vertical shift clock signal from the first vertical shift clock signal generation circuit 9H (same frequency as fH)
And the second vertical shift clock signal (frequency of 80 fH) from the second vertical shift clock signal generation circuit 9I are selectively switched by the switch 9J.

Second vertical shift clock signal generation circuit 9I
Then, the sampling clock signal S from the PLL circuit 1
A second vertical shift clock signal is generated by C, the fourth comparison signal from the data comparison circuit 9B, and the third data signal from the microcomputer 3. This second vertical shift clock signal has a period of 1/2 fH from A402. Occurs only 3 times.

In this embodiment, the generation timing of the second vertical shift clock signal is A402 and the number of times of generation is 3
However, the number of times is not limited to this as long as it is within the vertical blanking period.

Next, in the switch 9J, A1 to A401
Up to the first vertical shift clock signal generation circuit 9
The first vertical shift clock signal from H is selected, and the second vertical shift clock signal is selected in other periods.

As a result, from the switch 9J, V of FIG.
The signal indicated by CP is output and supplied to the liquid crystal panel 8.

In FIG. 3, during the period T1 to T2, only the horizontal start signal STH is constantly changed to the high level, so that the image data of A401 (black level) is written in the 401 line of the liquid crystal panel 8.

During the period from T2 to T3, the vertical shift clock signal VCP becomes a high-speed clock signal of 80 fH. Therefore, 401 to 480 lines of the liquid crystal panel 8 are scanned during this period, and the writing time is 1 / 8
Although 0, the image data of A402 (black level) is sequentially written from the 402th line to the 480th line of the liquid crystal panel 8.

Since the 79th signal of the vertical shift clock signal scans 480 lines of the liquid crystal panel 8,
The 0th signal is ignored.

Since the vertical shift clock signal is not supplied in the period of T3 to T4, the image data of A402 written in the liquid crystal panel 8 in the previous period of T2 to T3 is held as it is.

During the period from T4 to T5, the horizontal start signal STH and the vertical start signal SHV are always at the high level, and the vertical shift control signal VMC changes to the low level. Therefore, during this period, the liquid crystal panel 8
Scan 480 to 401 lines from bottom to top,
The image data of A404 (black level) is 401 from the 480 lines of the liquid crystal panel in the writing time of 1/80 of the normal time.
The lines are sequentially written.

In the period from T5 to T6, the horizontal start signal STH and the vertical start signal SHV are always at the high level, and the vertical shift control signal VMC is held at the low level, but the vertical shift clock signal VCP.
Is not supplied to the liquid crystal panel 8. Therefore, during this period, lines 401 to 480 of the liquid crystal panel 8 are always in the selected state, and the image data of A405 (black level)
Is 1f from 401 line to 480 line of liquid crystal panel 8
Since it is always written during the H period, it is possible to write a sufficient black level signal for the response characteristics of the liquid crystal panel 8.

In the period of T6 to T7, the horizontal start signal STH is always at high level, but the vertical start signal S
The HV and the vertical shift control signal VMC change to high level, and the vertical shift clock signal VCP is supplied to the liquid crystal panel 8. Therefore, in this period, the lines 401 to 480 of the liquid crystal panel 8 are scanned from the top to the bottom, and the image data of A406 (black level) is read from the lines 401 to 480 of the liquid crystal panel in the writing time of 1/80 of the normal time. The lines are sequentially written.

In the period of T7 to T8, the horizontal start signal STH changes to low level, the vertical start signal SHV changes to low level, and the vertical shift control signal VM.
C holds the high level, and the vertical shift clock signal V
CP is not supplied to the liquid crystal panel 8. Therefore, during this period, the 401st line to the 480th line of the liquid crystal panel 8 are not scanned, and the liquid crystal panel 8 is not scanned during the previous T6 to T7 periods.
The image data of A406 written in is held as it is.

In this way, the writing operation for one screen is completed, and the liquid crystal panel 8 having 480 lines has 1
The input effective image information is displayed on lines 400 to 400, and black is displayed on lines 401 to 480.

Then, when the vertical start signal STV changes from the low level to the high level, scanning of the next field is started.

In the present embodiment, the frequency of the vertical shift clock signal VCP during the vertical blanking period is set to 80 fH.
However, there is no problem if this frequency is 79 fH or higher.

As described above, by varying the horizontal start signal STH, the vertical start V signal STV, the vertical shift clock signal VCP, and the vertical shift control signal VMC supplied during the vertical blanking period, various computers can be supported. An optimal image can be displayed.

[0068]

According to the present invention, with the above-described configuration, even when different image signals are input from various computers, it is possible to achieve optimum operation without using the A / D conversion circuit, the memory, and the D / A conversion circuit. Images can be displayed.

Further, by switching the vertical scanning direction of the liquid crystal panel during the vertical blanking period, it is possible to display a sufficient black level in the non-signal portion.

[Brief description of drawings]

FIG. 1 is a block diagram showing a liquid crystal display device of the present invention.

FIG. 2 is a block diagram of a liquid crystal panel constituting the liquid crystal display device of the present invention.

FIG. 3 is a timing chart for explaining the operation of the liquid crystal display device of the present invention.

FIG. 4 is a block diagram showing a conventional liquid crystal display device.

[Explanation of reference symbols] 1 PLL circuit 3 Microcomputer 8 Liquid crystal panel 9 Timing pulse generation circuit 9A Line counter 9B Data comparison circuit 9C Polarity control signal generation circuit 9D Horizontal shift clock signal generation circuit 9E Horizontal start signal generation circuit 9F Vertical start signal generation circuit 9G Vertical shift control signal generation circuit 9H First vertical shift clock signal generation circuit 9I First vertical shift clock signal generation circuit 9J Switch 10 Polarity inversion circuit

Claims (11)

[Claims] 1. A liquid crystal display means for inputting an image signal to display an image, a microcomputer for outputting a discrimination signal according to a connected computer, and a discrimination signal from the microcomputer and a horizontal synchronizing signal as inputs. PLL means for creating a sampling clock signal and a comparison target signal having the same period as the horizontal synchronizing signal, and the liquid crystal display means based on the sampling clock signal and the comparison target signal from the PLL means and the discrimination signal from the microcomputer Horizontal start signal producing means for producing a horizontal start signal for starting horizontal scanning of the liquid crystal display device, and a horizontal shift clock signal for producing a horizontal shift clock signal corresponding to the horizontal pixels of the liquid crystal display means. Creating means and a vertical start signal for starting the vertical scanning of the liquid crystal display means Of vertical start signal generating means, vertical shift clock signal generating means for generating a vertical shift clock signal corresponding to a pixel in the vertical direction of the liquid crystal display means, and an up / down control for controlling vertical scanning of the liquid crystal display means. A liquid crystal display device, comprising: a timing pulse generating means having a vertical shift control signal generating means for generating a shift control signal. 2. The vertical shift clock signal creating means includes a first vertical shift clock signal creating means for creating a first vertical shift clock signal having a frequency of 1 / A of the horizontal synchronizing signal, and N times the horizontal synchronizing signal. A second vertical shift clock signal generating means for generating a second vertical shift clock signal having a frequency, and the first vertical shift clock signal and the second vertical shift clock signal are generated during a vertical blanking period of an input image signal. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is selectively switched. 3. The liquid crystal display device according to claim 1, wherein the vertical shift control signal generating means switches the direction of vertical scanning of the liquid crystal display means during a vertical retrace line period of an input image signal. 4. A liquid crystal display means for inputting an image signal to display an image, a microcomputer for outputting a discrimination signal according to a connected computer, and a discrimination signal from the microcomputer and a horizontal synchronizing signal as inputs. PLL means for creating a sampling clock signal and a comparison target signal having the same period as the horizontal synchronizing signal, and timing pulse creating means for receiving the sampling clock signal and the comparison target signal from the PLL means and the discrimination signal from the microcomputer The timing pulse creating means includes counter means for receiving a vertical synchronizing signal and a comparison target signal from the PLL means, and data comparing means for creating a comparison signal by inputting a count value of the counter means. A comparison signal from the data comparison means, a sampling clock signal from the PLL circuit, and And a horizontal start signal creating means for creating a horizontal start signal for starting the horizontal scanning of the liquid crystal display means based on the comparison target signal,
Horizontal shift clock signal generating means for generating a horizontal shift clock signal corresponding to horizontal pixels of the liquid crystal display means based on a sampling clock signal from the PLL means; a comparison signal from the data comparing means; Vertical start signal generating means for generating a vertical start signal for starting the vertical scanning of the liquid crystal display means based on the comparison reference signal from the PLL means, and the sampling clock signal from the PLL means and the comparison target. A first vertical shift clock signal generating means for generating a first vertical shift clock signal having the same frequency as the horizontal synchronizing signal based on the signal, a sampling clock signal from the PLL means and a discrimination signal from the microcomputer. Second vertical shift clock signal having a frequency M times that of the horizontal synchronizing signal Second vertical shift clock signal creating means for creating N times, first vertical shift clock signal from the first vertical shift clock signal creating means, and second vertical shift clock from the second vertical shift clock signal creating means Switching means for selectively switching the signal and vertical shift control signal generating means for generating a vertical shift control signal for controlling vertical scanning of the liquid crystal display means based on the comparison signal from the data comparing means. A liquid crystal display device having. 5. The liquid crystal display device according to claim 4, wherein the vertical shift control signal generating means switches the vertical scanning direction of the liquid crystal display means during a vertical retrace line period of the input image signal. 6. The liquid crystal display device according to claim 4, wherein the switching unit selects the second vertical shift clock signal generating unit during a vertical blanking period of an input image signal. 7. The liquid crystal display device according to claim 4, wherein the horizontal start signal from the horizontal start signal generating means is constantly output during a period in which the second vertical shift clock signal is being generated. . 8. The liquid crystal according to claim 4, wherein the vertical start signal from the vertical start signal generating means is always output during a period in which a second second vertical shift clock signal is being output. Display device. 9. The liquid crystal display according to claim 4, wherein the vertical shift control signal from the vertical shift control signal generating means is inverted during a period in which a second second vertical shift clock signal is being output. apparatus. 10. The frequency of the second vertical shift clock signal from the second vertical shift clock signal generating means is 8
5. The liquid crystal display device according to claim 4, which is 0 times. 11. The liquid crystal display device according to claim 4, wherein the number of times of the second vertical shift clock signal from the second vertical shift clock signal generating means is three.