JPH0520799A - 1-7 encoding circuit of magnetic disk device - Google Patents

Abstract

PURPOSE:To reduce a synchronization delay by stretching the time axis of an external data signal for a factor of two through the use of a stretching circuit synchronized with an external clock and forming the prescribed synchronizing signal processed by the required clock circuit and a first and a second storing circuits, then supplying it to an encoding circuit. CONSTITUTION:By a stretching circuit 3, an external data signal (a) becomes signal (e) whose time axis is stretched for a factor of two synchronized with an external clock (b) and signal (f) which is delayed for one period with respect to the clock (b) and then are inputted to a first and a second storage circuits 7 and 8, respectively. On the other hand, an internal clock (d) is divided into three parts synchronized with an external write signal (c), a clock circuit 6 outputs data fetch signal (h), hold signal (g) and data fetch signal (i), and under the control of these outputs and the clock (d), the circuits 7 and 8 output synchronizing signals (k) and (l), respectively delayed by the signal (g) and are supplied to an encoding circuit 9. By this configuration which does not perform any serial or parallel transformation, the synchronization delay is reduced and the discontinuity of 1-7 encoding words, which is generated during the start of a write operation, is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a magnetic disk device 1-
7 encoding circuit, especially resynchronizing an external data signal synchronized with an external clock signal sent from a higher-order device,
The present invention relates to a 1-7 coding circuit for smoothly connecting a 1-7 code word generated before an external write operation and a 1-7 code word at the start of a write operation.

[0002]

2. Description of the Related Art Conventionally, an encoding circuit of this kind of magnetic disk device doubles an external data signal synchronized with an external clock signal sent from a host device by using the external clock signal. A signal obtained by dividing the internal clock signal sent from the lower circuit by 2 is generated in synchronization with the external write signal sent from the upper device. The logical product of the frequency-divided signal and the external data signal doubled is obtained. Then, a serial data signal synchronized with the internal clock signal is obtained by taking in a signal obtained by performing the logical product of the internal clock signals.

In addition, a load signal which is a signal for encoding is generated in synchronism with an external write signal sent from a host device, a serial data signal is parallelized by 2 bits, and a load signal and a load signal 2 are generated. A bit-parallel data signal was sent to a 1-7 encoding circuit to obtain a 1-7 codeword.

[0004]

In the above-mentioned conventional 1-7 encoding circuit of the magnetic disk device, the conversion delay becomes large because the data signal converted once in series is converted again into the data signal parallel to 2 bits. .. Further, since the load signal is generated in synchronization with the external write signal sent from the host device, the 1-7 code word before the write operation and the 1-7 code word at the start of the write operation are discontinuous. There is a problem that

[0005]

A 1-7 encoding circuit of a magnetic disk device according to the present invention receives an external clock signal sent from a host device and an external data signal synchronized with this external clock signal, and A delay circuit for extending the external data signal and outputting the external data signal; a clock circuit for generating an output signal by receiving an external write signal sent from a host device and an internal clock signal sent from a lower circuit; First and second storage circuits for controlling the extended external data signal of the extension circuit with the output signal of the clock circuit, and the output signals of the first and second storage circuits are converted into 1-7 code words. And an encoding circuit.

[0006]

According to the present invention, the external data signal synchronized with the external clock signal sent from the host device can be resynchronized so that the 1-7 code words generated at the start of the write operation can be continued.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a magnetic disk device 1- of the present invention.
7 is a block diagram showing an example of a 7-encoding circuit. FIG. In FIG. 2, reference numeral 1 is a signal output from an upper circuit (not shown).
2A is a terminal for inputting an external data signal a, 2 is a terminal for inputting an external clock signal b shown in FIG. 2B output from an upper circuit (not shown), and 3 is the external data signal a.
2 is output by a higher-order circuit (not shown). The extension circuit 4 alternately takes in the external clock signal b and outputs the data signal shown in FIG. 2 (e) and the extension data signal shown in FIG. 2 (f). Terminals to which the external write signal c shown in (c) is input, 5
Is a terminal to which the internal clock signal d shown in FIG. 2D output from a lower circuit (not shown) is input.

6 is the internal clock signal d shown in FIG.
Irrespective of the external write signal c shown in FIG. 2C, a signal obtained by dividing the internal clock signal d by 3 is output as a load signal j shown in FIG. 2J, and is synchronized with the external write signal c. Then, a signal obtained by dividing the internal clock signal d by 3 is output as a data fetch signal h shown in FIG. 2 (h), and similarly, the internal clock signal d is divided by 3 in synchronization with the external write signal c. , A clock circuit that outputs a data fetch signal i shown in FIG. 2I as a signal delayed by one cycle of the internal clock signal d from the data fetch signal h.

In the clock circuit 6, if the load signal j shown in FIG. 2 (j) and the data fetch signal h shown in FIG. 2 (h) are in the same phase, one cycle of the internal clock signal d shown in FIG. 2 (d). A hold signal g (see FIG. 2G) for holding the minute data is output, and the load signal j and the load signal j shown in FIG.
If the data acquisition signal i shown in (i) has the same phase, a holding signal g (see FIG. 2 (g)) for holding data for two cycles of the internal clock signal d is output, and FIG. 2 (j) is output. If the load signal j shown in FIG. 2 has a phase different from that of the data capture signal h shown in FIG. 2 (h) and the data capture signal i shown in FIG. 2 (i), the holding signal g (FIG.
(See (g)) is output (in this embodiment, the phase is delayed by one cycle of the internal clock signal d shown in FIG. 2D).

In FIG. 2, the extended data signal e shown in FIG. 2 (e) is fetched by the data fetch signal h shown in FIG. 2 (h).
After delaying by the time indicated by the hold signal g shown in (g), the first synchronous data signal k shown in FIG. 2 (k) is output.
The memory circuit 8 receives the extended data signal f shown in FIG. 2 (f) by the data acquisition signal i shown in FIG.
After delaying the time indicated by the hold signal g shown in (g), the second synchronous data signal 1 shown in FIG.
The memory circuit 9, under the instruction of the load signal j shown in FIG. 2 (j), receives the synchronous data signal k shown in FIG.
1-7 determined by the combination of the synchronous data signals 1 shown in (l)
The coding circuit outputs a code word as a code signal m shown in FIG.

Next, one of the magnetic disk devices having the above structure
The operation of the −7 encoding circuit will be described. First, the extension circuit 3 alternately takes in the external data signal shown in FIG. 2A by the external clock signal b shown in FIG. 2B. In this case, the external clock signal b ₁ shown in FIG. At the rising edge of the data D ₁ of the external data signal a ₁ shown in FIG.
And outputs the extended data signal D ₁ which is extended as shown in FIG. Similarly, the external clock signal b
_At the rising edge of ₂ , the data D ₂ of the external data signal a ₂ is taken in and the extended data signal D ₂ extended as shown in FIG. Similarly, at the rising edge of the external clock signal b ₃ , the external data signal a ₃ is fetched,
The stretched data signal D ₃ stretched as shown in FIG.
Is output.

[0012] Similarly, captures data D ₄ of the external data signal a ₄ at the rising edge of the external clock signal b _4, 2
As shown in (f), the stretched data signal D ₄ stretched is output. Similarly, the data D ₅ of the external data signal a _{5 is taken in} at the rising edge of the external clock signal b ₅ ,
As shown in (e), the stretched data signal D ₅ is output. On the other hand, the clock circuit b divides the internal clock signal d shown in FIG. 2 (d) by 3 in synchronization with the external write signal c shown in FIG. 2 (c), and the data fetch signal shown in FIG. 2 (h). Although it outputs h, when it rises at the position indicated by the external write signal c shown in FIG. 2C, the data fetch signal h ₁ is output at the rising edge of the third division of the internal clock signal d,
Similarly, the data acquisition signal h ₂ is output at the next third division.

Then, the external write signal c shown in FIG.
2D, the internal clock signal d shown in FIG.
Although the data acquisition signal i delayed by the cycle is output, as shown in FIG.
When rising at the position shown by the external write signal c shown in (c), the data capture signal i ₁ is output at the rising edge of the third division of the internal clock signal d, and similarly, the internal clock signal d The data acquisition signal i ₂ is output in the third frequency division subsequent to. Then, the internal clock signal shown in FIG. 2 (d) is divided by 3 into the internal clock signal d regardless of the external write signal c shown in FIG. 2 (c) to output load signals j ₁ and j ₂ .

Then, the load signal j and the data acquisition signal h
If the load signal j and the data fetch signal i are in the same phase, the hold signal g for outputting data for one cycle of the internal clock signal d is output.
The hold signal g for holding data for two cycles is output, and if the load signal j is in a phase different from the data fetch signal h and the data fetch signal i, the hold signal g for not delaying the data is output (this In the embodiment, the phase is delayed by one cycle of the internal clock signal d). As described above, since the data fetch signal h and the data fetch signal i are generated in synchronization with the external write signal c, the data fetch signal h ₁ must be near the center of the extended data signal e _1. Similarly, the data capture signal i ₁ can be located near the center of the stretched data signal f ₁ .

Then, the first memory circuit 7 takes in the extended data signal e shown in FIG. 2 (e) as the data taking-in signal h shown in FIG. 2 (h), and uses the hold signal g shown in FIG. 2 (g). After delaying by the indicated time, the synchronous data signal k shown in FIG. 2 (k) is output. For example, since the data taken in by the data take-in signal h ₁ becomes the synchronous data k ₁ , it is possible to transfer the data from the external clock signal b to the internal clock signal d. Then, the second memory circuit 8 takes in the extended data signal f shown in FIG. 2f by the data take-in signal i shown in FIG. 2i, delays it by the time shown by the hold signal g shown in FIG. 2g, and then shows it in FIG. 2l. The synchronous data signal 1 is output.
For example, since the data captured by the data capture signal i ₁ becomes the synchronous data l ₁ , it is possible to transfer the data from the external clock signal b to the internal clock signal d. In this way, since the synchronous data signal k and the synchronous data signal 1 synchronized with the load signal j as shown in FIG. 2 (j) are obtained by the instruction of the hold signal g, the encoding circuit 9 causes the load signal j
Under the instruction of the synchronous data signal k, the synchronous data signal l
The code signal m can be output as shown in FIG.

[0016]

As described in detail above, according to the 1-7 encoding circuit of the magnetic disk device of the present invention, the external clock signal synchronized with the external data signal is doubled to generate the external write signal. Synchronize with the internal clock signal, take in the data that has been doubled by a clock that is obtained by dividing the internal clock signal by three, and pass the doubled data to the encoding circuit in synchronization with the load signal. As a result, the synchronization delay is reduced, and 1-7 generated at the start of the write operation.
There is an effect that the discontinuity of the code word can be eliminated.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a 1-7 encoding circuit of a magnetic disk device according to the present invention.

FIG. 2 is a timing chart showing waveforms of respective parts of FIG.

[Explanation of symbols]

 3 Extending Circuit 6 Clock Circuit 7 First Memory Circuit 8 Second Memory Circuit 9 Encoding Circuit

Claims (1)

Claim: What is claimed is: 1. An external clock signal sent from a host device and an external data signal synchronized with the external clock signal, and receiving a first extended external data signal and one cycle of the external clock signal. The delay circuit for outputting the second extended external data signal delayed by the delay time, the external write signal sent from the host device and the internal clock signal sent from the lower device, and receiving the internal write signal regardless of the external write signal. Load signal obtained by dividing the clock signal, data acquisition signal obtained by dividing the internal clock signal in synchronization with the external write signal, internal clock signal divided by the internal clock from the data write signal The data acquisition signal delayed by one cycle of the signal is output, and the phase relationship between the load signal and the data acquisition signal and the relationship between the load signal and the data acquisition signal delayed by one cycle A clock circuit for outputting a hold signal by correlation, the first
The first storage circuit which receives the extended external signal and the data capture signal and outputs the synchronous data signal delayed by the time indicated by the hold signal, and the second extended external signal which is delayed by one cycle. A second memory circuit which receives the data capture signal and outputs a synchronous signal delayed by the time indicated by the hold signal; and a synchronous signal of the first memory circuit and a second memory circuit under the instruction of the load signal. 1-7 encoding circuit for converting to a 1-7 code word determined by a combination with the synchronizing signal of the storage circuit and outputting the code word.