JPH0723345A - Time base correcting device - Google Patents

Abstract

PURPOSE:To reduce the scale of a time base correcting circuit by enabling a memory to be variable the phase relation between the writing timing of data and the reading timing thereof in a certain degree. CONSTITUTION:A clock and a reference signal whose phase is synchronized with that of a horizontal synchronizing signal is outputted from a Hi-PLL circuit in a clock and reference signal generating circuit 10. An ADC 1 converts an input signal into a digital signal by using a clock outputted from the circuit 10. A control circuit 5 generates a write control signal for an FIFO 3 in accordance with the 1st clock and a horizontal reference signal outputted from the circuit 10. A data processing circuit 2 executes the data processing of the input signal in accordance with the control signal generated from the circuit 5 and writes the processed data in the FIFO 3. The circuit 5 outputs also reference signal for determining the reading timing of the FIFO 3. Reading from the FIFO 3 and writing in a picture memory 4 are a series of operation and processed by the 2nd clock generated by a Lo-PLL in the circuit 10. Thereby a conversion circuit 6 synchronizes the FIFO reading reference signal outputted from the circuit 5 with I/O operation in/from the memory 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis correction device which can cope with an input image signal having a jitter to some extent in a data rearrangement device used for highly efficient encoding and recording or transmission of image information. .

[0002]

2. Description of the Related Art Since image data has a very large amount of data, high efficiency coding is often used to reduce the amount of data when transmitting or recording. High-efficiency coding is a means for compressing the amount of data by removing the redundant component of image information. For high-efficiency coding, it is necessary to rearrange input image data in the order of blocks suitable for coding. In particular, it is also important to rearrange in block units in order to improve the efficiency of high-efficiency coding and to disperse the influence of errors.

Here, in a system in which two fields of TV signals are collected into one page, and rearrangement is performed in the image memory of one page, the conventional time base correction for eliminating the jitter of the input signal between the analog signal and the rearrangement process. The device will be described. A conventional time axis correction device is shown in FIG.

Reference numeral 1 in FIG. 2 is an AD converter (hereinafter referred to as ADC),
2 is a data processing unit, 3 is a FIFO, 4 is an image memory, 5
Controls the processing from data processing to the input of FIFO3.
Control circuit 7, a second control circuit 7 for controlling from the output of the FIFO 3 to the input of the image memory, 9 is a sync separation circuit,
11 is a TBC memory, 12 is a TBC control circuit, 13
Is a third control circuit for controlling the reading of the image memory, 1
Reference numeral 4 is a PLL for synchronizing with an external signal, and 15 is a clock generation circuit for generating a fixed clock.

First, the sync separation circuit 9 separates a sync signal from a video signal input from the outside and outputs a horizontal sync signal. The PLL circuit 14 matches the phases of the horizontal synchronizing signal and the clock, and outputs the clock and the reference signal which are in phase synchronization with the horizontal synchronizing signal.

Using the clock output from the PLL circuit 14, the ADC 1 converts the input video signal into digital data. The converted digital data is written in the TBC memory 11 according to a signal output from the TBC control circuit 12 and a clock phase-locked with the input signal.
The data written in the TBC memory 11 is read according to the first fixed clock output from the clock generation circuit 15. Further, the TBC control circuit 12 outputs a reference signal serving as a reference for the data output from the TBC memory 11. The first control circuit 5 is the TBC control circuit 12
The operation is started based on the reference signal output from. The data is subjected to data processing such as filtering according to the control signal output from the first control circuit 5, and is written in the FIFO 3. The first control circuit 5 outputs a reference signal for reading data from the FIFO 3. The second control circuit 7 starts operating in accordance with the reference signal output from the first control circuit 5. According to the second fixed clock generated by the clock generation circuit 15 and the reference signal output from the first control circuit 5, a control signal for reading data from the FIFO 3 in the second control circuit 7 and data in the image memory 4 Generate a control signal for writing. The data written in the FIFO 3 is read according to the control signal output from the second control circuit 7 and written in the image memory 4. The second control circuit 7 generates a reference signal for reading data from the image memory 4. The third control circuit 13 is the clock generation circuit 1
The operation is started according to the second fixed clock output from the control circuit 5 and the reference signal output from the second control circuit 7. The data stored in the image memory 4 is the third control circuit 1
The data is read out while rearranging according to the control signal from 3.

[0007]

However, in the above-mentioned conventional configuration, the time axis correction process is required before the data rearrangement process is performed, which requires a large-scale memory and a dedicated control circuit, resulting in a memory cost. And increased power consumption.

An object of the present invention is to solve the problems of the conventional recording device and reproducing device.

[0009]

In order to solve the above-mentioned problems, according to the present invention, when one field or a plurality of fields are set to one page, the input moving image data is one page of image memory for each page. A time axis correction device for recording and outputting in a block unit after rearranging in a block unit, and writing the next image data in the image memory after synchronization for synchronization of an analog video input signal (for example, an output signal of an analog VTR). A sync separation circuit that separates signals, and an H that has a fast response to fluctuations in the sync signal output from the sync separation circuit
i_PLL and Low, which has a slow response to changes in the synchronization signal
_PLL, a clock and reference signal generation circuit, an ADC for converting an analog video input signal into digital data according to a first clock generated by the clock and reference signal generation circuit Hi_PLL, and a first clock. A first control circuit that generates a control signal for each processing circuit based on a first reference signal that is generated by Hi_PLL, and processing such as a filter according to a first clock and a control signal that is output from the first control circuit. And a FIFO for writing data in accordance with a first clock and a control signal from the first control circuit, and a clock and reference signal generation circuit for reading the reference signal of the FIFO output from the first control circuit. Conversion circuit that synchronizes with the second clock and the second reference signal generated by the Low_PLL of A second control circuit for generating a read control signal of the FIFO and the image write control signal of the memory of one page in accordance with FIFO read reference from the second
Clock and Low of clock and reference signal generation circuit
It is characterized by comprising a third control circuit for controlling the reading of the image memory according to the second reference signal generated by the PLL and a one-page image memory for rearranging the data. .

[0010]

According to the present invention having the above-described structure, when the input image data is rearranged, the phase relationship between the timing of writing the data in the memory and the timing of reading the data can be changed to some extent before the rearrangement processing. The scale of the time axis correction circuit to be performed can be reduced. This makes it possible to greatly reduce the circuit scale and power consumption of the system.

[0011]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 shows the operation timing in the conversion circuit.
FIG. 3 shows the timing with respect to changes in writing and reading in the image memory. In FIG. 1, 1 is an ADC, 2 is a data processing circuit, 3 is a FIFO, 4 is an image memory for one page, 5 is a first control circuit for controlling filter processing and writing in the FIFO, and 6 is a first clock. A conversion circuit for converting a signal synchronized with the second clock into a signal synchronized with a second clock, 7 is a second control circuit for controlling the reading of the FIFO and writing of the image memory 4, and 8 is a control of the reading of the image memory 4. A third control circuit, 9 is a sync separation circuit, and 10 is a clock and reference signal generation circuit composed of a Hi_PLL that has a fast response to changes in the input signal and a Low_PLL that has a slow response to changes in the input signal.

First, the input video signal is separated by a sync separation circuit 9 into a sync signal and output as a horizontal sync signal and a vertical sync signal. Hi_P of the clock and reference signal generation circuit 10
The LL circuit matches the phases of the horizontal synchronizing signal and the clock, and outputs the clock and the reference signal which are in phase synchronization with the horizontal synchronizing signal. Using the clock and the clock from the reference signal generation circuit 10, the ADC 1 converts the input signal into digital data. The first control circuit 5 generates a control signal for data processing and writing of the FIFO 3 according to the first clock and the horizontal reference signal output from the clock and reference signal generation circuit 10. The input signal converted into digital data is subjected to data processing such as filtering according to the control signal generated by the first control circuit 5, and is written in the FIFO 3. Further, the first control circuit 5 outputs a reference signal for determining the read timing of the FIFO 3. FIF
The reading of O3 and the writing of the image memory 4 are a series of operations, and Low_P of the clock and reference signal generation circuit 10 is performed.
It is processed by the second clock generated by LL. Therefore, as shown in FIG. 2, the conversion circuit 6 outputs the FIFO read reference signal output from the first control circuit 5 in synchronization with the second clock synchronized with the input / output of the image memory 4. FIG. 2 shows a case where the first clock has a shorter cycle and a longer cycle than the second clock. The second control circuit 7 generates a read control signal for the FIFO 3 and a write control signal for the image memory in accordance with the converted FIFO read reference signal and clock and the second clock generated by the reference signal generation circuit 10. Second
FIFO according to the control signal output from the control signal 7 of
The data is read from 3 and further written in the image memory 4.
The third control circuit 8 outputs the read control signal of the image memory 4 in accordance with the second clock generated by Low_PLL having a slow response speed to the fluctuation of the input signal and the read reference signal of the image memory 4 for each page. The data stored in the image memory is read while rearranging the data according to the control signal output from the third control circuit 8.

By repeating the above-mentioned operation as shown in FIG. 3, the writing of the image memory is performed in accordance with a large variation reference signal synchronized with a clock whose response is slow with respect to the variation of the input signal, and the reading of the input signal is performed. It is read out according to a reference signal synchronized with a clock that has a slow response to fluctuations. By adjusting the timing of writing and reading of the image memory used for rearrangement to correspond to the variable operation, it is possible to absorb the fluctuation of the input signal. Figure 3
Shows the normal operation and the case where the writing cycle to the image memory becomes shorter and longer, and shows the range where the input fluctuation can be absorbed by the control of the image memory.

In this embodiment, the first clock and the second clock are described as frequencies close to each other, but the same operation is performed even if they are completely different clocks.

[0016]

According to the present invention having the above-described structure, a clock and a horizontal reference signal having a fast response to an input signal variation are generated, and a horizontal reference signal and a clock having a slow response to an input signal variation and a vertical reference signal are generated. Of the image memory is performed in accordance with the synchronized horizontal reference signal, and the reading is performed in accordance with the vertical reference signal and the clock with little fluctuation, thereby changing the timing of writing and reading of the image memory against fluctuations. Try to follow. In this way, fluctuations in the input signal can be suppressed and the capacity of the special TBC circuit can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a time axis correction device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the conversion circuit according to the embodiment of the present invention.

FIG. 3 is a timing chart showing writing and reading of an image memory according to an embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional time axis correction device.

[Explanation of symbols]

 1 ADC 2 Data Processing Circuit 3 FIFO 4 Image Memory 5 First Control Circuit 6 Conversion Circuit 7 Second Control Circuit 8 Third Control Circuit 9 Sync Separation Circuit 10 Clock and Reference Signal Generation Circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H03L 7/22 9182-5J H04N 5/92 5/937 7/24 7734-5C H04N 5/93 C 7/13 Z

Claims (1)

[Claims] 1. When one field or a plurality of fields are set to one page, input moving image data is recorded in an image memory for one page for each page and then rearranged in a block unit and output. A time axis correction device for writing the next image data into the image memory after a fixed time, wherein a sync separation circuit for separating a sync signal of an analog video input signal and fluctuation of a sync signal output from the sync separation circuit To the clock and the reference signal generation circuit, which is composed of a Hi_PLL having a fast response to the clock signal and a Low_PLL having a slow response to the fluctuation of the synchronization signal, and an analog video input according to the first clock generated by the Hi_PLL of the clock and the reference signal generation circuit. An AD converter for converting a signal into digital data, a first clock and Hi_PL
A first control circuit that generates a control signal for each processing circuit based on the first reference signal generated by L, a filter, etc. according to the first clock and the control signal output from the first control circuit. A data processing unit for performing processing, a FIFO for writing data according to a first clock and a control signal from the first control circuit, and a read reference signal of the FIFO output from the first control circuit for the clock. And a conversion circuit for synchronizing with the second clock generated by Low_PLL of the reference signal generation circuit and the second reference signal, and a read control signal of the FIFO according to the second clock and the FIFO read standard from the conversion circuit. A second control circuit that generates a write control signal for the image memory for a page, a second clock, and Low_of the clock and reference signal generation circuit. Time axis correction comprising a third control circuit for controlling the reading of the image memory according to the second reference signal generated by LL and a one-page image memory for rearranging data apparatus.