JPH06152247A - Periodic signal generating circuit - Google Patents

Abstract

PURPOSE:To generate a periodic signal having a period shorter than that of an external reset signal with a small ROM capacity and to change the phase of the periodic signal to the external reset signal without changing the ROM contents. CONSTITUTION:An external reset signal RE is supplied to a load terminal LD of a counter 4. The counted value of the counter 4 is supplied as address data to a ROM 2. m periodic signals outputted from the ROM 2 are outputted through a register 3. Each time the counted value reaches a prescribed value, a clear signal SCLR is supplied to a clear terminal CLR of the counter 4 from the ROM 2. A load value S is loaded into the counter 4 by the signal RE. Thereafter, the counter 4 performs the counting operation with the period of the signal SCLR, and the periodic signal is outputted from the ROM 2. Since the counter 4 is cleared by the signal SCLR, the period signal outputted from the ROM 2 is generated with the small ROM capacity when its period is shorter than the period of the signal RE. The initial value of the counter 4 is changed by the change of the load value S to change the phase of the periodic signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a periodic signal generating circuit suitable for generating a block synchronizing signal or the like in a digital VTR by block coding.

[0002]

2. Description of the Related Art FIG. 6 shows a structural example of a recording system of a digital VTR by block coding.

In the figure, a video signal SV supplied to an input terminal 11 is converted into a digital signal by an A / D converter 12 and supplied to a blocking circuit 13. The blocking circuit 13 is provided for a block coding circuit 16 to be described later, and the blocking circuit 13 divides the screen to form a large number of unit blocks.

Video signal SV supplied to input terminal 11
Is supplied to the sync separation circuit 14, and the sync separation circuit 14
The horizontal sync signal Hsync separated by is supplied to the block sync signal generation circuit 15. Then, the block synchronization signal generation circuit 15 outputs a block synchronization signal in synchronization with the horizontal synchronization signal Hsync, and this block synchronization signal is supplied to the blocking circuit 13. Although not described above, the blocking circuit 13 performs blocking processing in synchronization with the block synchronization signal.

The signal of each unit block output from the blocking circuit 13 is sequentially supplied to the block encoding circuit 16. The block encoding circuit 16 is an encoding circuit (ADR) adapted to the dynamic range of each block.
C circuit), DCT (Discrete Cosine Transform) circuit, etc. are applied.

Further, the output signal of the block coding circuit 16 is supplied to the recording processing circuit 17, and is converted into frame-structured data, framing processing, error correction coding processing for adding error correction parity, and recording data. The recording signal is formed by performing channel encoding or the like to reduce the low frequency band of the signal. Then, the recording signal output from the recording processing circuit 17 is supplied to the magnetic head 18 and recorded on the tape.

Here, as the block synchronizing signal generating circuit 15 described above, a periodic signal generating circuit as shown in FIG. 7 is conventionally used. In the figure, 1 is a counter, 2 is a ROM forming a conversion table, and 3 is a register. An external reset signal RE is applied to the clear terminal CLR of the counter 1.
And the clock CLK is supplied to the clock terminal. The n-bit count value of the counter 1 is supplied to the ROM 2 as address data. And
The m periodic signals output from the ROM 2 are latched by the register 3 in synchronization with the clock CLK, whereby m periodic signals are obtained. When generating the above-mentioned block synchronization signal, the horizontal synchronization signal Hsync is used as the external reset signal RE.

[0008]

By the way, in the periodic signal generating circuit shown in FIG. 7, even when a signal having a shorter period than the external reset signal RE is generated, the count output for one period of the external reset signal RE is performed. RO of corresponding capacity
There was a problem that required M. Further, since the phase relationship of the periodic signal with respect to the external reset signal RE is uniquely determined by the contents stored in the ROM, there is a problem that the degree of freedom is small.

Therefore, according to the present invention, a periodic signal having a shorter period than the external reset signal can be generated with a small ROM capacity, and the phase of the periodic signal with respect to the external reset signal can be freely changed without changing the ROM contents. And a periodic signal generating circuit.

[0010]

A periodic signal generating circuit according to the present invention comprises a counter having a load terminal and a clear terminal, and a ROM for generating a periodic signal using the count output of this counter as address data. The external reset signal is supplied to the
A clearer signal is supplied.

[0011]

In the present invention, since the clear signal is supplied from the ROM to the counter to clear it, the ROM does not need to have a capacity corresponding to the count output for one cycle of the external reset signal, and the It becomes possible to generate a periodic signal having a period shorter than the period with a small ROM capacity. The initial value of the counter can be changed by changing the load value of the counter.
It is possible to freely change the phase of the periodic signal with respect to the external reset signal without changing the contents of the OM.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, parts corresponding to those in FIG. 7 are designated by the same reference numerals.

In the figure, 4 is a counter having a load terminal LD in addition to the clear terminal CLR. An external reset signal RE is supplied to the load terminal LD of the counter 4, and an n-bit load value S is supplied to the counter 4. The load value S can be freely set by a switch (not shown) or the like. The clock CLK is supplied to the clock terminal of the counter 4.

The n-bit count value output from the counter 4 is supplied as address data to the ROM 2 forming the conversion table. The m periodic signals output from the ROM 2 are clocked by the clock CLK by the register 3.
Are latched in synchronism with, thereby obtaining m sync signals.

Further, one of the m periodic signals output from the ROM 2 is used as a clear signal SCLR in the counter 4
Is supplied to the clear terminal CLR. This clear signal SCL
R becomes low level “0” every time the count value of the counter 4 supplied as address data becomes “S + L”, and becomes high level “1” in other periods. Therefore,
The count value of the counter 4 changes from "0" to "S + L", and data for generating m periodic signals from addresses "0" to "S + L" is written in the ROM 2.

In the above configuration, when the external reset signal RE is supplied to the load terminal LD of the counter 4 (see FIG. 2).
B), the counter 4 is loaded with the load value S in synchronization with the clock CLK (shown in FIG. 2A), and becomes the initial value of the counter 4 (shown in FIG. 2C).

After that, when the counter 4 is counted up by the clock CLK and the count value becomes "S + L", the clear signal SCLR output from the ROM 2 becomes low level "0" (shown in FIG. 2D) and the clock CL
The counter 4 is cleared in synchronization with K (illustrated in FIG. 2C). Hereinafter, in the counter 4, until the external reset signal RE is supplied to the load terminal LD, “0” to “S + L”
The count operation of is repeated and the maximum (S
A periodic signal of + L + 1) clock period is output, which is latched by the register 3 and output.

In this example, the counter 4 is cleared by the clear signal SCLR output from the ROM 2, so that when the cycle of the periodic signal output from the ROM 2 is shorter than the cycle of the external reset signal, the ROM 2 is external. It is not necessary to have a capacity corresponding to the count output for one cycle of the reset signal RE, and the cyclic signal can be generated with a small ROM capacity.

Further, in this example, since the load value S is loaded into the counter 4 by the external reset signal RE, the initial value of the counter 4 can be changed by changing the load value S, and the ROM contents can be changed. The phase of the periodic signal with respect to the external reset signal RE can be freely changed without doing so.

By the way, in a commercially available counter such as TTL, clearing is prioritized over load as an internal circuit. Therefore, when the counter 4 in the example of FIG. 1 prioritizes clearing over loading, the following problems occur.

That is, first, the load value S of the counter 4 is
Is set to 0, and when the timing of the external reset signal RE and the clear signal SCLR becoming the low level “L” in the steady operation match (shown in FIGS. 3B and D), the phase of the periodic signal output from the ROM 2 Even if the load value S is set to a value other than 0 in order to change, the load value S is not loaded into the counter 4 and the phase of the periodic signal cannot be changed (see FIG. 3C). 3A shows clock C
LK is shown.

FIG. 4 shows another embodiment of the present invention in which such a problem is eliminated. 4, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

In the figure, the external reset signal RE is supplied to the load terminal LD of the counter 4 and also to one input terminal of the AND circuit 5. The clear signal SCLR output from the ROM 2 is supplied to the other input terminal of the AND circuit 5 and also to one input terminal of the AND circuit 6. The output signal of the AND circuit 5 is supplied to the other input terminal of the AND circuit 6. And
The output signal of the AND circuit 6 is supplied to the clear terminal CLR of the counter 4 as a clear signal SCLR '.

This example is constructed as described above, and the other parts are constructed in the same manner as the example of FIG. In this example, when the load value S of the counter 4 is initially set to 0, and the timings at which the external reset signal RE and the clear signal SCLR become low level “L” in the steady operation match (illustrated in FIGS. 5B and 5D). ), The clear terminal CL of the counter 4 from the AND circuit 6
Clear signal SCLR 'supplied to R is at high level "1"
(Illustrated in FIG. 5E). Note that FIG. 5A shows the clock CL
K is shown.

Therefore, even if the timings at which the external reset signal RE and the clear signal SCLR become low level "L" match, the counter 4 is loaded with the load value S by the external reset signal RE (see FIG. 5C). . As a result, the initial value of the counter 4 can be moved to change the phase of the periodic signal output from the ROM 2.

[0026]

According to the present invention, the counter has a ROM.
Because a clear signal is supplied to clear the ROM,
Does not need to have a capacity corresponding to the count output for one cycle of the external reset signal, and a cyclic signal having a cycle shorter than the cycle of the external reset signal can be generated with a small ROM capacity. Further, since the load value is loaded into the counter by the external reset signal, the initial value of the counter can be changed by changing the load value.
The phase of the periodic signal with respect to the external reset signal can be freely changed without changing the OM contents.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a timing chart showing an operation example of the example of FIG.

3 is a timing chart showing a malfunction example of the example of FIG. 1. FIG.

FIG. 4 is a block diagram showing another embodiment of the present invention.

5 is a timing chart showing an operation example of the example of FIG.

FIG. 6 is a block diagram showing a configuration example of a digital VTR.

FIG. 7 is a block diagram showing a configuration example of a conventional periodic signal generating circuit.

[Explanation of symbols]

 2 ROM 3 register 4 counter 5, 6 AND circuit

Claims (2)

[Claims] 1. A counter having a load terminal and a clear terminal, and a ROM for generating a periodic signal using the count output of the counter as address data, and an external reset signal is supplied to the load terminal.
A periodic signal generating circuit, wherein a clear signal is supplied from the ROM to the clear terminal. 2. A periodic signal generating circuit comprising a gate circuit for prioritizing clearing over load in the counter, and blocking the clear signal when the external reset signal and the clear signal have the same timing.