JP3156566B2 - Video signal recording device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for converting an analog video signal into a digital signal and recording the digital signal in a digital state.
The present invention relates to a video signal processing device.

[0002]

2. Description of the Related Art FIG. 11 shows an example of a conventional video signal recording apparatus. In FIG. 11, reference numeral 201 denotes a synchronization separation unit that separates a synchronization signal 211 and an analog video signal 215 from the video signal 210. Reference numeral 202 denotes a vertical synchronization signal detection unit that detects a vertical synchronization signal portion from the synchronization signal 211 and outputs a vertical synchronization signal detection flag 212. Reference numeral 203 denotes a frame reference signal generation unit that generates a frame reference signal 213 at a cycle of the vertical synchronization signal detection flag 212. 204
Is a horizontal synchronization signal detecting means for detecting a horizontal synchronization signal portion from the synchronization signal 211 and generating a line reference signal 214.
An A / D converter 205 converts an analog video signal 215 into a digital video signal 216. Reference numeral 206 denotes a video signal 216 in a digital state,
Main video signal processing means for writing data for each line into a memory and processing the data in units of frames in accordance with the line reference signal 214 and the line reference signal 214. The main video signal processing unit 206 performs processing such as compression and addition of an error correction code, and generates recording data 217. A recording unit 207 records the recording data 217.

[0003] As shown in FIG. 2, a video signal 210 has one field in a first field and a second field.
Make up one frame. One field includes a vertical blanking section including a vertical synchronization signal, and an effective image section. Further, the effective image section is configured by horizontal blanking including a horizontal synchronization signal and video data. 1
The field has a total length of 262.5 lines including a vertical blanking portion having a length of 9 lines and an effective image portion having a length of 253.5 lines.

FIG. 12 shows the timing of each block.
The operation will be described. The synchronizing separation means 201 outputs the video signal 21
0 is output as a synchronization signal 211,
To C are output as an analog video signal 215. The vertical synchronization signal detection means 202 detects the portion D of the synchronization signal 211 and outputs a vertical synchronization signal detection flag 212. The frame reference signal generation means 203 inverts the frame reference signal 213 after the time G when the vertical synchronization signal detection flag 212 is input. Frame reference signal 21
3 operates at the field period regardless of the phase of the field of the video signal 210. Horizontal synchronization signal detection means 2
Reference numeral 04 detects a horizontal synchronization signal portion from the synchronization signal 211 and outputs a line reference signal 214. In a period where there is no horizontal synchronization signal, the line reference signal 214 is interpolated at the cycle of the immediately preceding horizontal synchronization signal.

For example, consider the case of an image as shown in FIG. The numerical value M-N (M = 1, 2; an integer between N = 1 to 240 and indicating N = 7 in the figure) on the right in the figure is the M-th
This is data of the Nth line of the field. The main video signal processing means 206 resets the line counter at the change point of the frame reference signal 213, and thereafter, resets the line reference signal 214.
The number of lines is counted at the falling edge of. When the value of the line counter is between 20 and 258, the main video signal processing means 206 writes the digital video signal 216 into the memory as an effective image portion. Also, the frame reference signal 2
It is assumed that the data after the rising of No. 13 is the data of the first field, and the data after the falling is the data of the second field. In the memory, data of the first field and the data of the second field are alternately written for each line. The relationship of the timing of the input signal is shown in FIGS.

FIGS. 13 and 14 show a case where the phase of the field of the video signal 210 and the phase of the frame reference signal 213 match. As shown in FIG. 13, the frame reference signal 2
When 13 rises, the main video signal processing means 206 sets the value of the line counter of the rising line of the frame reference signal 213 to 0 at this time. Further, since the frame reference signal 213 has risen, the subsequent data is used as data of the first field. Then, the line counter stores the data after 20 in the odd areas M1, M2 of the memory.
3, digital video data 216 is written into M5 and M7. Next, as shown in FIG.
When 13 falls, the main video signal processing means 206 sets the value of the line counter of the falling line of the frame reference signal 213 to 0 at this time. Further, since the frame reference signal 213 has fallen, the subsequent data is used as data of the second field. Then, the line counter stores the data after 20 in the even areas M2, M2 of the memory.
4, write the video data 216 to M6 and M8. Thus, one frame of data is written to the memory. FIG. 17 shows the fields of the video signal 210 and the frame reference signal 21.
3 shows the relationship between the input image and the memory when the phase of 3 is matched.

FIGS. 15 and 16 show the case where the phases of the field of the video signal 210 and the frame reference signal 213 are inverted. As shown in FIG. 16, when the frame reference signal 213 rises, the main video signal processing unit 206 sets the value of the line counter of the rising line of the frame reference signal 213 to 0 at this time. Further, since the frame reference signal 213 has risen, the subsequent data is used as data of the first field. Then, the line counter stores the data after 20 in the odd area M1,
The video data 216 is written to M3, M5, and M7. Next, as shown in FIG. 15, when the frame reference signal 213 falls, at this time, the main video signal processing means 206
Sets the value of the line counter of the falling line of the frame reference signal 213 to 0. Further, since the frame reference signal 213 has fallen, the subsequent data is
Field data. Then, the line counter stores the data after 20 in the even areas M2, M4, M of the memory.
6. Write digital video data 216 to M8.
Thus, one frame of data is written to the memory. However, when writing the video data to the memory because the field of the video signal 210 and the phase of the frame reference signal 213 are inverted, M1 and M2, M3 and M
4, M5 and M6 and M7 and M8 are written in reverse. FIG. 18 shows the relationship between the field of the video signal 211, the input image when the phase of the frame reference signal 213 is inverted, and the memory. Thereafter, the main video signal processing unit 206 performs processing such as adding an error correction code to the frame-based video signal written in the memory,
17 is generated. The recording unit 207 records the recording data 217 generated by the main video signal processing unit 206.

With the above-described configuration, when the input video signal 210 is converted to digital and recorded, when a signal whose field is discontinuous due to a channel change or the like is recorded, the input video signal 210 And the phase of the frame reference signal 213 are inverted, and the first field and the second field are recorded in reverse.

[0009]

In the conventional video signal recording apparatus described above, when recording a signal having discontinuous fields such as a channel change of a TV receiver, a first field and a second field are recorded. May be inverted. When the signal is recorded, the first field and the second field are recorded in reverse. When a signal in which the first field and the second field are recorded in reverse is reproduced, there is a problem that the reproduced image fluctuates up and down.

The present invention solves the above-mentioned conventional problems and provides a video signal recording apparatus in which a reproduced image does not fluctuate up and down even when a signal of an input video signal has a discontinuous field. The purpose is to do.

[0011]

SUMMARY OF THE INVENTION In order to solve the above-mentioned conventional problems, the present invention provides a synchronizing separation means for separating an analog video signal and a synchronizing signal from a video signal, and detecting a vertical synchronizing signal section from the synchronizing signal. Vertical synchronization signal detection means for outputting a vertical synchronization signal detection flag, horizontal synchronization signal detection means for detecting a horizontal synchronization signal portion from the synchronization signal and outputting a line reference signal, and a vertical synchronization signal detection flag and a frame reference signal to be described later. A phase control means for generating a phase control signal for controlling a timing of changing a frame reference signal to be described later, a frame reference signal generation means for generating a frame reference signal by the phase control signal, and a digital video signal Digital video signals are converted into frame units using an AD converter that converts them into signals, and a frame reference signal and a line reference signal. Comprising a main video signal processing means for generating processed record data, and recording means for recording data.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention according to claim 1 of the present invention provides a synchronous separating means for separating an analog video signal and a synchronizing signal from a video signal, and a vertical synchronizing signal detecting section for detecting a vertical synchronizing signal portion from the synchronizing signal. Vertical synchronization signal detection means for outputting a signal detection flag, horizontal synchronization signal detection means for detecting a horizontal synchronization signal portion from the synchronization signal and outputting a line reference signal,
Frame reference signal generating means for generating a frame reference signal based on a phase control signal described later; and the vertical synchronization signal detection flag and the frame reference signal cause the rising of the frame reference signal to take a time m (m: Control so that the falling of the frame reference signal is after a time n (n is a positive number and m <n) from the vertical synchronization signal detection flag. Phase control means for generating the phase control signal, an AD converter for converting the analog video signal to a digital video signal, and converting the digital video signal in frame units by the frame reference signal and the line reference signal. Main video signal processing means for processing and generating recording data; and recording means for recording the recording data. , Thus, even when a field like a channel change was recorded discrete signal, it is recorded without the playback picture shakes up and down.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a video signal recording device according to an embodiment of the present invention. In FIG. 1, reference numeral 101 denotes a synchronization separation unit that separates a synchronization signal 111 and an analog video signal 115 from a video signal 110. Reference numeral 102 denotes a vertical synchronization signal detection unit that detects a vertical synchronization signal portion from the synchronization signal 111 and outputs a vertical synchronization signal detection flag 112. Reference numeral 104 denotes a phase control unit that generates a phase control signal 114 that controls a timing at which the frame reference signal 113 is changed, based on the vertical synchronization signal detection flag 112 and the frame reference signal 113.
103 is a frame reference signal generating means for changing the frame reference signal 113 by the phase control signal 114. 105
Is a horizontal synchronizing signal detecting means for detecting a horizontal synchronizing signal portion from the synchronizing signal 111 and outputting a line reference signal 117.
An A / D converter 106 converts an analog video signal 115 into a digital video signal 116. Reference numeral 107 denotes a digital video signal 116 for converting a frame reference signal 113
Main video signal processing means for writing data for each line into a memory in accordance with the line reference signal 117 and processing the data in frame units. The main video signal processing unit 107 generates recording data 118 by performing processing such as compression and addition of an error correction code. Reference numeral 108 denotes a recording unit that records the recording data 118.

As shown in FIG. 2, the video signal 110 has 1 in two fields of a first field and a second field.
Make up one frame. One field includes a vertical blanking section including a vertical synchronization signal, and an effective image section. Further, the effective image section is configured by horizontal blanking including a horizontal synchronization signal and video data. 1
The field has a total length of 262.5 lines including a vertical blanking portion having a length of 9 lines and an effective image portion having a length of 253.5 lines.

FIG. 3 shows the timing of each block, and the operation will be described. The synchronizing separation means 101 outputs the video signal 110
Are separated into a synchronization signal 111 and a portion from B to C into a video signal 115. The vertical synchronization signal detection means 102 detects the portion D of the synchronization signal 111 and outputs a vertical synchronization signal detection flag 112. Phase control means 10
4 is a phase control signal 11 based on the value of the frame reference signal 113 when the vertical synchronization signal detection flag 112 is HIGH.
4 is controlled. When the vertical synchronization signal detection flag 112 is HIGH, the frame reference signal 113
Is LOW, the phase control signal 114
Is output. If the frame reference signal 113 is HIGH, a phase control signal 114 is output at timing F. That is, the phase control signal 114 is output such that the rising of the frame reference signal 113 is at timing E and the falling of the frame reference signal 113 is at timing F.
The vertical synchronization signal detection flag 112 and the frame reference signal 1
(Table 1) shows the relationship between T.13 and the phase control signal 114.

[0016]

[Table 1]

The frame reference signal generating means 103 changes the frame reference signal 113 at the timing when the phase control signal 114 is input. At this time, even when the fields of the input video signal 110 are discontinuous, the frame reference signal 113 toggles the frame reference signal 113 at a field cycle regardless of the fields of the input video signal 110. 113 (a), 11 in FIG.
4 (a) is a pattern in which the frame reference signal 113 rises at timing E. 113 (b) and 114 (b) are patterns in which the frame reference signal 113 falls at the timing F. The horizontal synchronizing signal detecting means 105 outputs the synchronizing signal 11
1, the horizontal synchronization signal portion is detected, and the line reference signal 11 is detected.
7 is output. In a period in which there is no horizontal synchronization signal portion in the synchronization signal 111, the line reference signal 117 is generated in the cycle of the immediately preceding horizontal synchronization signal portion.

For example, consider the case of an image as shown in FIG. The numerical value M-N (M = 1,2, an integer between N = 1 to 240 and indicating N = 7 in the figure) on the right side of the figure is
This is data on the Nth line of the Mth field. The main video signal processing means 107 resets the line counter at the transition point of the frame reference signal 113, and thereafter, resets the line reference signal 1
The number of lines is counted at the falling edge of 17. The main video signal processing means 107 writes the digital video signal 116 whose line counter value is from 20 to 258 to the memory as an effective image portion. Also, the frame reference signal 11
The data after the rising edge of 3 is the data of the first field,
The data after the fall is the data of the second field. Data of the first field and the second field are alternately written to the memory for each line. The relationship of the timing of the input signal is shown in FIG. 5, FIG. 6, FIG. 7, and FIG.

FIGS. 5 and 6 show the case where the phase of the field of the video signal 110 and the phase of the frame reference signal 113 match. As shown in FIG. 5, when the frame reference signal 113 rises, the main video signal processing means 107
Sets the value of the line counter of the rising line of the frame reference signal 113 to 0, and sets the subsequent data to the first
Field data. Then, the line counter stores the data after 20 in the odd areas M1, M3, M of the memory.
5. Write a digital video signal 116 to M7. Next, as shown in FIG. 6, when the frame reference signal 113 falls, at this time, the main video signal processing means 107
The value of the line counter of the falling line of the frame reference signal 113 is set to 0, and the subsequent data is used as the data of the second field. And the line counter is 20
Subsequent data is stored in even areas M2, M4, M6,
The digital video signal 116 is written to M8. Thus, one frame of data is written to the memory. FIG. 9 shows a field of the video signal 110 and a frame reference signal 113.
3 shows a relationship between an input image and a memory when the phases are the same.

FIGS. 7 and 8 show the case where the phase of the field of the video signal 110 and the phase of the frame reference signal 113 are inverted. As shown in FIG.
Rises, the main video signal processing means 10
7 sets the value of the line counter of the rising line of the frame reference signal 113 to 0, and sets subsequent data as data of the first field. Then, the line counter stores the data after 20 on the odd-numbered areas M1, M3,
The digital video signal 116 is written into M5 and M7.
Next, as shown in FIG. 7, when the frame reference signal 113 falls, the main video signal processing means 107
Sets the value of the line counter of the falling line of the frame reference signal 113 to 0, and sets the subsequent data to the second
Field data. Then, the line counter stores the data after 20 in the even areas M2, M4, M of the memory.
6. Write a digital video signal 116 to M8. Thus, one frame of data is written to the memory. FIG.
0 indicates the relationship between the field of the video signal 110, the input image when the phase of the frame reference signal 113 is inverted, and the memory.

Thereafter, the main video signal processing means 107 performs processing such as adding an error correction code to the video signal in units of frames written in the memory to generate recording data 118.
108 records the recording data 118. With the above configuration, when the video signal 110 is converted to digital and recorded, the rising of the frame reference signal 113 is performed even when the fields of the video signal 110 are discontinuous.
By controlling the fall to timing F at timing E, the video signal 110 and the frame reference signal 113 are controlled.
To prevent the reproduced image from fluctuating up and down due to the phase inversion.

[0022]

According to the present invention, a synchronizing separation means for separating an analog video signal and a synchronizing signal from a video signal, a vertical synchronizing signal detecting means for detecting a vertical synchronizing signal portion from the synchronizing signal and outputting a vertical synchronizing signal detection flag, A horizontal synchronization signal detecting means for detecting a horizontal synchronization signal portion and outputting a line reference signal, and a phase control signal for controlling a timing of changing a frame reference signal to be described later based on a vertical synchronization signal detection flag and a frame reference signal. Phase control means, a frame reference signal generating means for generating a frame reference signal based on the phase control signal, an AD converter for converting an analog video signal into a digital video signal, and a digital signal based on the frame reference signal and the line reference signal. Main video signal processing means for processing the video signal in units of frames to generate recording data; By a recording means for recording, VH
Even in the case of recording a signal in which the field of the input signal is discontinuous, as in the splice recording of the S system VTR, the recording can be performed without shaking the screen up and down during reproduction.

[Brief description of the drawings]

FIG. 1 is a block diagram of a video signal recording device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a video signal in the video signal recording device.

FIG. 3 is a timing chart of the video signal recording device.

FIG. 4 is a diagram showing an example of a video signal on a screen of the video signal recording device.

FIG. 5 is a timing chart of the video signal recording device.

FIG. 6 is a timing chart of the video signal recording device.

FIG. 7 is a timing chart of the video signal recording device.

FIG. 8 is a timing chart of the video signal recording device.

FIG. 9 is a relationship diagram between a video signal on a screen of the video signal recording device and a memory;

FIG. 10 is a diagram showing a relationship between a video signal on a screen of the video signal recording device and a memory;

FIG. 11 is a block diagram of a conventional video signal recording device.

FIG. 12 is a timing chart of a conventional example.

FIG. 13 is a timing chart of a conventional example.

FIG. 14 is a timing chart of a conventional example.

FIG. 15 is a timing chart of a conventional example.

FIG. 16 is a timing chart of a conventional example.

FIG. 17 is a diagram showing a relationship between a video signal on a screen and a memory according to a conventional example.

FIG. 18 is a diagram showing a relationship between a video signal on a screen and a memory according to a conventional example.

[Explanation of symbols]

 Reference Signs List 101 synchronization separation means 102 vertical synchronization signal detection means 103 frame reference signal generation means 104 phase control means 105 horizontal synchronization detection means 106 A / D converter 107 main video signal processing means 108 recording means

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hidemi Oka 1006 Oaza Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (58) Field surveyed (Int. Cl. ⁷ , DB name) H04N 5/91- 5/956 H04N 9/79-9/898

Claims (1)

(57) [Claims] 1. A synchronizing separation unit for separating an analog video signal and a synchronizing signal from a video signal, a vertical synchronizing signal detecting unit for detecting a vertical synchronizing signal portion from the synchronizing signal and outputting a vertical synchronizing signal detection flag, Horizontal synchronization signal detection means for detecting a horizontal synchronization signal portion from a synchronization signal and outputting a line reference signal; frame reference signal generation means for generating a frame reference signal based on a phase control signal to be described later; the vertical synchronization signal detection flag and the frame The rising edge of the frame reference signal is controlled by the reference signal so that the rising edge of the frame reference signal is after a time m (m is a positive number) from the vertical synchronization signal detection flag, and the falling edge of the frame reference signal is detected by the vertical synchronization signal detection flag. Phase control for generating the phase control signal for controlling after a time n (n is a positive number and m <n) An AD converter for converting the analog video signal into a digital video signal; a main video for processing the digital video signal on a frame basis by the frame reference signal and the line reference signal to generate recording data A video signal recording device comprising: signal processing means; and recording means for recording the recording data.