JP2599436B2 - Image enlargement display method and apparatus - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an enlarged display apparatus for a video signal, and more particularly to an enlarged video signal display method suitable for enlarging and displaying a digitalized video signal. It concerns the device.

[Prior Art] In recent years, the cost of digital memories has been reduced, and consumer video equipment having a large capacity digital video signal memory and capable of performing various special processes has appeared on the market.

For example, as an example, VTR (Video Tape Recorder) realizes noiseless search, and VDP
(Video Disc Player)
This allows trick play on CLV (constant linear velocity) discs. There is also a digital noise reducer utilizing a memory as a one-field delay element. Such special processing can be realized if there is at least one field of memory. Therefore, in consideration of cost, most consumer devices have only one field of capacity.

By the way, a circuit for enlarging and displaying a part of a screen as a special process also performed using a memory has conventionally existed. As the enlargement method, there are a method of changing the sampling frequency in accordance with the enlargement ratio and writing the same in a memory at the time of digital conversion of the video signal, and a method of performing interpolation insertion on the digitalized video signal data. In the former method, the circuit scale becomes large because the frequency of the sampling clock is changed. In the latter method, a method of performing interpolation when reading data from a memory is general and can be easily realized. For example, when the data is enlarged by a factor of two (area ratio is quadrupled), the same data is read out two times at a time, that is, read out twice and interpolation is performed. Incidentally, as this kind of prior art, Japanese Patent Laid-Open No.
No. 100183 can be mentioned.

[Problem to be Solved by the Invention] However, when the latter enlargement processing is performed in a memory having a capacity of one field, the following problem occurs.

Hereinafter, the problem will be described with reference to FIG. 14th
In the figure, the horizontal axis indicates the time direction, and the vertical axis indicates the vertical direction of the screen or the writing / reading direction of the memory. In addition, here, in order to make the description easy to understand, the description will be made with the enlargement magnification being twice. First, writing to the memory is performed from A to B.
Thereafter, the process returns to the memory start point C, that is, the upper end of the screen, and continues writing toward the end point D of the second field. Hereinafter, D, E, ... are written. On the other hand, reading is performed as follows. For example, in the case of enlarging the upper part of the screen, 1/2 of the number of vertical lines (1/4 in data amount) is read from A to F in one field time. At this time, it goes without saying that the interpolation as described above is performed and an enlarged image is obtained. Similarly, at the bottom of the screen,
Reading from M to B takes one field time,
You can enlarge it. However, if it is attempted to enlarge a portion other than the uppermost portion and the lowermost portion, for example, the central portion of the screen, the read timings H to I overlap the write timings A and B, as is apparent from the drawing. This means that the time relationship between writing and reading is reversed. This is not a problem when enlarging a still image, but causes a problem that a normal reproduced image cannot be obtained when enlarging a moving image. It is also conceivable to change the read start timing so that time reversal does not occur. However, in this case, every time the enlargement position is changed, discontinuity of vertical synchronization occurs, resulting in a very unsightly reproduced image.

Conventionally, when a movie for a theater was packaged as a video, trimming was not performed, and a black screen was provided at the top and bottom of the screen while maintaining the original aspect ratio to match the aspect ratio of the TV. is there. In such video software, the entire screen can be viewed like watching a movie in a theater, but the picture itself becomes smaller,
The problem that it becomes hard to see arises. Therefore, when performing enlargement, it is very convenient if there is a function that can perform trimming on such an image without bothering the user. However, at present,
No one having such a function is found.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-described problems, to enlarge an image with a memory for one field, and to enlarge an image to be appropriately enlarged for video software that has not been trimmed. It is to provide a method and an apparatus.

[Means for Solving the Problems] In an image enlargement and display method according to the present invention, a digital video signal is written in a memory for one field, and a part of an image written in the memory is read out over one field period. An image enlargement display method for enlarging an image, wherein the writing and reading are continued with the writing field start timing and the reading start timing being shifted by about 1/2 field time. It is assumed that.

An enlarged image display device according to the present invention includes a memory for storing a digital video signal for one field, a writing unit for writing the digital video signal to the memory, and a reading unit for reading a digital video signal from the memory.
In the image enlargement display device for enlarging an image by reading a part of an image over one field period by the reading means, means for shifting the write field start timing and the read field start timing by approximately 1/2 field time. Is provided.

According to another aspect, an enlarged image display apparatus according to the present invention includes a memory for storing a digital video signal for one field, writing means for writing the digital video signal into the memory, and reading a digital video signal from the memory. Reading means for reading out a part of the image over one field period by the reading means to enlarge the image. Is provided, means for setting timing such that the read memory address moves from the end point of one field to the start point at the time of completion of the operation.

According to still another aspect, an enlarged image display apparatus according to the present invention includes a memory for storing a digital video signal for one field, writing means for writing the digital video signal into the memory, and a digital video signal from the memory. Reading means for reading out a portion of the image over one field period by the reading means to enlarge the image.
When read data corresponding to two fields is read, there is provided means for setting timing so that the write memory address moves from the end point of one field to the start point.

Another enlarged image display apparatus according to the present invention includes a first memory for storing a digital video signal, writing means for writing the digital video signal to the first memory, and a read for reading the digital video signal from the memory. Means for enlarging an image by reading a part of the image over a one-field period by the reading means, wherein the presence of an image in the signal corresponds to a video signal which has not been trimmed. Means for detecting an area to be scanned or a black screen area where no image exists, means for obtaining an enlargement ratio of an image from information obtained by the means, and means for detecting an image according to the enlargement ratio so as to delete the black screen region. Means for performing enlargement is provided.

In this apparatus, the means for detecting the area where the image exists or the area where the image does not exist may perform detection over the first plurality of fields and may not perform detection in the subsequent fields. Means for detecting the presence or absence of characters in the black screen area and generating a detection signal;
Means may be provided for displaying only the black screen area where the character is present in the original size without enlargement in accordance with the detection signal.

[Operation] Hereinafter, the operation of the present invention will be described with reference to FIG. First, writing to the memory is performed as A, B, C, D, E,. Next, the reading is delayed by means for shifting by about 1/2 field time, and is performed from A ', H', M 'as shown in FIG. By reading in this manner, for example, A ', F', C ', G', E ',... At the top of the screen, and H', I ', J', K 'at the center of the screen , L ',... And at the bottom of the screen, M', B ', F', D ', G',..., And do not overlap with the write timing. Therefore, even if the moving image is enlarged in the memory for one field, the time reversal does not occur.

Also, by means of detecting a portion where an image is present, it is possible to know which portion of the picture is present on the playback screen, and thereby it is possible to know the start line and the end line of the image. By using this, the enlargement ratio, the read start address, and the like can be easily obtained. Therefore, trimming by optimal enlargement can be automatically performed.

[Examples of the Invention] Hereinafter, examples of the present invention will be described.

First, a first embodiment will be described with reference to FIGS.

The first is a configuration diagram showing an optical video disc player as an example in the first embodiment. Here, in the description of the present embodiment, the description will be made assuming that the enlargement magnification is twice as an example.

First, a reproduced video signal demodulated by a demodulator (not shown) and input from an input terminal 1 is input to a circuit TBC2 for correcting a time axis. Time axis correction circuit (TB
C) 2, both reference signals are input from a reference signal generating circuit 7 that generates a clock signal CLK serving as a reference for the time axis and a reference horizontal synchronizing signal HD. Do. On the other hand, CLK from reference signal generation circuit 7
The signals are A / D converter 3, field memory 4, write address generator 9, read address generator 10 and D / D
The HD signal is input to the A converter 5, and is input to the write address generation circuit 9, the read address generation circuit 10, the delay circuit 11, and the microcomputer 35. The video signal output from the TBC 2 is input to the A / D converter 3 and the vertical synchronizing signal separating circuit 8, where the vertical synchronizing signal separating circuit 8 separates the vertical synchronizing signal VD into a desired pulse width.
To the write address generating circuit 9 and the delay circuit 11. The delay circuit 11 delays the vertical synchronizing signal VD by approximately 1/2 field time (approximately 7.8 ms) to generate a vertical synchronizing signal VD ', which is input to the read address circuit 10 and the microcomputer 35. The A / D converter 3 converts the input video signal into, for example, an 8-bit digital signal in accordance with the clock signal CLK and sends it to the field memory 4. Note that, in this example, a luminance / color difference separation circuit and a color demodulation circuit are not described for the sake of simplicity. Actually, output terminal 6 from TBC2
Are performed for each of the separated and demodulated luminance and color difference. Synchronization signals are also omitted here for the sake of simplicity. Hereinafter, one of the luminance and color difference signals is described.
The field memory 4 sequentially stores signals according to the write address signal input from the write address generation circuit 9 and the clock signal CLK.

Here, an example of the storage method is shown in FIG. FIG.
The memory address and the storage state of the signal are shown for one bit of the signal. Here, a case will be described in which the frequency of CLK, which is the sampling clock for digital conversion, is four times the frequency (4FSC) of the color subcarrier. First, in order to perform enlargement, processing is easier if a specific video signal is always present at a specific position in the memory. Therefore, if CLK is set to 4FSC, the number of video signal samples is 910 per line, and the actual number of lines in one field is about 254 considering 9 lines in the blank period. As shown in (1), a signal is stored in the memory by a method of designating an address in one line by the lower 10 bits (1024) of the address of the field memory 4 and a line unit address by the upper 8 bits (256). . Therefore, each time the 11th bit increases by 1, the address for one line increases. In the following,
The 10 bits are referred to as an H address indicating the horizontal direction, and the upper 8 bits are referred to as a V address indicating the vertical direction. It is assumed that writing is performed on the memory with VD as a start timing, that is, with the address set to 0.

Next, returning to FIG. 1, reading from the field memory 4 will be described. The enlargement process is performed at the time of reading, as described in the conventional example. Reading is performed in accordance with the read address generated by the read address circuit 10 and the CLK. CL is applied to the read address circuit 10.
In addition to K, HD, VD ', a control signal CON indicating the presence or absence of enlargement processing
T and a PRESET value indicating a read start position are input. These signals are output to the microcomputer 35 as shown in the figure.
It is generated from such as. First, when performing enlargement, for example, if the enlargement location is the upper right part of the screen, the address of the memory corresponding to that location is
Is input as a PRESET value from the result of the calculation, and reading is started while performing interpolation by reading data twice, for example. At this time, the read start timing is determined by the vertical synchronizing signal in the same manner as at the time of writing. Here, the vertical synchronizing signal VD 'delayed by approximately 1/2 field by the delay circuit 11 is supplied to the read address circuit 10. You are typing. As a result, the read field timing is shifted from that of the write by approximately 1/2 field time. Therefore, as described above, regardless of which part of the memory is read, the time relationship between the write and the read is reduced. Will not be reversed. The signal read from the memory is then
The A-converter 5 converts the video signal into an analog video signal again and outputs the enlarged video signal from the output terminal 6. When the enlargement is not performed, the reading is stopped twice according to the content of the CONT signal, and the PRESET value is set to 0 at the start address of the field memory 4.
Address.

Next, the write address generation circuit 9, the read address generation circuit 10, and the delay circuit 11 will be described in more detail with reference to FIGS.

FIG. 2 is an example showing the write address generation circuit 9 and its periphery. Here, the write address generation circuit 9 is an 8-bit counter for generating a V address.
92 (hereinafter referred to as a V counter 92), a 10-bit counter 94 (hereinafter referred to as an H counter 94) for generating an H address, and a V for generating a reset signal VRES for clearing both counters at the period of the vertical synchronization signal VD. A reset circuit 91;
An H reset circuit 93 for generating a reset signal HRES for clearing the H counter 94 in the cycle of the horizontal synchronizing signal HD and VRES
And an OR circuit 95 which takes a logical sum of the HRES and HRES and sends it to the H counter 94.

The write address is generated as follows. First VR
After both counters are cleared by ES, the H counter 94
Starts counting from 0 at CLK. At the end of one horizontal period (hereinafter referred to as 1H) (the fact that the counter value indicates "910" at this time is as described in FIG. 6), a clear signal is input from HRES. , The counter value becomes 0 again and returns to the top of the line. At the same time, the horizontal synchronizing signal HD is input to the V counter 92 as a clock, and one line is counted, and the process proceeds to the next line.
In this manner, this operation is repeated until the next VRES is input to both counters, and the signal is stored in the memory 4 for one field in the form shown in FIG.

FIG. 3 is an example showing the read address generation circuit 10 and its periphery. Here, the read address generation circuit 10 is an 8-bit counter 10 for generating a V address.
2 (hereinafter referred to as a V counter 102) and a 10-bit counter 104 for generating an H address (hereinafter referred to as an H counter 104).
V) that generates a preset signal VPRS that presets both counters to a certain value in the cycle of the vertical synchronization signal VD.
A preset circuit 101 and a preset signal HPRS for presetting the H counter 104 to a certain value in the cycle of the horizontal synchronization signal HD.
And an OR circuit 105 which takes the logical sum of VPRS and HPRS and sends it to an H counter 104. Both counters are provided with a preset value PRESET which is a read start address and a control signal for enlargement. A certain CONT is given from the microcomputer 35. Further, a 1/2 frequency dividing circuit 106 for further enlargement is provided. Reference numeral 11 denotes the delay circuit shown in FIG. The 1/2 frequency divider 106 and the delay circuit 11 will be described later. The read address at the time of enlargement is generated as follows. First, both counters are preset by VRES, and PRESET values are loaded into both counters. Thereafter, the H counter 104 starts counting from the PERSET value with CLK. At this time, a signal 4FSC having the same cycle as that of writing is input to the memory as CLK, but a signal obtained by dividing the frequency by 1/2 with the CONT signal, that is, a signal having a cycle of 2FSC, is input to the H counter as a clock signal of the counter. .
Therefore, the horizontal address is the clock 2 to the memory.
Therefore, the same signal is output twice from the memory in the horizontal direction. When the 1H time has elapsed (the counter value at this time is the PRESET value "+455"
The preset value is input from the HPRS, and the counter value becomes the PRESET value in one line again. On the other hand, since a signal obtained by dividing the horizontal synchronizing signal HD by 1/2 is input to the V counter 102 as a clock, the counter value in the vertical direction also increases by one line for two lines. Therefore, data is read twice in the vertical direction, so that enlargement is performed. Here, the timing for performing counter presetting in the vertical cycle is generated by the vertical synchronization signal VD ′ delayed by approximately 1/2 field time in the delay circuit 11, so that the timing to start reading is approximately 1 / As described above, there is no time lag between two fields and the time relationship between writing and reading does not reverse. By repeating this operation until the next VPRS is input to both counters as described above, a signal doubled is read from the memory 4.

Next, in FIG. 4, a 1/2 frequency dividing circuit 8 for performing enlargement is used.
6 will be described. Reference numeral 861 denotes a flip-flop circuit which forms a frequency divider. Reference numeral 862 denotes a switch that is switched by the control signal CONT. CLK (or H
D) One of the signals is input to the input terminal 862a of the switch 862, and the other is 1/2 frequency-divided by the flip-flop 861,
The signal is input to the other input terminal 862b of the switch 862.
When not expanding, switch 862 is connected to terminals 862a and 862
c is conducting, and CLK (or HD) is output as it is. For expansion, switch 862 is connected to terminals 862b and 862
c conducts, and the divided CLK (or HD) is output. In this way, a counter clock signal for enlargement can be generated.

Next, the delay circuit 11 will be described with reference to FIG. 111,
Reference numeral 112 denotes a 4-bit counter, and both counters form an 8-bit counter. An HD clock and a VD are input to this counter as a clear signal. The counter value is cleared at the VD timing, and the number of HDs is counted. The counter output is input as it is or to the AND circuit 114 through the NOT circuit 113. In this embodiment, when 131 HDs, which are approximately 1/2 field time, are counted, a high level is output and set to VD '. . With such a configuration, approximately 1/2 of VD
A VD 'signal delayed by a field time can be obtained.

Next, as second, third, and fourth embodiments,
An effective enlargement method for an untrimmed video signal of video software will be described. Note that the effective range of these embodiments is not limited to the one-field memory capacity particularly as in the first embodiment. Although there is no particular limitation on the enlargement method, the following description will be given based on the first embodiment.

First, a second embodiment of the present invention will be described with reference to FIGS. In the present embodiment, in order to perform trimming by enlargement, a video signal portion is detected so that the magnification can be automatically calculated.

FIG. 7 is a configuration diagram showing the detection circuit and its periphery. FIG. 8 shows the signals of the respective parts in FIG. 7, and the symbols in both figures are shown in correspondence. Here, the field memory 4 and the write address generation circuit 9 perform the same operations as those described in the first embodiment. First, the reproduced video signal that has passed through the fsc trap circuit 12 that removes the color subcarrier signal and the clamp circuit 13 that reproduces the DC component is input to the voltage comparison circuit 14. The fsc trap circuit 12 is provided in order to eliminate a malfunction caused by the color burst signal of the black burst signal in the voltage comparison circuit 14 at the subsequent stage. Therefore, a gate circuit that removes only the color burst signal may be used instead of the trap circuit. The comparison voltage VR is input to the other terminal of the voltage comparison circuit 14. This voltage VR is, as shown in FIG.
The level is set slightly higher than the black level of the playback video signal. Thus, it is detected whether or not the video signal is at the black level. The voltage comparison circuit 14 detects a signal portion existing at the center of the screen and outputs a high level. Thereafter, the output signal is input to a retriggerable monomultivibrator (hereinafter, referred to as MMV) 15. MMV15 is set to be in the high level state for about 2H after the rising input. Therefore, a high level is continuously output during a period in which a signal is present, and a signal having a high level in a range in which a video signal is present is obtained as shown in FIG. Thereafter, this output is input to the AND circuit 17. On the other hand, VD indicating the vertical synchronization timing is input to the clock input terminals of the gate generation circuit 16 and the latch circuit 19. As shown in FIG. 8 c), the gate generation circuit 16 generates a gate signal which is at a high level only for a period corresponding to the screen display range from the number of HDs with VD as a reference timing. For example, as shown in FIG. 8a), when the reproduced video signal is obtained from a video disc, an erroneous detection caused by a code signal superimposed and recorded in a vertical blanking period can be performed. This is to remove erroneous detection caused by noise caused by dropout or the like by the gate signal. This gate signal is also input to the AND circuit 17. This gives A
From the ND circuit 17, an AND output d) in which only the portion where the video signal exists is at a high level is obtained. Thereafter, the output d) is input to the latch circuit 19. Here the latch circuit
19, NOT circuit 18, AND circuits 20, 21 and OR circuit 22
An edge detection circuit for detecting the rise and fall of the output d), that is, the edge, is configured. With this circuit, as shown in FIG. 8 (e), a data timing signal is obtained such that only the start and end portions of the image area are at the high level for 1H. This signal e) is one of the microcomputer 35
And the other is sent to the switch circuit 23. Switch circuit 23
Is a V address of the write address, that is, data indicating the number of lines. This switch circuit
23 is controlled at the data timing e), and the V address indicating the start and end lines of the image area is stored in the microcomputer 35.
Send to The microcomputer 35 obtains the timing with the VD and the data timing e), takes in the data, and knows the image existence area. Thereafter, an appropriate enlargement magnification reading start address can be easily obtained by arithmetic processing in the microcomputer 35.

By the way, among video software packages that have not been trimmed in recent years, particularly for Western movies and the like, as shown in FIG. 11, a Japanese translation is displayed in a black screen area instead of an image area on the screen. When the above processing is performed on such video software, the edge E, F generated by a character as shown in FIG. May be detected and a malfunction may occur. For this problem,
Since the positions of E and F change due to the change of characters, detection is performed over several fields, and the majority value, average value, and only the first two values after VD timing are obtained. The problem can be solved by making the value valid, processing the value by the microcomputer 35 so as not to easily change the value once determined, and performing an operation. Here, it goes without saying that the image existence position detection circuit described in FIG. 7 can be realized in a purely digital system by using a digital filter, a digital comparator, and the like.

Next, a third embodiment will be described with reference to FIGS. This embodiment is particularly effective for displaying the above-described characters in a black screen area. If the processing of the above embodiment is performed for a case where the character is in the black screen area, the character will not be displayed on the screen due to the enlargement. Therefore, in the present embodiment, as shown by the arrow in FIG. 11, the black screen area on which characters are displayed is displayed as it is without performing enlargement, thereby performing appropriate enlargement processing without missing characters. It is to try.

In order to perform the above operation, it is first necessary to determine whether or not there is a character in the black screen area. Although it is conceivable that the user makes the determination and sets the presence / absence of a character using a switch or the like, it is desirable that the system can automatically determine the presence or absence of the character. FIG. 9 is a block diagram of a character detection circuit for that purpose. FIG. 12 shows the signal timings in FIGS. 9 and 11. Hereinafter, FIG. 9 will be described.

In FIG. 9, signals b, c, and d are the same signals as those in FIG. 7 described in the second embodiment. First, the input gate output d is inverted by the NOT circuit 24 and input to the MMV 25. By doing so, the output of MMV25 is
It goes high at the timing of line C shown in the figure.
From the timing, the MMV 25 is set in advance so as to maintain the high level for a sufficient time (for example, 1/2 field time) to include the time when the video signal is not present (that is, the timing of the line D), and then to the low level. ing. A gate signal c is added to the MMV 25 as a clear signal. Since the gate signal c becomes low level at the timing of the line D as shown in FIG.
The MMV 25 is cleared at that timing. Therefore, the output from the MMV 25 becomes a signal that goes high at the timing of the line C and goes low at the timing of the line D. This is a signal indicating the black screen area at the bottom of the screen as shown in FIG. 12g). This character gate g
Are input to the AND circuit 26 together with the MMV output b. Therefore, if there is a character in the black screen area in the output of this AND circuit 26,
A pulse signal having a certain width according to the character is obtained.
Thereafter, this signal is input as a clock signal of the latch circuit 27. A high level is always applied to the latch circuit 27 as input data. Here, the latch circuit 27 is set to a low level in advance by a reset signal generated from a microcomputer or the like each time image reproduction is started (that is, each time reproduction of a disk or tape is started). Therefore, if there are no characters in the black screen area,
Since nothing is output from the AND 26, the output from the latch circuit 27, that is, the character detection signal remains at the low level, but once a character is detected, the rising of the character signal h catches the high level, and the latch circuit 27 outputs Outputs a high-level signal and confirms that there is a character.

When it is determined that there is a character, a control signal is provided so that only the black screen area at the bottom of the screen is not enlarged during reading.
Form CONT. Since the line starting from the black screen area at the bottom of the screen is the line C obtained at the time of writing, V
The address is always checked, and when the value becomes the same as that of the line C, CONT may be set to indicate the non-expanded state.
There is a method in which the microcomputer 35 checks the V address, but the load on the microcomputer 35 increases. Therefore, it is conceivable to create a control signal by a method as shown in FIG. In FIG. 12, a field memory 4 and a read address generating circuit 10 are the same as those shown in the prior art. In the figure, 28 is a data comparison circuit, 29
Is an AND circuit. The V address of the read address, that is, the address data indicating the number of lines, is always input to the comparison circuit 28. On the other hand, the value of the line C indicating the start of the black screen area is detected from the microcomputer 35 to detect the line C. Is determined and input at the time of writing to the memory.
The data of the line D indicating the bottom of the screen is also set in advance, and the comparison circuit 28 can obtain the timing of the period corresponding to the black screen area, that is, the period during which no enlargement is performed, by comparing these data. . This timing and the control signal for performing the above-described enlargement
From the CONT, the timing is re-established by the AND circuit 29, and the obtained signal is input to the read address generation circuit 10 as the control signal CONT2 for the present embodiment and is controlled. By using the method described above, when there is a character in the black screen area, the enlarged image that has been trimmed is displayed at the upper part of the screen, and the character is displayed at the lower part of the screen as before.
Video software can be enjoyed without loss of characters due to enlargement.

Next, as a fourth embodiment, an example will be described in which a more appropriate enlarged image can be provided for an image that has not been trimmed. In the above embodiment, since the lower part of the screen is not enlarged, there is a problem that the display area of the television screen cannot be used effectively. The present embodiment provides a means for solving this problem.

FIG. 13 is a configuration diagram of the fourth embodiment. This figure is
FIG. 1 shows the processing after the A / D converter in FIG. 1, where the A / D converter 3, the memory 4, the D / A converter 5, the microcomputer
35 is the same as that described in the first embodiment, and also includes a write address generation circuit 9, a read address generation circuit 10, a switch 2
3. The image position detection circuit 29 performs the same operation as that described in the second embodiment, and the character detection circuit 30 performs the same operation as that described in the third embodiment. Also, as in FIG.
It is assumed that D, VD ', HD signals and the like are supplied to each block. Hereinafter, the operation will be described. The video signal output from the TBC is digitally converted in the same manner as in the related art, and stored in the memory 4. At this time, as in the second embodiment, the position of the image is detected by the image position detection circuit 29 and the switch 23. At the same time, the character detection circuit 30 generates a character gate signal g indicating the black screen area. In this embodiment, the character gate signal g is sent to the AND circuit 32. on the other hand,
The video signal is input to a character extraction (character extraction) circuit 31. Normally, the characters superimposed on the black screen area are white. Therefore, characters in the black screen area can be extracted by means similar to the image detection method described in the second embodiment. Thereafter, the extracted characters are stored in the character memory 33. Since the lower half of the screen is stored in the memory 33 for a reason to be described later, not only characters but also an image portion may be stored as it is. The output of the character extraction circuit 31 is
And only the characters are stored in the memory 33 by the character gate signal g indicating the character portion. This memory 33
The characters are stored by the character address signal generated and input by the write address generation circuit 9. If the number of lines to be stored here is, for example, the case where the black screen area is the largest, and the case where a theater movie of 70 mm film is packaged in a video software is considered as an example,
Since the height x width = 1: 2.2, the black screen area on the TV screen is about 100 lines. Therefore, it is sufficient to store about 100 lines in the memory 33. Therefore, in this embodiment, 128 lines, that is, the lower half of the screen are stored in order to facilitate the setting of the memory address as described later. At this time, the capacity of the memory 33 is set to 128 lines × 910 samples ×
It is sufficient that 1 bit = 116480 bits. Further, since 128 lines are designated for the character address signal, the lower 7 bits of the V address sent to the memory 4 may be used for the V address. Further, by enabling the 8th bit of the V address to write-enable the memory, it is easy to store only the lower half of the screen. Next, reading is performed as follows. Reading from the memory 4 is the same as the method read in the second embodiment. Therefore, the video signal read out and converted into an analog signal by the D / A converter 5 is a signal that is subjected to trimming and displays a picture over the entire screen,
The character does not exist. On the other hand, from the character memory 33,
Character reading is performed in synchronization with the reading of the memory 4. This synchronization can be easily realized by counting VD, HD, and CLK inputted to the read address generation circuit 10 by a counter and specifying the same address at the time of writing. In this manner, in synchronization with the timing corresponding to the lower half of the screen of the image read from the memory 4 and enlarged,
Reads characters from memory 33. Thereafter, this character is sent to the mix circuit 34. The mix circuit 34 multiplexes the characters on the enlarged image and outputs a signal from the output terminal 6. Therefore, on the enlarged screen, characters are multiplexed at the same position as in the state where trimming is not performed. By performing the above-described enlargement processing, the television screen can be effectively used and characters can be prevented from being lost due to the enlargement. In the read address generation circuit 10, the address value sent to the character memory 33 can be changed, the multiplex position of the character can be changed, and a control signal indicating the presence or absence of the mix can be input to the mix circuit 34, If necessary, characters may be multiplexed.

[Effects of the Invention] As described above, according to the present invention, the reversal of the time relationship due to the reading at the time of enlargement is eliminated, so that even in the current special display system having the image memory having the capacity of one field, the memory capacity can be reduced. Can be enlarged without increasing the number of images. Also, by detecting the black part in the displayed image, the trimming by enlargement can be automatically performed, so that the user can easily enjoy the trimmed image on the untrimmed video software. Becomes

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a first embodiment of the present invention, FIG. 2 is a configuration diagram around a write address generation circuit in FIG. 1,
FIG. 3 is a block diagram showing the periphery of the read address generation circuit in FIG. 1, FIG. 4 is a circuit diagram of a 1/2 frequency divider circuit in FIG. 1, FIG. 5 is a circuit diagram of a delay circuit in FIG. 6 is an explanatory diagram of an example of storing image data in a memory, FIG. 7 is a configuration diagram of an image position detecting circuit in the second embodiment, and FIG. 8 is a signal timing of each unit in FIG. FIG. 9 is a block diagram of a character detection circuit according to the third embodiment.
FIG. 10 is an explanatory diagram showing generation of an enlargement control signal in the third embodiment, FIG. 11 is an explanatory diagram showing a screen for explaining the third and fourth embodiments, FIG. 12 is FIG. FIG. 13 is a timing chart of signals corresponding to the screen in FIG. 11, FIG. 13 is a circuit configuration diagram of the fourth embodiment, and FIGS. FIG. Explanation of reference numerals 4 ... Field memory, 8 ... VD separation circuit, 9 ... Write address generation circuit, 10 ... Read address generation circuit, 11 ... Delay circuit, 23 ... Switch circuit, 29 ... Image position detection Circuit, 30 ... character detection circuit, 28 ... comparison circuit,
31 ... Character extraction circuit, 32 ... Character memory, 34 ...
Mix circuit.

Continued on the front page (51) Int.Cl. ⁶ Identification number Reference number in the agency FI Technical display location H04N 5/278 H04N 5/278 5/46 5/46

Claims (6)

(57) [Claims] An image magnifying device which writes a digital video signal into a memory for one field and reads out a part of the image written in the memory over one field period to enlarge the image at a magnification of 2 times or less. A display method, wherein the writing and reading are continued in a state where the writing field start timing and the reading start timing are shifted by about 1/2 field time. 2. A memory for storing a digital video signal for one field, writing means for writing the digital video signal to the memory, and reading means for reading the digital video signal from the memory, wherein the reading means reads the digital video signal from the memory. An image enlargement display device for enlarging an image at a magnification of 2 times or less by reading a part over one field period, wherein the write field start timing and the read start timing are set to approximately 1/2 field time An enlarged image display device, comprising a shift unit. 3. A memory for storing a digital video signal for one field, writing means for writing the digital video signal in the memory, and reading means for reading the digital video signal from the memory. An image enlargement display device in which an image is enlarged at a magnification of 2 times or less by reading a part over one field period, and when writing of the digital video signal for approximately 1/2 field to the memory is completed. And means for setting timing so that the read memory address moves from the end point of one field to the start point. 4. A memory for storing a digital video signal for one field, writing means for writing the digital video signal in the memory, and reading means for reading the digital video signal from the memory, wherein the reading means reads the digital video signal. An image enlargement display device for enlarging an image at a magnification of 2 or less by reading a part over one field period, and at the time when read data corresponding to approximately 1/2 field is read from the memory, An enlarged image display device comprising: means for setting timing so that a write memory address moves from an end point of one field to a start point. 5. A first memory for storing a digital video signal, writing means for writing the digital video signal to the first memory, and reading means for reading the digital video signal from the memory, An image enlargement display device for enlarging an image by reading a part of the image over one field period by a dipping means, wherein a region or an image where an image in the signal is present for a video signal which has not been trimmed Black screen detecting means for detecting a black screen area where no black screen area exists, enlargement rate obtaining means for obtaining an image enlargement rate based on information obtained by the black screen detecting means, and determining the presence or absence of characters in the black screen area. A character detection unit that detects and generates a detection signal; and an image based on the enlargement ratio obtained by the enlargement ratio acquisition unit so as to delete the black screen area. Enlargement means for enlarging an image, wherein in response to the detection signal being given, in response to the detection signal, only the black screen area where the character is present is displayed in the original size without being enlarged. An enlarged image display device, comprising: a configured enlargement unit. 6. A first memory for storing a digital video signal, writing means for writing the digital video signal to the first memory, and reading means for reading a digital video signal from the memory, wherein the reading is performed. An image enlargement display device for enlarging an image by reading a part of the image over one field period by a dipping means, wherein a region or an image where an image in the signal is present for a video signal which has not been trimmed A black screen detecting means for detecting a black screen area where no black screen exists, wherein the black screen detecting means is configured to perform detection over the first plurality of fields and not to perform detection thereafter. Means for obtaining an enlargement rate of an image based on the information obtained by Image enlarging display device being characterized in that a magnifying means for enlarging an image based on the enlargement ratio obtained by the means.