JPH04129439A - Multi-frame synchronization circuit - Google Patents

Abstract

PURPOSE:To make the circuit scale small by applying data speed conversion and phase correction with a single memory. CONSTITUTION:A serial/parallel converter 41 converts a reception data from a multi-frame synchronization detection circuit 32 into a parallel data synchronously with a pulse and gives the result to a dual port RAM 42. Then a write address is generated in response to the system clock and a reception data subject to parallel processing is written in a dual port memory 42 and a data is read from the memory 42 by using a read address generated by the system frame pulse and the system clock. Thus, the speed conversion and the phase correction are attained by the single dual port memory 42. Thus, the circuit scale is made small.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a multi-frame synchronization circuit that converts the speed and corrects the phase of frame data coming in from an external line to form a multi-frame configuration, which requires only one memory and has a small circuit scale. A multi-frame synchronization detection circuit that detects the frame synchronization of received data serially input from the line and generates a multi-frame synchronization pulse, and a system frame pulse that serves as a reference within the equipment. a phase comparison circuit that performs a phase comparison with the multi-frame synchronization pulse to obtain a phase difference; and an address counter that generates a write address in synchronization with a system clock within the device after the phase difference has been determined. , a serial/parallel conversion circuit that converts the received data into parallel data, an address generation circuit that generates a read address based on the system frame pulse and the system clock, and a serial/parallel conversion circuit that converts the received data into parallel data according to the write address from the address counter. It has a dual port memory in which parallel data from the circuit is written and data is read out and output according to the read address from the address generation circuit.

[Industrial application field]

The present invention relates to a multiframe synchronization circuit, and more particularly, to a multiframe synchronization circuit that performs speed conversion and phase correction on frame data coming in from an external line to create a multiframe configuration.

In recent years, with the development of networks, frame data coming from an external line is sometimes treated as a multi-frame structure in order to improve data reliability. In this case, it is necessary to perform speed conversion and phase correction of the data.
There is a demand for reducing the scale of the circuit and lowering the cost.

[Conventional technology]

FIG. 3 shows a block diagram of an example of a conventional circuit.

In the same figure, terminals 10 and 11 are supplied with received data (RData) received from an external line and a clock (RCLK) extracted from the received data, and a multi-frame synchronization detection circuit 12 detects a frame synchronization bit. to generate a multi-frame pulse (MFP). Received data (RData) is sequentially written into a frame aligner (FA) 13, which is a speed conversion RAM, by a clock (RCLK).

A pulse generator (PC) 14 generates a system clock (SYSCLK) and a system frame pulse (S
YSFP) to generate multi-frame addresses and various timing signals.

Data is read from the frame aligner 13 by a read clock from a pulse generator 14, and this data is converted into parallel data by a serial/parallel converter (S/P) 20 and written into a RAM 21 for phase correction.

When a multiframe pulse is supplied from the multiframe synchronization detection circuit 12, the address phase conversion circuit 22 holds the frame number represented by the upper bits of the multiframe address supplied from the pulse generator 14 as a phase difference, and An address obtained by subtracting the phase difference from the address number of the address is supplied to the selector (SEL) 23 as a write address. Selector 23
switches the write address and the multi-frame address supplied as a read address from the pulse generator 14 according to the control pulse from the pulse generator 14 and supplies it to the RAM 21, and the RAM 21 receives the write/successive pulse from the pulse generator 14. Parallel data from the S/P 20 is written to the address supplied by the selector 23 in response to this, and the data is successively output. This read data is latched by the latch circuit 24 and supplied from the terminal 25 to the next stage circuit in the device.

In other words, the frame aligner 13 converts the speed of data received from the line to the speed within the device, and the RA
At M21, phase correction is performed to match the phase of the received data frame with the phase of the multiframe within the device.

[Problem to be solved by the invention]

The conventional circuit requires two RAMs, the frame aligner 13 which is a RAM for variation conversion, and the RAM 21 for phase correction.Especially when the size of multi-frames in the device is large, each of the above two RAMs is large. There was a problem of increasing the circuit scale and increasing the size of the circuit.

The present invention has been made in view of the above points, and an object of the present invention is to provide a multi-frame synchronization circuit that requires only one memory and can be downsized in circuit scale.

[Means to solve the problem]

The multi-frame synchronization circuit of the present invention includes a multi-frame synchronization detection circuit that detects frame synchronization of received data serially input from a line and generates a multi-frame synchronization pulse, and a multi-frame synchronization detection circuit that detects frame synchronization of received data serially input from a line, and a A phase comparison circuit that compares the phase with the frame synchronization pulse to obtain the phase difference; an address counter that generates a write address in synchronization with the system clock in the device after the phase difference is set; and a phase comparison circuit that converts the received data into parallel data. a serial/parallel conversion circuit that converts the data into a serial/parallel conversion circuit; an address generation circuit that generates a read address based on the system frame pulse and the system clock; and an address generation circuit that writes parallel data from the serial/parallel conversion circuit according to the write address from the address counter.
It has a dual port memory that reads and outputs data according to a read address from an address generation circuit.

[Effect]

In the present invention, the phase difference between the multi-frame synchronization pulse detected and generated from the received data and the system frame pulse is set, and a write address is generated according to the system clock, and the parallelized received data is transferred to the dual port memory. Since data is written to the memory and read from the memory using a read address generated from the system frame pulse and system clock, speed conversion and phase correction can be performed using a single dual-port memory, reducing the number of memories compared to conventional memory. This decreases the number of circuits and enables miniaturization of the circuit scale.

〔Example〕

FIG. 1 shows a circuit diagram of one embodiment of the circuit of the present invention.

In the figure, received data (R, data) is input to the terminal 30, and the terminal 31 receives the data extracted from the received data (A).
) is input. The multi-frame synchronization detection circuit 32 detects a frame synchronization bit in the received data in synchronization with the clock, generates a multi-frame pulse (MFP) shown in FIG. 2(B), and supplies it to the phase comparison circuit 35.

Further, each of the terminals 33 and 34 is shown in FIG. 2(I).

System clock (SYSCLK) shown in (C).

Each system frame pulse (SYSFP) enters and is supplied to the phase comparison circuit 35, and the phase comparison circuit 35
As shown in Figure (D), the received data (RData) at the time of multi-frame pulse (MFP) input is set as an O frame, and the tarock (RCLK) is counted, and the system frame pulse (SYSFP) shown in Figure 2 (E) is started. The above count value (MAO to MA3) at the time of rising is sent to address counter 4.
Supply to ゜. Also, the system clock (SYSCLK)
From this, a pulse (S/PCL) for serial/parallel conversion shown in FIG. 2(F) is generated and supplied to the address counter 40 and the serial/parallel converter (S/P) 41, respectively.

The serial/parallel converter 41 converts the received data (Rdata) from the multi-frame synchronization detection circuit 32 into pulses (
S/PCL) and convert it to parallel data and input it to the data input terminals DIO to DI7 of the dual port RMA42.
supply to.

The address counter 40 has a count value (MAO to MA3.
) with the frame number specified as the initial value and tepulse (S
/PCL) is incremented, and when this frame number or the number of multiframe frames is reached, the frame number is returned to 0, and the frame number is included as the upper bit as shown in Figure 2 (G). The write address is generated and supplied to the write address input terminals ALO to ALN of the RAM 42. Further, the RAM 42 is supplied with a write enable W and a chip select 1 shown in FIG. 2(H) which are synchronized with the pulse (S/PCK) from the phase comparison circuit 35.

As a result, data is written into the RAM 42 in accordance with the line speed.

In addition, a pulse generator (
PG) 43 is the frame number shown in Fig. 2 (J) that counts the system clock when the system clock (SYSCL) rises at the input of the system frame pulse (SYSFP) with the frame number being 0 as the upper bit. An address is generated and supplied to the read address input terminals ARO to ARN of the RAM 42, and π is generated by the output enable JT and chip select shown in FIG. 2 (K) synchronized with the system clock, respectively.
Supply to AM42. As a result, the data output terminal of the RAM 42 outputs the output data (TDa
t a) is successively outputted at the internal speed of the device, and is supplied from the terminal 45 to the next stage circuit in the device.

In the example of FIG. 3, immediately after the rising edge of the system frame pulse, parallel data is written to the dual port RAM 42 with frame number "5", and
42 is the frame number after the input of the system frame pulse.
0'' is read out in this order to perform phase correction.

In this way, the phase difference between the multi-frame synchronization pulse detected and generated from the received data and the system frame pulse is set, the write address is generated according to the system clock, and the parallelized received data is transferred to the dual-port RAM 42. Since data is written to and read from the RAM 42 using a read address generated from the system frame pulse and the system clock, speed conversion and phase correction can be performed using a single dual port RAM 42, which reduces the number of memories compared to the conventional one. This makes it possible to reduce the size of the circuit.

[Effects of the Invention] As described above, according to the multi-frame synchronization circuit of the present invention, data speed conversion and phase correction can be performed with a single memory, making it possible to downsize the circuit scale, which is extremely practical in practice. Useful.

4,

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the circuit of the present invention, FIG. 2 is a signal timing chart of the circuit of the present invention, and FIG. 3 is a block diagram of an example of a conventional circuit. In the figure, 32 is a multi-frame synchronization detection circuit, 35 is a phase comparison circuit, 40 is an address counter, 41 is a serial/parallel converter, and 42 is a dual port RAM. 43 indicates a pulse generator.

Claims (1)

[Claims] A multi-frame synchronization detection circuit (32) that detects frame synchronization of received data serially input from a line and generates a multi-frame synchronization pulse; A phase comparison circuit (35) that performs phase comparison with the multi-frame synchronization pulse to obtain a phase difference; and an address counter (35) that generates a write address in synchronization with the system clock within the device after the phase difference is set. 40), a serial/parallel conversion circuit (41) that converts the received data into parallel data, an address generation circuit (43) that generates a read address based on the system frame pulse and the system clock, and the address counter (40); A dual-port memory (42) writes parallel data from the serial/parallel conversion circuit (41) according to a write address from 40), and reads and outputs data according to a read address from the address generation circuit (43). A multi-frame synchronization circuit characterized by: