JPH0863387A - Device for reading out memory - Google Patents

Abstract

PURPOSE: To read out consecutive memories in synchronism with a clock in the minimum read cycle time tRCmin . CONSTITUTION: The device consists of an address controller 1 which outputs an address ADR in synchronism with a clock CLK, memory 2 which inputs an address ADR from an address controller 1 and outputs data (1) stored in advance, the 1st register 3 which takes in data (1) from the memory 2 in synchronism with a delay clock DLY at the output, the 2nd register 4 which outputs data (2) in synchronism with a clock CLK, and delay circuit 5 which outputs a delay clock DLY with it delayed by the delay time T. Thus, when the memory 2 outputs the data (1) and holds it by the output holding time tOH, the data (1) is sample-and-holding by the register 3 in the tOH period. The 2nd register 4 samples the data (2) and outputs data (3).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory reading device capable of continuously reading from a memory in synchronization with a clock even in the minimum read cycle time of the memory.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of a conventional system. An address controller 1 that operates in synchronization with a clock CLK and outputs an address ADR;
The memory 2 which receives the address ADR from the memory 2 and outputs the data stored in advance, and the register 6 which outputs the data from the memory 2 as fetched data in synchronization with the clock CLK.

This operation will be described with reference to FIG. FIG. 4 is a time chart diagram of the prior art. (1) Normal case,
(2) The case where the read cycle is advanced is described. (1) In the normal case, the read cycle t of the memory 2
_{When RC} is larger than the minimum read cycle time t _RCmin (t _RC > t _RCmin ) and (2) the read cycle is advanced, the read cycle t _RC of the memory 2 is equal to the minimum read cycle time t _RCmin (t _RC = t _RCmin ). In the figure, the shaded area represents the output indefinite state.

First, (1) Normal case (t _RC > t _RCmin )
I will describe. The address controller 1 outputs the address (h) delayed by the delay time t _{d with} respect to the clock input (g). As shown in (i), the memory 2 outputs stable data after the elapse of the address access time t _AA, which is the maximum time during which the output is stable against changes in the address (h), and outputs the data stored in advance. , The output is held for the output hold time t _OH after the next address (h) change. The output data is sampled by the clock (g) in the register 6 and output as data, so that the data can be continuously read in synchronization with the clock.

Next, (2) the case where the read cycle is advanced (t _RC = t _RCmin ) will be described. The address controller 1 outputs the address (1) delayed by the delay time t _{d with} respect to the clock input (k). As shown in (m), the memory 2 outputs stable data after the address access time t _AA for the change of the address (l), outputs the data stored in advance, and changes the next address (l). The output is held for the post output holding time t _OH . However, the minimum read cycle time t _RCmin and the address access time t _{AA of} the memory 2 are the same in a commercially available memory, and are further delayed by the delay time t _{d with respect} to the clock (k). The output indefinite state is sampled at the minimum read cycle time t.
_{In RCmin} , it is impossible to read continuously in synchronization with the clock.

[0006]

As described above, in the conventional technique, in the normal case (t _RC > t _RCmin ), continuous reading can be performed in synchronization with the clock, but the read cycle is advanced to the minimum read cycle time t _RCmin. If (t _RC
= T _RCmin ), continuous reading cannot be performed in synchronization with the clock.

The object of the present invention is to solve the problems of the prior art, and to _{achieve the} minimum read cycle time t _RCmin ,
An object of the present invention is to provide a memory reading device that enables continuous reading in synchronization with a clock.

[0008]

An object of the invention is to provide an address controller which operates in synchronism with a clock and outputs an address, and a memory which receives an address from the address controller and outputs prestored data.
A delay circuit that outputs a delayed clock obtained by delaying the clock by a certain delay time, a first register that captures and outputs data from the memory in synchronization with the delay clock of the delay circuit described below, and the first register A second register for taking in and outputting the data from the device in synchronization with the clock, and a delay circuit for adjusting the delay time of the clock to the period of the output holding time of the memory and outputting the delayed clock. This is achieved by making it possible to perform continuous reading in synchronization with the clock even in the cycle of the read cycle time.

[0009]

According to the above means, the address controller outputs the address delayed by the delay time t _d with respect to the clock input. The output of the memory is stable after the elapse of the address access time t _AA, which is the maximum time for the output to stabilize with respect to the address change, and the previously stored data is output, and the output hold time t _OH after the next address change. Hold output only. The output data is sampled by the delayed clock obtained by delaying the clock by the delay time T in the first register and output as data. The data is sampled by the clock in the second register and output as data. By adjusting the timing of the delayed clock during the memory output holding time t _OH ,
Data can be sampled and output, and data can be output.

[0010]

EXAMPLES The present invention will be described below with reference to examples. FIG. 1 is a block diagram of an embodiment of the present invention. An address controller 1 that operates in synchronization with a clock CLK and outputs an address ADR, and an address AD from the address controller 1 are shown.
The memory 2 which inputs R and outputs the data stored in advance, and the data from the memory 2 are delayed clock D
A first register 3 that captures and outputs data as data in synchronization with LY, a second register 4 that captures and outputs data as data that is synchronized with clock CLK, and a delay obtained by delaying clock CLK by delay time T. The delay circuit 5 outputs the clock DLY.

FIG. 2 is a time chart for explaining the operation of this embodiment. In the figure, the shaded area represents the output indefinite state. The address controller 1 outputs the address (b) delayed by the delay time t _{d with} respect to the clock input (a). As shown in (c) of the memory 2, the output is stable after the elapse of the address access time t _AA, which is the maximum time for the output to stabilize with respect to the change of the address (b), and the data stored in advance is output. ,And,
The output is held for the output hold time t _OH after the next address (b) change. The output data is sampled by the delayed clock (d) by delaying the clock (a) by the delay time T in the first register and output as data (e). The data is sampled by the second register 4 at the clock (a) and output as data (f). The delay circuit 5 delays the clock (a) by the delay time T to generate the delay clock (d). The delay time T is set so that the delay clock (d) is generated during the output holding time t _OH of the memory 2. It is possible to continuously read and operate in synchronization with the clock with the minimum read cycle time t _RCmin by adjusting the.

[0012]

As described above, according to the present invention, there is an effect that continuous memory reading can be surely performed in synchronization with the clock even at the minimum read cycle time t _RCmin .

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a time chart diagram of an example of the present invention.

FIG. 3 is a configuration diagram of a conventional example.

FIG. 4 is a time chart diagram of a conventional example.

[Explanation of symbols]

1 ... Address controller, 2 ... Memory, 3 ... First register, 4 ... Second register, 5 ... Delay circuit.

Claims (1)

[Claims] 1. An address controller which reads data from a memory in synchronization with a clock and which operates in synchronization with the clock and outputs an address, and an address from the address controller which is input and outputs previously stored data. Memory, a first register for fetching and outputting data from the memory in synchronization with a delay clock of the delay circuit described below, and a second register for fetching and outputting data from the first register in synchronization with the clock Register and a delay circuit that adjusts the clock delay time to the output hold time of the memory to output the delayed clock, and continuously reads in synchronization with the clock even in the minimum read cycle time of the memory. A memory reading device characterized by being capable of performing.