JP2870287B2 - Integrating circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a time division multiple access (hereinafter, referred to as TDMA) satellite communication system. In particular, it relates to an integrating circuit for high-speed data processing.

[0002]

2. Description of the Related Art In a TDMA satellite communication system, as one method for controlling the transmission level of all slave stations in which a reference station participates in order to compensate for the deterioration of the line quality due to a decrease in power level due to rain attenuation, the reference station transmits data. Transmission level control is performed for the reference station synchronization burst, and the reception levels of the reference station synchronization burst and the slave station burst are measured and compared at substantially the same time to find out the level drop of the slave station and compensate for this. Level control. Here, the level measurement target data present in the slave burst is integrated over a predetermined measurement interval T seconds, an average value of the measurement interval is obtained from the integration result, and this is measured as the reception level of the slave burst. Next, an integrating circuit for obtaining the reception level will be described. As shown in FIG. 4, a conventional integrating circuit includes a frame counter 2 for knowing a burst position in a frame.
1 and an address decoder 22 for generating a pulse at a measurement target burst position obtained from the frame counter 21.
A CPU 24 that performs integration by using the output of the address decoder 22 as an interrupt signal; and an input / output buffer 23 that receives input data 201 input to the integration circuit and passes it to the CPU 24. As shown in FIG. 5, in a situation where I slave stations exist for one reference station, one reference station synchronization burst and I slave station bursts N1 to NI exist in one frame. Since the level measurement is performed in pairs of the base station synchronization burst and the slave station burst, the measurement is performed once in the reference station synchronization burst and once in the slave station burst, and the measurement time is measured for one slave station in order to increase the level measurement accuracy. Level measurement was performed by integrating the measured values over T seconds. Next, the operation of this conventional example will be described. FIG. 4 shows a configuration of a conventional integrating circuit used as such a measuring means. The frame counter 21 determines a burst position on the input data 201 as an address based on the input frame pulse 202 and clock 203 and notifies the decoder 22 of the address. The address decoder 22 decodes the received address to obtain an interrupt signal indicating the burst position to be measured, and outputs the interrupt signal to the CPU 24. Also, the input data 201 is received by the input / output buffer 23 and passed to the CPU 24. The CPU 24 captures input data via the input / output buffer for each interrupt signal. The CPU 24 integrates the bursts to be measured over a measurement section T seconds. CPU
The integration result obtained at 24 is output as the output 204 of the integration circuit. This result is notified to the corresponding slave station via another line, and the slave station performs level control based on the result to achieve the purpose of transmission level control. In the conventional circuit, when the number of participating stations is small, even if sudden rain attenuation occurs, the integration time is short, so that the transmission level control can be executed quickly. Here, (a) of FIG. 5 shows a measurement section for 1 × slave burst having one phase from frame 1 to frame A, and (b)
Indicates a frame format composed of a reference station synchronization burst and a slave station burst.

[0003]

The needs of the TDMA satellite communication system are expanding from a small number of communication systems between large cities to a large number of communication between small and medium-sized local cities.
Indeed, it is growing into a communication system with a relatively large number of participating stations that makes great use of the multiple connectivity of satellite communication.
Under the situation of such a communication system having a large number of participating stations, when a transmission level control method using a conventional integrating circuit is used, if the number of slave stations is I, the control cycle C for one slave station is T × I second. And the transmission level control becomes less effective because it cannot follow a sudden level change due to rainfall.

The present invention eliminates such a drawback and increases the number of bursts measured in one frame from one to J to enable parallel processing in the same measurement section (hereinafter referred to as a phase). An object of the present invention is to provide an integrating circuit having means for shortening a control cycle for a slave station.

[0005]

According to the present invention, there is provided an input terminal for inputting data to be measured contained in a burst of a slave station coming from a slave station, and an output terminal for passing the result of integration of the data to be measured to the slave station. In the integrating circuit provided, a ROM in which a slave burst position, a data position to be measured, and a measurement section are stored in advance, a clock related to the slave burst, and a frame pulse that triggers counting are input, and the clock is counted. A frame counter for generating an address in one frame cycle and outputting it to the ROM, the clock and the super frame pulse which is a trigger for starting counting , and inputting a ripple carrier out signal from the frame counter as an enable signal; This clock is counted, an address is generated in one superframe cycle, and A superframe counter output to OM, integration result of the measured data at the address where the frame counter and the superframe counter is output up to the previous time based on the latch pulse signal and a reset signal read from the ROM is extracted A first flip-flop, an adder that adds the current measurement target data via the input terminal to the integration result of the previous measurement target data extracted from the first flip-flop, the frame counter, Using the output of the superframe counter as an address, the addition result of the adder is stored every time based on the address signal and the write enable signal read from the ROM, and the addition result is supplied to the first flip-flop every time. The integration RAM and the frame counter And the cumulative for RAM in accordance with the output control signal read from the ROM output of the super-frame counter as an address
And a second flip-flop for providing the content stored in the second terminal to the output terminal.

[0006]

The parallel processing of a plurality of bursts is performed by hardware within one measurement section. Thereby, the data processing speed can be increased.

[0007]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of this embodiment, in which an address signal for the integrating RAM 16, a latch pulse signal for the flip-flop 14, a reset signal for the flip-flop 14,
Is a write enable signal for the integrating RAM 16,
Indicates an output pulse signal to the flip-flop 17. FIG. 2 is a diagram showing a measurement principle according to this embodiment. FIG. 2A shows a measurement section for a J × slave burst having 1 to A frames as one phase,
(B) shows a frame format composed of a reference station synchronization burst and a slave station burst, and (c) shows a relationship between a superframe, a phase, and a control cycle. FIG.
Is a timing chart showing the operation of the embodiment.
= 3, J = 2, and T = 3 frames, where 〜 in the figure indicates control signals corresponding to 〜 in FIG. 1, and (a) indicates a reference station synchronization burst. (B) shows a relationship between a superframe, a phase, and a control cycle. As shown in FIG. 1, this embodiment includes a frame counter 11, a superframe counter 12, a ROM 13, a flip-flop 14, an integrating RAM 16, an adder 15, and a flip-flop 1.
7 is provided. That is, in this embodiment, as shown in FIG. 1, the input terminal for inputting the input data 101 which is the data to be measured included in the slave burst coming from the slave and the output data 1 which is the integration result of the data to be measured.
05 is provided with an output terminal for passing to the slave station. Further, as means characterized by the present invention, a ROM 13 in which a slave station burst position, a measurement target data position and a measurement section are stored in advance, and a clock related to the slave station burst 103 and frame pulse 1 that triggers counting
02, the clock 103 is counted, the frame counter 11 for generating an address in one frame cycle and outputting it to the ROM 13, and the clock 103 and the counting start trigger.
Input the super frame pulse 104 to be a machine ,
The clock 103 is counted using the ripple carry-out signal from the frame counter 11 as an enable signal,
An address is generated in one superframe cycle and
A superframe counter 1 2, the integration result of the measured data up to the previous basis of the latch pulse signal and a reset signal read from the ROM13 with the address frame counter 11 and the superframe counter 12 outputs are extracted to output to Flip-flop 14,
The outputs of the adder 15 and the frame counter 11 and the super-frame counter 12 for adding the current measurement target data via the input terminal to the integration result of the previous measurement target data extracted from the flip-flop 14, and The adder 1 based on the address signal and the write enable signal read from the ROM 13.
5 is stored every time and the addition result is given to the first flip-flop 14 each time.
16 and a flip-flop 1 for giving the contents stored in the integrating RAM 16 to the output terminal in accordance with the output control signal read from the ROM 13 using the outputs of the frame counter 11 and the super-frame counter 12 as addresses.
7 is provided.

Next, the operation of this embodiment will be described. The frame counter 11 which operates by the clock 103 input to the integrating circuit and the frame pulse 102 which starts counting starts generates an address in one frame cycle and outputs it to the ROM 13. Also, the super frame counter 12 enables the ripple carry out of the frame counter 11 to enable the super frame pulse 104.
Is generated, and an address is generated in one superframe cycle and output to the ROM 13. ROM 13
The slave station burst position, the measurement target data position, and the measurement section are recognized from this address. ROM using this information
Reference numeral 13 outputs a measurement timing control signal to the flip-flop 14, the integrating RAM 16, and the flip-flop 17 which are provided at the subsequent stage.

Next, the integration operation will be described with reference to FIG.
For example, an N1 burst will be described. The total number of slave stations is I, and the number of parallel processing bursts performed during one phase is J
Number. The ROM 13 stores the address 1 in the N1 burst section.
The address is output to the integrating RAM 16. ROM 13
Outputs a latch pulse to the flip-flop 14 within the section of the address 1, and extracts the integration result of the N1 burst up to the previous frame stored in the integration RAM 16. At this time, in the case of the frame in which the measurement of the N1 burst is started, the ROM 13 resets the flip-flop 14 in the section of the address 1 to set the integration result of the N1 burst up to the previous frame to “0”. As a result, integration is newly started from the current burst. Adder 1
5 always integrates the integration result up to the previous frame input from the flip-flop 14 and the input data 101 and outputs the result to the integration RAM 16. In this adder 15, there is no recognition of the burst position, the position of the data to be measured and the measurement section. The integration result output from the adder 15 is written into the integration RAM 16 by the write control signal (write enable) input from the ROM 13 within the section of the address 1 for the N1 burst.
The loop operation from the adder 15 to the integrating RAM 16 is performed for T seconds, and the ROM 13 outputs an output pulse to the flip-flop 17 within the N1 burst (address 1) section of the measurement end frame. Then, the output data 105 of the integrating circuit is output from the flip-flop 17. Although the above operation has been described focusing on the level measurement operation of the N1 burst, the measurement of J slave bursts is simultaneously performed as shown in FIG. The number of phases and the control cycle C seconds for this number of J are as follows.

When J = 1, measurement of all stations is completed in the first phase. C = T ... Equation When J <1, I ÷ J = K. When remainder: M. When M = 0, measurement of all stations is completed in the first to Kth phases. C = T × K = T × (I / J) formula When M> 0, measurement of all stations is completed in the first to K + 1st phases C = T × (K + 1) = T × {(I / J) +1} formula T: Measurement time per phase The control cycle C is:
In the present invention, it is possible to set I = J,
In this case, the control cycle is T seconds, and the control cycle can be greatly reduced. For example, assuming that the frame length is 20 milliseconds, in the conventional circuit, the CP within one frame length of 20 milliseconds
There will be a limit of two interrupt signals to U. On the other hand, in the present invention, even if there are I = 100 slave bursts in one frame, it is possible to finish integrating these 100 bursts simultaneously within T seconds.

Next, the process of extracting five measurement timing signals from the ROM 13 will be described with reference to FIGS. Of the input addresses D0 to D7 of the ROM 13, D0 to D4 are addresses counted in one frame, and in this embodiment, 32 bits (0
0000-11111). In one frame, the reference station synchronization burst, the N1 burst, the N2 burst, and the N3 burst are each configured by 8 bits. Of the input addresses D0 to D7 of the ROM 13, D5 to D7
D7 is an address counted in one superframe, and "00" of D5 to D7 in the address map table of FIG.
“0” represents the first frame, “001” in FIG. 7 represents the second frame, and similarly “101” in FIG. 11 represents the sixth frame. The input addresses D0 to D of the ROM 13
A change point is provided at a predetermined position in the burst located at 7, and the address signal, the latch pulse signal,
Obtain a reset signal, a write enable signal, and an output pulse signal. For example, the signals that must be output from the ROM 13 in the first super frame, the first phase, and the first frame are the signals shown in FIG. 12, and when this is reflected in FIG. 6, the address signal becomes the reference station synchronization burst “00”. , N1 burst “01”, N2 burst “10”, N3 burst “11”, and the latch pulse signal is all “0” in the base station synchronous burst section.
There is a transition point of “1” in the second address of the N1 burst and N2 burst, and the reset signal is a transition point of “0” in the first address of all “1”, N1 burst, and N2 burst in the base station synchronous burst section. Yes, the write enable signal is “1” for the base station synchronization burst section, N
There is a transition point of “0” at the fourth address of one burst and N2 burst. In this way, by writing data in the ROM 13 in advance, a measurement timing signal can be extracted from the ROM 13.

[0012]

As described above, according to the present invention, the parallel processing of a plurality of bursts is performed in one phase, and the circuit configuration for performing this processing is entirely realized by hardware. The data processing speed can be increased and the processing cycle of transmission level control can be shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a measurement principle according to an embodiment of the present invention.

FIG. 3 is a timing chart showing the operation of the embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional example.

FIG. 5 is a diagram showing a measurement principle according to a conventional example.

FIG. 6 is a diagram showing correspondence between addresses and data of a ROM included in FIG. 1;

FIG. 7 is a diagram showing correspondence between ROM addresses and data included in FIG. 1;

FIG. 8 is a diagram showing correspondence between addresses and data of a ROM included in FIG. 1;

FIG. 9 is a diagram showing correspondence between ROM addresses and data included in FIG. 1;

FIG. 10 is a diagram showing correspondence between ROM addresses and data included in FIG. 1;

FIG. 11 is a diagram showing correspondence between ROM addresses and data included in FIG. 1;

FIG. 12 is a view showing an example of an output of a ROM included in FIG. 1;

[Explanation of symbols]

 Reference Signs List 11 frame counter 12 super frame counter 13 ROM 14 flip-flop 15 adder 16 accumulating RAM 17 flip-flop 21 frame counter 22 address decoder 23 input / output buffer 24 CPU 101 input data 102 frame pulse 103 clock 104 super frame pulse 105 output data 201 Input data 202 Frame pulse 203 Clock 204 Output data

Claims (1)

(57) [Claims] 1. An integrating circuit having an input terminal for inputting data to be measured contained in a slave burst coming from a slave and an output terminal for passing the result of integration of the data to be measured to the slave. A ROM in which the position, the position of the data to be measured and the measurement section are stored in advance, a clock relating to the slave burst and a frame pulse which triggers counting are input, the clock is counted, and an address is generated in one frame cycle. Then, a frame counter to be output to the ROM, the clock and the super-frame pulse which is a trigger of counting start are input, and the clock is counted using the ripple carry-out signal from the frame counter as an enable signal. super off to be output to the ROM and generates an address in the frame period A frame counter, and a first flip-flop from which an integration result of the data to be measured up to the previous time is extracted based on a latch pulse signal and a reset signal read from the ROM at an address output by the frame counter and the super frame counter. And an adder for adding the current measurement target data via the input terminal to the integration result of the previous measurement target data extracted from the first flip-flop, and the frame counter and the super frame counter. An integrating RAM for storing the addition result of the adder every time based on an address signal and a write enable signal read from the ROM using the output as an address, and for giving the addition result to the first flip-flop each time;
And a second flip-flop for giving the content stored in the integrating RAM to the output terminal in response to the output control signal read from the ROM using the outputs of the frame counter and the super frame counter as addresses. An integrating circuit, comprising: