JPS58200673A - Start timing decision circuit - Google Patents

Abstract

PURPOSE:To decide always a stabilized start phase, by generating the 1st and 2nd pulse trains in synchronization with a burst and horizontal synchronizing circuit, respectively, and by generating a pulse train having the fixed width by the pulse trains to extract the only pulse. CONSTITUTION:A 1/4 counter 40 of a timing decision circuit generates the 1st pulse train which is synchronized with a burst signal, and a phase comparator 31, 14MHz OSC 32, 1/910 counter 33 MONOSC oscillator 37, etc., generate the 2nd pulse train in synchronization with a horizontal synchronizing signal. The 1st pulse train latchs the state of the 1st pulse train to a latch circuit 44 and generates the 4th pulse train having a fixed width, in synchronization with the 1st pulse train and having the same frequency as that of a subcarrier, from a data-through and holding circuit 50. The 3rd pulse train which is in synchronization with the 2nd pulse train and has the same frequency as that of the horizontal frequency is generated from a D latch 63, and the pulse train is delayed by clock delay lines 58-59 to select the 4th pulse train by a selector 51.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a start timing determining circuit in a digital counter circuit for generating addresses used in, for example, a frame synchronizer.

In digital equipment that handles television signals, it is necessary to start the counter at a timing synchronized with the television synchronization signal, such as an address counter in a frame synchronizer. In these devices, the counter is operated using a clock pulse locked to the input burst signal (8C), and the start phase of the counter is often based on the Mizuko synchronization signal. The on signal is 5C
Since the phase relationship of -H is arbitrarily set, this start phase is not the only stable one, and an unstable region inevitably occurs.

For example, when specifying the start timing (phase) of a digital counter (hereinafter referred to as the 0th phase), even if the θ address regulation pulse A and the counter black relationship are maintained, each phase relationship is independent. If so, the start phase would have been undefined. An example of this is shown in diagram ta1. In the case of the phase relationship shown in FIG. 1, it is unclear whether the 0th position phase of the counter output is the phase shown by C or a. Therefore, each time the θ address specifying pulse arrives, the phase becomes C or C/. This appears as a flaw in the frame synchronizer, where the vertical lines become zigzag when played back.

The object of the present invention is to eliminate the conventional instability and always achieve only '1. .

An object of the present invention is to provide a start phase determining circuit which can provide a start phase of -.

Next, the present invention will be explained in detail with reference to the drawings.

Figure 2 is a block diagram of a frame synchronizer that converts an input television video signal into a different standard synchronization system signal. Input *m
The t-pass filter 2 removes signal components of half or more of the clock frequency in the input signal, and the A/D converter 4 samples the signal at the clock frequency (14 MHz) and converts it into P(,'M data 5. - A write clock pulse 12 synchronized with the color burst in the universal signal is generated by the write clock pulse generator 11, and a good write address 14 is generated by the write address generator 613 in synchronization with the synchronization signal of the input signal. The information for one frame period of the PCM data 5 is stored in the digital memory 6 at convolution address 1.
It is written to the location determined by 4.

On the other hand, read timing crystalline signal (black burst signal)
19 cuff-burst-synchronized readout pulses 1
2' is generated by the successive clock generator 11', and the successive address 1 is synchronized with the synchronization signal of the successive timing reference signal 19.
4' is generated by the read address generator 13'. Then, the PCM in the shift memory 6 is controlled by the successive address and read clock.
The data is read and the read output is D/A'':1
It is converted into a PAM signal by the converter 8, and by removing frequency components of more than half of the clock frequency by the output side low-pass filter 2', the nine television broadcast signal lO is synchronized with the readout reference signal, that is, it is synchronously converted. can get.

The write address 14 and the subsequent address [C are divided into the H address part and ■address part, respectively, and are processed according to the synchronization signal of the input television video signal and the subsequent Confucian standard synchronization signal, address 0 pulse generator 21.21 ' to determine the 0 address. In a frame synchronizer, in order for the color phase of the output to not change even if the 0th status phase of the H address moves, this movement must be done at a subcarrier period (2
80nsec).

■Address θ can be stably determined from ■synchronous phase and H synchronous phase, but H address θ has an unstable element in the phase relationship shown in Figure 1, so the O position phase may not be constant. . Even in the case of such a phase relationship, the 0 address pulse generator 21. supplies a stable H address 0 phase.
It is 21'.

Since the internal configurations of blocks 21 and 21' are exactly the same, block 21 will be described below. Figure 3 is 2a
The detailed configuration of the clock 21 in A is shown. 8 E P H synchronized and separated from the input video signal and made into H period
The Hals 30 is synchronized with the phase comparator 31° and the 7'j MO
By decoding the outputs of the NOCLOCK 34 and the 1/91 G counter 33, it is possible to obtain a WH2 pulse 36 corresponding to the width of one ring in the jlH period and a WHI pulse 35 having a width of 4 clocks in the H period.

Also, using the wh1 pulse as a clock, 97 Lippufu Pilgrimage Tsubu (
(b) A LINEF/F pulse 40 whose polarity is inverted every IH is obtained in the path 39. Using this LINEF/F pulse 40 and the wn2 pulse 36t-, a MONO8C pulse 38 having a subcarrier period synchronized with the 5EPH30 pulse is obtained. The relationship between signals 34, 35, 36, 38°40 is always fi, and LINE P/F pulse -40 is 1"
The phase relationship at level is as shown in FIG. On the other hand, the second
The 14MHz clock generated in response to the burst signal of the input Eirin signal by the BCO loop in the write clock generator shown in the figure is input to the counter 62 which divides the frequency by 4, and the 22 lower bit signals WSCO41 and W3C142 are latched. circuit 4
4 and is latched at the timing of MONO8038. Latch times M44Mi force Kl), WH1-1 H 52 (
The phase relationship between the WHI pulse 35 (a pulse delayed by one subcarrier) and the W8.01 pulse 42 (the relationship between the burst in the input signal and the horizontal synchronization signal) is determined.

This phase relationship determines the amount by which the jp and WHL-1 pulses are delayed. This WHI-1 pulse extracts the only timing corresponding to the 011n pulse from among the nine clocks generated by the BCO loop. This relationship will be explained in detail in section 1' of the theory that extracts the only 0 homachi pal and su.

As mentioned above, in the 7-frame synchronizer, the write side address generator 13 and the subsequent address generator 13'
Even if they operate independently, in order for the color phase to always be stable, the address signals 14° and 14' must always maintain the same phase relationship in the SC period with respect to each input burst signal. , the position of 0 honor ground also has an SC period (28
0n 5ec) Changes in cycles. Therefore, the 0 homachi designation pulse for the address counter clock is W8C
AND gate 6 from Q pulse 41 and W3C1 pulse 42
The W3C2 pulse Yton generated in B is extracted and used at the phase required for location specification. Therefore 8EPH3
It suffices if the address 0 homachi designation pulse WH135 with 0 as the big brother has a phase relationship with the WSC243t so that it can be extracted stably.

FIG. 5 is a diagram for explaining in detail the present invention, which brings the 0-point designated pulse WHI 35 to a stable region according to the phase relationship between the WSe2 43 and the MONO 8038.
a) shows the 14 MHz clock 12, the lower bit outputs W3C041 and W3C142 of the counter 62, and their ant output W3C243; %(b).

(C), (d) and (e) are the phase relationship of the MONO803g with respect to the phase indicated by (→), the output WHI-152 of the latch circuit 63, and the selector 51.
The signal 61 selected in FIG. In the case of (b), selector 51r, W) II-1 for 210ns (3X70)
WHI −4 delayed by w is selected, which causes w
Point P of sc243 is extracted as the timing indicating the start from ground 0#r. Similarly (C), (d) and (e)
Then delay by 140 n5 (2x70) each &W
WH delayed by HI-3t-170ns (IX70)
I-2t, select WHI-1 with no delay, and
The P point of Se243 is extracted. The selector 51 selects the output 56°5 of the latch circuit 44 via the delay line 48, 49 and the data through/hold circuit 50t.
It will be held at 7. In the invention, the phase of the burst signal in the input video signal and the horizontal synchronization signal 3 In Figure 3, the zero pulse is extracted from the AND gate 64, and is generated by the AND gate 65 to this gate 64. Vv8C
242, *0 point designation pulse 6 selected by vri151
1 and Aritub 7 A LINEF/F signal 40 from Hyp 39 is supplied. Since the IJNEF/F signal 40 is supplied in this way, the aO address pulse actually appears only once in 21i, but the frame synchronizer
Since the address counter circuit is composed of a ring counter or the like, it is possible to define a sufficiently accurate 0 address using information once every 2H. The reason why the LINE P/F signal 40 is supplied to the gate 64 is that the phase of the subcarrier and the horizontal synchronization signal differs by 1806 in the phase of the subcarrier for each line, so the operation of the latch circuit 63 is This is to avoid using the latch output when the output becomes unstable.

However, W3C041, W3C142 and MON0
If the phase relationship with 38 is shown in FIG. 6, i.e.
Signals 56,57 from latch circuit 44, ie W3C0
41, WSCI 44! When moving from (-) where is determined to be (0, 1) to (b) where it is determined to be (1, 0), the output of the selector 51 changes greatly from 61α to 61β, and is not extracted. It is conceivable that the phase will shift by 280118, and in the case of jin, the only position P cannot be extracted.In the present invention, in such a case (
(When entering the unstable region) Output 5 of the t-latch circuit 44
Decoder 45 receiving 6.57. A combination of the latch circuit 46 and the trigger flop 47 detects the error, and in such a case, the data through hold circuit 50 is changed to a function of holding the previous state to maintain a stable state. That is, the state of 61α is maintained to ensure that only one position P is extracted.

Next, the embodiment of the present invention will be described in more detail with reference to FIG. One of its outputs, Y1 signal 61
The signal 56,57 becomes level 0 under the condition of (1°0), and becomes level IK under other conditions. The same (Y signal 62 is at level 0 when signals 56, 57 are (0, 0)), and YS signal 63 is at level 0 when signals 56, 57 are (0, 1). Signal Y1. Yx and Ys are latch circuits 46 and are output by the decoder at the time of switching (
transient) is removed and the flip-flop circuit 47
supplied to The tree flop circuit 47 receives the signal Y1'
When signal 64 becomes level 0, the output signal becomes level l, and when either signal YSl'65 or signal Ys'66 becomes level 0, the output signal (HOLDCON'I' or
) 67 is a level 1 circuit.

Hold control signal 67 obtained in this way
is supplied to the data through m- hold circuit 50.0 time wI50 holds the data supplied to the input terminals Dt, Dg.If the control signal 67 is at level 0, it is supplied to the input terminal Dt,I)+ and holds the data supplied to the input terminal Dt, Dg. Output as is,
When the hold control signal 67 becomes level 1, the input data when the signal 67 changes from level 0 to level 1 is held while the signal 67 is at level 1. The delay lines 48, 49 are good ones having a delay time (i.e., a delay time in blocks 45, 46, 47) from Iman No. 56, 57 to obtaining the hold control signal 671-.

From the above explanation, in the case of the phase shown in Fig. 6, the signal 56°57 changes from (1, 0) - (0, 1), the output pulse 610 of the 4 selector 51 does not change in phase, and a stable 0 address regulation is established. It is clear that it can be done.

[Brief explanation of the drawing]

Figure 1 shows the clock and clear pulse (
This shows the phase at which the θ address regulation pulse) becomes unstable. FIG. 2 is a system diagram of a frame synchronizer as an example to which the present invention can be applied, FIG. 3 is a system diagram of an embodiment of the present invention, and FIG.
The figure shows various signals (blocks 31 to 31) in the embodiment of the present invention.
33.37°39) phase relationship diagram, #! FIG. 5 is a phase correction diagram of the 0-address specifying pulse with respect to the address generator phase, and FIG. 6 is a diagram of the phase relationship of the 0-address specifying pulse that becomes unstable when there is no hold circuit in the embodiment. Figure 1

Claims (1)

[Claims] A circuit that determines the only start timing from a pulse train synchronized with a burst signal by a horizontal synchronization signal in a television signal, the circuit comprising means for generating a first pulse train synchronized with the burst signal, and means synchronized with the horizontal synchronization signal. means for generating a second pulse train; means for latching the state of the first pulse train by the second pulse train and outputting a state signal; means for producing a third pulse having a predetermined pulse width; delay means for variably delaying the third pulse in accordance with the state signal; means for producing a fourth pulse train of equal frequency and uniform pulse width;
and extraction means for extracting a unique pulse from the fourth pulse train based on the third pulse from the delay means.