JPH0323018B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frame synchronization circuit for synchronizing each frame of received digital data.

In digital equipment that performs digital transmission, such as digital exchanges and information processing equipment,
In order to receive transmitted digital data without error, it is essential to synchronize it.

To achieve such synchronization, it is necessary to match the timing of the receiving device to the synchronization pattern added to the transmitted digital data, or to match the timing of the received data to the timing of the receiving device. There may be cases where this is not necessary.

[Conventional technology]

While a conventional frame synchronization circuit is equipped with a frame counter, the frame pattern of the received data is detected by a detection circuit, and the frame synchronization is performed by using the detected frame phase as a reference and matching the phase of the frame counter to that frame phase. There is something to take.

[Problem that the invention seeks to solve]

Since this type of frame synchronization circuit requires changing the phase of the frame counter, in a system configuration where the absolute phase within the system is determined by the frame counter, the frame synchronization circuit described above cannot be used in that system. Can not.

[Means for solving problems]

The present invention provides a frame synchronization circuit capable of solving the above-mentioned problems, and includes a reference frame counter, and input data including a data frame pattern is written using the count value of the reference frame counter as a write address. a memory, a frame pattern detection circuit connected to a read output of the memory, a temporary holding circuit that holds the count value of the reference frame counter in response to the output of the frame pattern detection circuit, and a count of the temporary holding circuit. and a count value of the reference frame counter when the phase difference between the phase of the write address and the phase of the read address is zero, and an output value of the difference output circuit. and a readout circuit that reads out data from the memory using a value obtained by correcting the count value of the reference frame counter as a readout address.

[Effect]

According to the circuit of the present invention, input data is written to the address of the memory indicated by the count value of the reference frame counter. The reading circuit reads out the memory, and in response to a frame pattern being detected by the frame pattern detection circuit, the count value of the reference frame counter is held in the temporary holding circuit. The difference output circuit outputs the difference between the held count value and the count value of the reference frame counter when the phase difference is zero. Since frame synchronization is achieved by using the count value of the reference frame counter corrected by the difference as a call address for reading data from the memory, the reference frame counter can be utilized for the synchronization. Therefore, the phase of the reference frame counter is not changed by input data and can be used as the absolute phase of the system.

〔Example〕

FIG. 1 shows one configuration example of a frame synchronization circuit. In this figure, 1 is a memory (RAM) into which input data including a data frame pattern input via line 2 is written and read.
The write address for memory 1 is supplied to the write section of memory 1 via line 5 from count output 4 of the reference frame counter. The count output 4 of the reference frame counter 3 is also connected to one input of an adder 6, and the adder 6 is composed of, for example, a TTL IC, and "1" is supplied to its Ci input. The reference frame counter 3 also has a reference frame pattern detection pulse output 7.

Reference numeral 8 denotes a frame pattern detection circuit connected to the readout output of the memory 1 and generating a data frame pattern detection pulse. The data frame pattern detection pulse of the frame pattern detection circuit 8 is supplied as a start pulse to a phase difference detection counter 10 constituting the phase difference detection circuit 9. The counter 10 also receives the reference frame pattern detection pulse of the reference frame counter 3 as a stop pulse. The output of counter 10 is connected via latch 11 to the other input of adder 6. The output of adder 6 is connected to the readout section of the memory.

The operation of the above-mentioned configuration circuit will be explained.

For convenience of explanation, it is assumed that the phase difference counter 10 is set to an initial state (zero output) and the operation of the circuit is started. Input data including a data frame pattern input via line 2 is written to memory 1 using the count value of the reference frame counter as a write address, and data is read from memory 1 using the output value of adder 6 as a read address.

The frame pattern of the read data is detected by the frame pattern detection circuit 8 and a data frame pattern detection pulse is generated, and this pulse is used as a start pulse to detect the phase difference detection counter 1.
0. Unless there is a phase difference between the data frame pattern detection pulse and the reference frame pattern detection pulse supplied from the reference frame counter 3, the counter 10 cannot perform a counting operation. That is, the count value is at zero indicating that there is no phase difference. The count value is latched in latch 11, supplied to adder 6, and added to the count value of the reference frame counter. Therefore, the read address of the memory 1 is the same as the address to which the input data was written.

However, if there is a phase difference between the reference frame pattern detection pulse and the data frame pattern detection pulse, a counting operation corresponding to the phase difference is generated in the counter 10. The adder 6 corrects the count value of the reference frame counter 3 by the count value to shift the timing of reading data from the memory 1 and synchronize the frames.
As is clear from the above, frames are synchronized without changing the phase of the reference frame counter.

FIG. 2 shows one embodiment of the invention. In this embodiment, a frame synchronization circuit is constructed without using the phase difference detection counter 10 required in the phase difference detection circuit 9 of FIG. That is, the count value of the reference frame counter 1 is latched in the latch 20 in response to the data frame pattern detection pulse, and when the count value and the data frame pattern match the reference frame pattern of the reference frame counter 3, the latch 20 is latched. The difference (phase difference) from the count value (α) that would be latched in the adder 2
1 (one example is configured similarly to adder 6).
It is designed so that it can be output from. The latch 20 and the adder 6 correspond to the temporary holding circuit and the readout circuit described in the sections ``Means for solving the problem'' and ``Operation'', respectively. 22, 23
is an inverter. Inverter 22, adder 2
1. The inverter 23 corresponds to the differential output circuit described in the [Means for solving the problem] and [Operation] sections. Other identical components are given the same reference numerals and their explanations will be omitted.

The basic operation of the frame synchronization operation explained with reference to FIG. 1 is the same in the circuit shown in FIG. will be mainly explained below.

As described above, when a frame pattern is detected by the frame pattern detection circuit 8, the count value of the reference frame counter 3 is latched in the latch 20 in response to the detection signal. The count value is supplied to one input of the adder 21 via an inverter 22.

The other input of this adder 21 has a phase difference between the phase of the write address (the phase of the address output from the reference frame counter 3) and the phase of the read address (the phase of the address output from the adder 6). When it is zero, the reference frame counter 3
Since the count value α is supplied, when the phase difference is zero, the adder 21 outputs a value of zero. Therefore, no modification of the read address in adder 6 occurs.

When a phase difference occurs between the phase of the write address and the phase of the read address, the adder 21 outputs a value corresponding to the phase difference. The count value of the reference frame counter 3 is corrected by that value in the adder 6, and the corrected count value is supplied to the memory 1 as a read address. In this way, the phase of the write address and the phase of the read address are synchronized.

As is clear from the foregoing, the reference frame counter 3 used in the system is utilized for frame synchronization. Since the phase of the reference frame counter 3 is not changed by input data, the phase is preserved.

〔Effect of the invention〕

As explained above, according to the present invention, the count value of the reference frame counter at the time when the frame pattern read out from the memory is detected is taken in and the difference from the reference phase value is calculated, so that the frame synchronization of the reference frame counter is It can be used for In its use, since the phase of the reference frame counter is not changed by input data, it can be used as the absolute phase of the system.

[Brief explanation of drawings]

FIG. 1 is a diagram showing one example of the configuration of a frame synchronization circuit, and FIG. 2 is a diagram showing an embodiment of the present invention. In the figure, 1 is a memory, 3 is a reference frame counter, 6 and 21 are adders, 8 is a frame pattern detection circuit, 9 is a phase difference detection circuit, 10 is a phase difference detection counter, 11 and 20 are latches, 22 and 23 is an inverter.

Claims (1)

[Claims] 1. A reference frame counter, a memory into which input data including a data frame pattern is written using the count value of the reference frame counter as a write address, and a frame pattern detection circuit connected to a read output of the memory. , a temporary holding circuit that holds the count value of the reference frame counter in response to the output of the frame pattern detection circuit; and a temporary holding circuit that holds the count value of the reference frame counter in response to the output of the frame pattern detection circuit; a difference output circuit that outputs the difference between the count value of the reference frame counter when the phase difference is zero; and a value obtained by correcting the count value of the reference frame counter by the output value of the difference output circuit, and uses the value as the read address. 1. A frame synchronization circuit comprising: a readout circuit for reading data from a memory.