JPH0548649B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention corrects the deviation caused by disturbance between a frame synchronization signal and a frame bit in a data signal in a data transmission system, and restores the frame bit to its original normal state. This invention relates to a frame bit recovery device.

[Conventional technology]

Conventionally, a large-scale integrated circuit (NEC's μPD7720), for example, was used as a transmitting integrated circuit, and a frame bit was added instead of a frame synchronization signal to the transmitted data signal, in other words, without transmitting a frame synchronization signal. In a system that transmits only a data signal and a transmission clock, as shown in Fig. 2, a frame bit f of alternating ``0'' and ``1'' is sent to the first bit of each frame in synchronization with a frame synchronization signal d. A method of adding information is generally used. The frame bits of “0” and “1” alternate are:
It is appended within the data by software within the integrated circuit. Transmission of the data signal containing frame bits is performed by applying the transmission clock to the serial clock (SCK).

In addition, in Figure 2, one frame is 256 bits.
This shows an example of inserting the frame bit f for frame synchronization at the beginning of the frame. For example, if the transmission speed is 16 kbps, the frame synchronization signal is
It becomes 62.5Hz. In other words, 16msec (=1/62.5Hz)
There is a frame synchronization signal every other time.

[Problem that the invention seeks to solve]

However, in such a signal format, when the serial clock (SCK) fluctuates due to disturbance, the number of bits in the frame changes, and as a result, the position of the frame bits deviates from the frame synchronization signal. That is, as shown in FIG. 3, when noise g enters the serial clock, a shift occurs in the data a output from the integrated circuit. Once the deviation occurs, the integrated circuit has no means to determine the deviation.
After that, the position of the frame bit and the frame synchronization signal remain out of alignment, and the original normal state is not restored. Therefore, as shown in FIG. 4, there is a problem if the data is out of sync in the transmission system that inputs the frame synchronization signal d to the integrated circuit 11 and the next pass 12 and transmits the output data from the sender (SEND) 13. occurs.

That is, the position of the frame bit in the output data from the integrated circuit 11 is assumed to be at the position of the frame synchronization signal d and is transmitted to the next process, that is, the next path 12, which causes an inconvenience. At this time, there is no problem because the receiving side (REC 14) synchronizes the frame from the frame bits "1" and "0" of data a, but in the case of Fig. 4, the process before transmission (next path 12) In this case, a shift occurs between the position of the frame bit and the position of the frame synchronization signal, resulting in the above-mentioned problem.

[Means for solving problems]

In order to solve these problems, the present invention
A means for adding frame bits to data in synchronization with a frame synchronization signal within an integrated circuit, means for detecting whether or not frame bits in the data signal are synchronized with the frame synchronization signal, and means for sending a signal to reset the integrated circuit when the bits are out of synchronization.

[Effect]

In the present invention, when a deviation occurs between the frame bits in the data signal and the frame synchronization signal due to disturbance, the large-scale integrated circuit is reset to eliminate this deviation.

〔Example〕

An embodiment of a frame bit recovery device according to the present invention is shown in FIG. In FIG. 1, 1 is a large-scale integrated circuit (for example, NEC μPD7720) as an additional means, 1a is a storage unit for data generated in the large-scale integrated circuit 1, and 2 is a data signal a input for synchronization detection. A synchronization bit detector as a detection means for outputting a signal b; 3 a reset signal generator as a reset means for inputting a synchronization detection signal b and outputting a reset signal c; 4 a frame synchronization signal d
5 is an input terminal to which the transmission clock e is input.

The operation of the frame bit recovery device configured as described above will be explained. First, large-scale integrated circuit 1
generates data with alternating frame bits of "0" and "1" added to the beginning of the data in synchronization with the frame synchronization signal d (see FIG. 2). This generated data is sent out from the serial output of the large-scale integrated circuit 1 as a data signal a. The data signal a is
By applying the transmission clock e to the input terminal 5, it is sent out from the serial out. The synchronization bit detector 2 detects that the data signal a is the frame synchronization signal d.
It is detected whether the frame bits are alternating "0" and "1" synchronized with the frame bit. If there is a bit shift between the generated data and data signal a, the frame bits of data signal a will not alternate between "0" and "1" synchronized with frame synchronization signal d, and synchronization bit detector 2 will detect synchronization. Does not output signal b. Conversely, if there is no bit shift between the generated data and data signal a, the synchronization bit detector 2 outputs a synchronization detection signal b. The synchronization bit detector 2 latches the data signal a at times [N] and [N+1] in synchronization with the frame synchronization signal d, obtains the values at times [N] and [N+1], and excludes the values. This can be realized by processing with a logical sum. In the reset signal generator 3,
Only when the synchronization bit detector 2 changes from outputting the synchronization detection signal b to not outputting the synchronization detection signal b, a reset signal c sufficient to reset the large-scale integrated circuit 1 is output. The large-scale integrated circuit 1 is reset by the reset signal c, and the frame bits return to their original normal state. That is, when the integrated circuit 1 is a signal processor, for example, by resetting the integrated circuit, the integrated circuit starts from the initial operation, that is, operates from the initial state in the same way as when the power is turned on.
Therefore, the out-of-synchronization frame bits can be restored to a normal state. Reset signal c
can be realized by using monomulti.

〔Effect of the invention〕

As explained above, the present invention resets the large-scale integrated circuit when the frame bits are not synchronized with the frame synchronization signal, so that the out-of-synchronization frame bits can be restored to their original normal state. effective.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the frame bit recovery device according to the present invention, Fig. 2 is a diagram showing an example of a frame structure used in data transmission, and Fig. 3 explains problems with the prior art. FIG. 4 is an explanatory diagram for explaining the problem of the prior art. 1...LSI, 1a...Storage section, 2...Synchronization bit detector, 3...Reset signal generator, 4, 5...
...Input terminal.

Claims (1)

[Claims] 1. In a data transmission system using an integrated circuit, a frame synchronization signal is applied to the integrated circuit from the outside, and within the integrated circuit, a frame of alternating "0" and "1" is added to the data in synchronization with the frame synchronization signal. adding means for adding bits; detecting means for detecting whether frame bits in the data signal output from the serial output of the integrated circuit are synchronized with the frame synchronization signal; 1. A frame bit recovery device comprising: reset means for sending a signal to reset the integrated circuit when the bits are not synchronized.