JP3516652B2 - Synchronization method and circuit of multi-bit signal - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to relates to a synchronization method and circuitry of the multi-bit signal, in particular, to a method and a circuit to ensure synchronization of the conversion time of the signal in step requiring conversion clock.

[0002]

2. Description of the Related Art Conventionally, in a multi-bit signal synchronizing circuit, the synchronization is performed with the multi-bit being kept as it is. In the case of performing synchronization with multiple bits, it is necessary to synchronize with data in which only one bit changes among the multiple bits in order to prevent data corruption due to synchronization shift.

[0003]

The above-mentioned synchronization of multi-bit signals has a problem that there is a dependency relationship that only one bit can change before and after data change.

An object of the present invention is to solve the above problems and to provide a multi-bit signal synchronizing circuit which is not affected by the number of changed bits when data changes.

[0005]

According to the method of synchronizing a multi-bit signal of the present invention, the data of the multi-bit signal is transferred to a first clock.
Synchronized when varying <br/> conversion into signals synchronized with the signal or we second clock, a step of synchronizing the data with the first clock, the previous data to the multi-bit data each d ₁ to a data change detecting step of detecting a change with d _2, the detection in the data change detecting step, at data temporary hold its data from the data change detection unit 2 reads the previous data d ₂ coercive Soo Step and data change detection signal k
A data change detection signal synchronization step of synchronizing ₁ with a second clock, and a data capture permission generation step of generating and outputting a capture permission signal k ₃ for permitting the capture of temporarily held data, signals that the last data in the temporary holding in the data acquisition signal k ₃ is synchronized with the second clock
Having a step of reading in the data d ₃ of.

Further, the same data change detecting step, and outputting the input data as the first previous data synchronized with the clock, the previous data d ₂ between the current input data d ₁ a data comparison step of outputting the data <br/> data change detection signal k ₄ when comparing the gender, are different,
Synchronize with the data change detection signal k ₄ first clock c ₁ Type and consists of a step of outputting the data change detection signal as k ₁ is inverted, the data change detection signal synchronization step, data change The data acquisition permission generation step includes the step of inverting the detection signal k ₁ and synchronizing with the second clock c ₂ , and the data acquisition permission generation step is permitted by the data change detection signal synchronized with the second clock c _2. Generated signal k ₃
Synchronization method is a step of generating output is one of the specific embodiment.

Further, the synchronization circuit of the multi-bit signal of the present invention converts the multi-bit data signals to signals in synchronism with the synchronized <br/> signal or we second clock to the first clock Many
A synchronization circuit of Tsu DOO signal, first and clocked circuit 1 to synchronize data at the first clock, the data change detection for detecting a change from the previous data d ₂ to the multi-bit data each d ₁ a means 2, the data change detecting means 2 outputs the data change detection signal k ₄ by the data change detecting means 2
The data temporary holding means 5 for reading and holding the previous data d ₂ from the above, the synchronization circuit 3 for synchronizing the data change detection signal k ₁ with the second clock, and the data temporary holding means 5
Data capture permission generation means 4 for generating and outputting a capture permission signal k ₃ for permitting the capture of the data held from the data capture signal k _{3 of the} data capture permission generation means 4.
A second clocked means 6 read out from the data temporary storage unit 5 in the data d ₃ of the signal in synchronization with data of the multi-bit signal to the second clock, the by.

Further, the data change detecting means 2 inputs the input data d ₁ and the first clock c _1, the first flip-flop 21 to output in synchronization with the first clock c ₁
If, by comparing the identity of the output a previous data d ₂ is the input data d ₁ of the first flip-flop 21, a comparator 22 for outputting a data change detection signal k ₄ When different, de synchronizing the first clock c ₁ enter the over data change detection signal k _4, made from the second flip-flop 24 for outputting the first inverter 2 3 as k ₁ by inverting the data change detection signal , Second synchronization means 3
But the third flip-flop 25 to input and output k ₁ of the second flip-flop 24 and a second clock c ₂
And the output of the third flip-flop 25,
Fourth flip-flop 2 which is synchronized with the clock c ₂ of
6, the data fetching permission generating means 4 takes the exclusive OR of the output k _{2 of} the fourth flip-flop 26 and the output of the fifth flip-flop 29 and outputs the data of the fourth flip-flop 26 . A first EXOR gate 27 that outputs an inverted output by an inverted output based on the data change detection signal ,
The output of the first EXOR gate 27 is set to the second clock c ₂
By synchronizing, the fifth flip-flop 29 takes in the inverted by the second inverter 28, the output of the fifth flip-flop 29 synchronizes with the second clock c _2, the output of the second EXOR gate 31 And a fifth flip-flop 29 for taking in
Synchronization circuit of the output and the second EXOR gate 31 which receives the output of flip-flop 30 of the sixth multi-bit signal consisting of is an exemplary specific embodiments of this invention.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of a multi-bit signal synchronization circuit to which the multi-bit signal synchronization method of the present invention is applied.

The synchronization circuit according to the present embodiment has a first clock
The first clock operation circuit 1 that outputs based on the clock,
A data change detection unit 2 for detecting a data change by comparing the multi-bit signal data d ₁ output from the first clock operation circuit with the previously output data d ₂ and a signal k for notifying the data change detection. ₄ , the data temporary holding unit 5 that holds the previous data d ₂ at the first clock, the synchronization circuit 3 that synchronizes the data change detection signal k ₁ at the second clock c ₂ , and the instruction for data acquisition a data acquisition permission generating unit 4 which, taken in as data acquisition permission signal k ₃ data d ₃ of the signal that is synchronized from the temporary holding section data to multi-bit signal data d ₃ to the second clock c ₂ by the output And a second clock operation circuit 6.

The multi-bit signal data change detection unit 2 outputs a multi-bit signal d ₁ output from the first clock operation circuit _1.
And the data held one clock before are compared to detect whether the data has changed. When detecting a change in data, the multi-bit signal data change detection unit 2 gives an instruction to the data temporary holding unit 5 to hold the data.

Further, the data change detection unit 2 for the multi-bit signal
1 to notify the synchronization circuit 3 that the data output from the first clock operation circuit 1 has changed.
The bit detection result k ₁ is inverted. The synchronization circuit 3 synchronizes the 1-bit detection result k ₁ in the second clock c ₂ from the data change detection unit 2 of the multi-bit signal.

The data fetch permission generation unit 4 generates a data fetch permission signal k ₃ for the second clock operation circuit 6 to receive the temporary holding data d ₃ from the data temporary holding unit 5, and the second clock operation circuit Notify 6. The second clock operation circuit 6 receives the temporary holding data d ₃ from the temporary data holding unit 5 in response to the data loading permission signal k ₃ from the data loading permission generation unit 4.

Next, the details of the multi-bit signal data change detection unit 2, the synchronization circuit 3, and the data acquisition permission generation unit 4 will be described with reference to FIG. First, the data change detection unit 2 for a multi-bit signal includes a flip-flop (FF) 21, a comparator 22, an inverter 23, and an FF 24. FF21 holds data d ₁ from the first clocked circuit 1 are operating in synchronism with the first clock c _1.

The comparator 22 compares the output data of the first clock operating circuit 1 with the output data of the FF 21, and outputs the result to the FF 24.
Notify to. FF 24 operating with the first clock c ₁
Inverts the output according to the comparison result from the comparator 22. The output of the FF 24 is F that operates on the second clock.
Input to F25. Next, the synchronization circuit 3 uses the FF2
5 and FF 26. The FF 25 is operating with the second clock c ₂ , and the output from the FF 24 operating with the first clock c ₁ is input. The FF 26 is operating with the second clock c ₂ and the output of the FF 25 is input. The output of the FF 26 is input to the EXOR circuit 27.

Finally, the data acquisition permission generation unit 4 uses the EX
OR circuit 27, inverter 28, FF29, FF30,
It is composed of an EXOR circuit 31. EXOR circuit 27
Receives the outputs of FF26 and FF29 and creates a permission signal for inverting the output of FF29. FF29 is EXOR
The output is inverted by the output inversion permission signal from the circuit 27.

The EXOR circuit 31 has FF29 and FF3.
The output of 0 is input. The EXOR circuit 31 generates the data fetch enable signal k ₃ for the second clock operation circuit 6 and is also used as a latch enable signal for the FF 30. The FF 30 fetches the output of F F 29 in response to the data fetching permission signal k ₃ of the EXOR circuit 31.

Next, the operation of the circuit shown in FIG. 1 will be described. First clock c ₁ to 100 MHz z, the second clock c ₂ a 120MH z, a multi-bit signal that is synchronized 4
Illustrating a second clocked circuit 6 to operate the 4-bit signal is passed in the first clocked circuit 1 from 120MH z of 100 MHz z assuming bits.

[0019] When 4-bit signal output from the first clocked circuit 1 of the 100 MHz z is changed to "Ah" from "5h" in hexadecimal representation, the data changes in the data change detection unit 2 of the multi-bit signal Upon detection, the temporary data holding unit 5 is instructed to hold the data of "5h". The data temporary storage unit 5, a detection result k ₄ from the data change detection unit 2 of the multi-bit signal becomes "1", holds the "5h" data from the data d _2.

Further, the data change detection unit 2 for the multi-bit signal
Then, when a data change is detected, the 1-bit detection result k ₁ to the synchronizing circuit 3 is inverted. It is assumed that "0" has been output and is inverted to "1". The synchronization circuit 3, a 1-bit detection result k ₁ from the data change detection unit 2 of the multi-bit signal to synchronize with 120MH z, and outputs the data acquisition permission generator 4.

[0021] The data acquisition permission generating unit 4, data acquisition permission signal k ₃ of the second operation circuit 6 of 120MH z by detecting a change from "1" to output "0" from the synchronization circuit 3 "1" is output to. In 120MH z operation circuit 6, temporarily holding data d ₃ from the data temporary storage unit 5 Once the data capture permission signal k ₃ becomes "1""5
".100MH z operation circuit 1 data d ₁ is further from capturing" 3h "is a change to the same manner multibit signal in the data change detection unit 2 of the data to" Ah "from" 3 h
When the change to "h" is detected, the data temporary holding unit 5 is instructed to hold the "Ah" data.

The detection result k ₁ to the synchronizing circuit 3 is also inverted from "1" to "0". In the synchronization circuit 3, 1
To synchronize with 20MH z. The output to the data acquisition permission generation unit 4 changes from "1" to "0". In the data acquisition permission generating unit 4 detects that the output from the synchronization circuit 3 is changed to "1" to "0", and outputs "1" to the data acquisition permission signal k _3. In the second clocked circuits 6 of 120MH z, data capture permission signal is "1"
Then, "Ah" from the temporary data holding unit 5 is fetched.

Referring to FIG. 2, the FF 21 is 100 HM.
The 4-bit signal from the first clock operating circuit 1 of z
The clock of 0MH z have taken in synchronization with each other. Comparator 22, if the same data by comparing the first output of the clock operation circuit 1 and the output of the 100 MHz z of FF 21 "0", and outputs "1" if they differ. FF24
When the output from the comparator 22 becomes "1", the inverter 23 inverts and takes in the output of the FF 24.

The FF25 is 120MH z, FF24 10
In 0MH z operation, this portion is asynchronous. FF26
It is capturing synchronously output from FF25 to 120MH z. EX by changing the output of FF26
The output of the OR circuit 27 becomes "1". FF29 is EX
When the output of the OR circuit 27 becomes "1", the inverter 28 inverts and takes in the output of the FF 29. When the output of the FF 29 is inverted, the input of the EXOR circuit 27 has the same value, so the output of the EXOR circuit 27 becomes "0".

Further, when the output of the FF 29 changes, E
The output of the XOR circuit 31 becomes "1", and the FF 30 outputs E
When the output of the XOR circuit 31 becomes "1", the output of the FF 29 is fetched.

Referring to FIG. 3, the data d ₁ is 100
The data from the first clock operating circuit 1 of MH z is “5”.
h "to" Ah "," about Ah is changed to 3h "" from ". Data d ₂ is changed even data d ₂ after one clock data d ₁ is changed by the output of the FF 21.

The detection result k ₄ is the output of the comparator 22, and the comparator 22 outputs the data d ₁ and the data d _2.
Are output, "0" is output for the same data, and "1" is output for different data. The detection result k ₄ is the data d ₁
There "Ah", data d ₂ is outputting each "1" when the "5h" and when the "3h" and "Ah". The output of the detection result k ₁ is inverted when the detection result k ₄ becomes “1”.

[0028] In addition, data d ₃ is, the detection result k ₄ "1"
When it comes to one in which data of data d ₂ is taken in synchronization with the first clock c _1. The detection result k ₄ is input to the FF 25. The detection result k ₂ is the output of the FF 25.

When the detection result k ₂ changes from "0" to "1", the output of the EXOR circuit 27 becomes "1". FF2
The output of the 9, E XOR circuit 27 inverts the output becomes "1".

The detection result k ₃ becomes "1" when the output of the FF 29 is inverted. The second clock operation circuit 6 takes in the data d ₃ when the detection result k ₃ becomes “1”.
Further, when the detection result k ₃ becomes “1”, the output of the FF 30 is inverted.

In addition, the first clock c ₁ is set to 120 MH
z, also it is operated in the same circuit configuration as the above-described embodiments in the case where the second clock c ₂ assuming 100 MHz z.

[0032]

As described above, according to the present invention, the following effects can be obtained by providing the data change detecting portion for the multi-bit signal, detecting the data change and outputting the data change detection signal.

The first effect is that the multi-bit signal to be synchronized has no dependency on the data before and after the change, and can cope with any multi-bit signal. The reason is that when a multi-bit signal to be synchronized changes, it is detected that it has changed, the data before synchronization is temporarily held by the clock before synchronization, and the fact that it has changed again This is because, after being notified as a detection result and being synchronized, a fetching permission signal for the temporarily held data is generated and fetched at the clock after synchronization.

The second effect is that the addition of the data change detecting unit for the multi-bit signal can prevent the synchronization deviation from occurring in the multi-bit synchronization and prevent the data corruption. The reason is that when a multi-bit signal to be synchronized changes, the change is detected, and the change is notified to the synchronizing circuit as a 1-bit detection result to synchronize.

[Brief description of drawings]

FIG. 1 is a block diagram of a multi-bit signal synchronization circuit of the present invention.

FIG. 2 is a data change detection unit 2 for a multi-bit signal shown in FIG.
When a synchronization circuit 3, a detailed circuit diagram of an embodiment of a data acquisition permission generating unit 4.

FIG. 3 is a timing chart of each signal at the first and second clocks of the multi-bit signal synchronization circuit shown in FIG.

FIG. 4 is a flowchart of an embodiment of a multi-bit signal synchronization method of the present invention.

[Explanation of symbols]

1 first clocked circuit 2 data change detection unit 3 synchronizing circuit 4 Romantic acquisition permission generating unit 5 data temporary holding portion 6 second clocked circuit 21,24,25,26,29,30 flip-flop 22 comparator 23, 28 Inverters 27, 31 Exclusive OR ( EXOR) circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04L 7/00 H03L 7/00 H04L 29/02

Claims (8)

(57) [Claims] 1. A synchronization method for a multi-bit signal, signal synchronized multi-bit data signal to the first clock
When converting the signal synchronized with the pressurized et second clock, a step of synchronizing the data with the first clock, the previous data every multi-bit data (d ₁₎ (d ₂₎ change The data change detecting step for detecting that the data change detecting step and the data change detecting step detects the previous data (d ₂ ) from the data change detecting means (2).
Allow the temporary data retention Soo step, and the data change detection signal synchronization step of synchronizing the data change detection signal (k ₁₎ by the second clock, the capture of data temporarily held for holding the data a data acquisition permission generating step for generating and outputting a capture permission signal (k ₃₎ of the data acquisition signal (k ₃₎ by temporarily storing in the previous
It has a step of reading data in the data (d ₃₎ of the signal synchronized with the second clock, the synchronization method of the multi-bit signal. 2. A data change detecting step, and outputting the previous data the input data synchronously with the first clock, the previous data and (d ₂₎ the current input data (d ₁₎ comparing the identity of the data comparison step of outputting the data change detection signal (k ₄₎ when it is different, enter the data change detection signal (k ₄₎ said first clock (c ₁₎ in synchronizing consists of a step of inverting and outputting the data change detection signal as (k _1), the data change detection signal synchronization step, by reversing the data change detection signal (k ₁₎ of the second clock (C ₂ ) synchronizing step, wherein the step of generating the data acquisition permission includes the step of synchronizing the second clock.
The method for synchronizing a multi-bit signal according to claim 1 , which is a step of generating and outputting a data fetch permission generation signal (k ₃ ) by a data change detection signal synchronized with (c ₂ ) . Wherein the frequency of said first clock second
The method for synchronizing a multi-bit signal according to claim 1 or 2 , wherein the frequency is higher than the frequency of the clock . Wherein said frequency of said first clock second
The method for synchronizing a multi-bit signal according to claim 1 or 2 , wherein the frequency is lower than the clock frequency . 5. The data of a multi- bit signal is converted into a first clock signal.
<br/> into a signal synchronized with the synchronous signal or we second clock click, a synchronizing circuit of the multi-bit signal, the first clock to synchronize data with said first clock The operation circuit (1), the data change detection means (2) for detecting the change from the previous data (d ₂ ) for each multi-bit data (d ₁ ), and the data change detection means (2) output a data change detection signal (k ₄₎ by the data change detection unit data temporary holding means for holding reads previous data from _{(2) (d 2) (} 5), the data change detection signal (k ₁₎ of the second (3) for synchronizing with the clock of (3), and a data fetch for generating and outputting a fetch permission signal (k ₃ ) for permitting fetch of the held data from the data temporary holding means (5). Permission generation means (4) and data acquisition permission generation Stage (4) data acquisition signal (k ₃₎ signal that is synchronized from the data temporary holding means (5) the data of the multi-bit signal to the second clock by the
Data having the (d ₃₎ to to read the second clocked means (6), the synchronization circuit of the multi-bit signal. 6. A data change detecting means (2) is, as input and input data (d ₁₎ and said first clock (c _1),
Said first clock first flip-flop (21) for output in synchronization with (c _1), the previous data which is the output of the first flip-flop (21) (d ₂₎ and the input data (d ₁₎ comparing the identity and, a comparator (22) for outputting the data change detection signal (k ₄₎ when it is different, enter the data change detection signal (k ₄₎ said first clock ( Synchronize with c ₁ ) and use the first inverter (2 3 )
And a second flip-flop (24) which inverts the data change detection signal and outputs it as (k ₁ ). The second synchronizing means (3) outputs the second flip-flop 24 (k). type third flip-flop for inputting and ₁₎ and the second clock (c ₂₎ (25), the output of the third flip-flop (25), before
Serial it from the fourth flip-flop (26) to be synchronized with the second clock (c _2), data acquisition grant generation means (4) is the output of the fourth flip-flop (26) (k ₂₎ When the first EXOR which outputs the inverted output by inverting the output based on the data change detection signal of the fourth flip-flop takes the exclusive OR of the output of the fifth flip-flop (29) (26)
Gate (27) and the output of the first EXOR gate (27) synchronized with the second clock (c _2), a second inverter (28)
The said fifth flip-flop capturing inverted (29), said second output of said fifth flip-flop (29)
Clock synchronize with (c _2), the sixth flip-flop to capture the output of the second EXOR gate (31) (3
0), the output of the fifth flip-flop (29) 6
Synchronization circuitry of the multi-bit signal according to the second EXOR gate for receiving as input (31) output, to claim 5 consisting of the flip-flop (30) of. Wherein said frequency of said first clock second
7. The multi-bit signal synchronization circuit according to claim 5, which has a frequency higher than the clock frequency . Wherein said frequency of said first clock second
7. The multi-bit signal synchronization circuit according to claim 5, which is lower than the frequency of the clock .