JP2003332896A - Digital delay circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To dissolve a problem that a circuit is complicated by providing a redundant register block and a coincidence judging block, and designing is hard due to a skew between the internal blocks concerning the rise and fall edges in a digital signal. <P>SOLUTION: A rise and fall detecting means 100 detects the rise or fall of the digital signal DS1, and the number of clocks in the detection are stored in a clock count number storage means 300. The delay amount DT of the digital signal is set in a delay amount setting means 600 as the number of the clocks. A count number measuring means 500 obtains the sum of the number of the clocks in the clock count storage means 300 and the delay amount setting means 600. When a delay amount detecting means 700 detects coincidence between the count number measuring means 500 and a clock count means 400, a digital signal reproducing means 800 outputs a delayed signal DDS1. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital delay circuit for delaying a digital signal.

[0002]

2. Description of the Related Art In a digital signal processing system,
When the mechanical section is controlled by digital signal output and the response from the mechanical section becomes the input of the system, a certain delay is added to the response of the mechanical section. For example, it is a case of controlling a motor with a digital circuit. FIG. 18 is a block diagram of a system that controls the rotation of a motor by digital control. The phase data PD for motor control is input from the digital control means 1800 to the motor driver 1810, and the motor driver 181
0 drives the motor 1820. At this time, the rotation angle of the motor is detected by the sensor 1830 and its output is fed back to the digital control means 1800. Since the response speed of the mechanical portion such as the motor has a certain delay, the output of the sensor 1830 is delayed from the phase data PD.
Not in sync. The output of the digital control means 1800,
For example, in order to synchronize the phase data PD with the output of the sensor 1830, it is necessary to delay the phase data PD in the digital control unit 1800. As such a digital signal delay circuit, for example, Japanese Patent Application Laid-Open No. 7-25484.
There is 9.

FIG. 2 is an example of a block diagram of a conventional digital delay circuit. In this example, when the rising / falling detection block 10 which detects the rising / falling edge of the digital signal detects the edge of the signal TS, the time code at that time is given by the time code generation block 20. This time code is
If the edge is a rising edge, it is stored in the register block 30, and if the edge is a falling edge, it is stored in the register block 40. The time code generation block 20 is provided with a delay amount by the input signal DL. In this time code generation block 20, the generated time code and the set D
In this configuration, the values of L are compared, and if they match, the time code is reset to "1". The set value of the register block 30 or the register block 40 in which the time code is set, that is, the output is the match determination block 50 or 60.
At, the output is compared with the output of the time code generation block 20. Then, when the output of the time code generation block 20 makes one round and coincides with the set value of the register block 30 or 40, the coincidence determination block 50 or 60 gives an initialization signal to the register block 30 or 40, and A set or reset signal is given to the JK flip-flop 70, and the delayed digital signal is reproduced.

[0004]

However, JP-A-7-2
The circuit of 54849 has a plurality of register blocks and match determination blocks that have exactly the same functions for the rising edge and the falling edge of the input digital signal. In other words, it has a plurality of identical blocks corresponding to the difference in the edge direction. This leads to more complicated and large-scale digital signal delay circuits. In addition, the relationship of signals is asynchronous among many components (between blocks). Therefore, if the circuit scale becomes large, there is a possibility that a malfunction will occur due to the skew between the constituent elements. Furthermore, when this circuit is integrated into an IC, there is a drawback that skew control becomes complicated.

The present invention has been made to solve such a problem, and it is possible to delay a digital signal with a minimum number of blocks regardless of the rising edge and the falling edge of the digital signal. To do. Furthermore, it is an object of the present invention to simplify the control of the skew between the constituent elements by controlling in a synchronous manner.

[0006]

In order to solve the above problems, the following inventions are provided. One aspect of the digital delay circuit of the present invention is, in a digital delay circuit for delaying a digital signal, edge detection means for detecting a rising edge or a falling edge of the digital signal, and at least 1.
A clock counting means which is a bit free-run counter, a clock count number storing means which stores a clock count number of the clock counting means when the edge detecting means detects an edge, and a delay amount which sets a delay amount of a digital signal. Setting means, count number measuring means for obtaining the sum of the delay amount set in the delay amount setting means and the clock count number stored in the clock count storage means, and clock count numbers of the count number measuring means and the clock count means Delay amount detecting means for detecting that the two match,
Digital signal reproducing means for reproducing the delayed digital signal based on the coincidence information from the delay amount detecting means. Another aspect of the digital delay circuit of the present invention further has edge direction storage means for storing the edge direction of the digital signal, and the edge direction storage means stores the edge direction storage means based on the coincidence information from the delay amount detection means. It is characterized by clearing the valid / invalid information in the edge direction. According to another aspect of the digital delay circuit of the present invention, the edge detecting means detects a plurality of rising or falling edges of the digital signal, and the clock count number storing means of the clock counting means detects a plurality of edges. The present invention is characterized by including a storage unit control block that stores a plurality of clock count numbers and stores the plurality of clock count numbers in a specific storage register of the clock count number storage unit. According to this aspect, it is possible to delay the rising and falling edges of the digital signal.

[0007]

1 is a block diagram of a digital delay circuit according to a first embodiment of the present invention. The delay circuit is provided with a rising / falling detecting means (edge detecting means) 100 for detecting a rising edge and a falling edge of the input signal DS1. When an edge of the input signal DS1 is detected by the rising / falling detection means 100, whether the edge is a rising edge or a falling edge is determined.
In addition to being stored in the edge direction storage means 200, the clock count number output from the clock count means 400 when an edge is detected is stored in the clock count number storage means 300. Count number measuring means 500
And the delay amount detecting means 700, the delay amount setting means 60
By detecting that the time corresponding to the delay amount preset to 0 has elapsed, the rising edge or the falling edge of the edge is reproduced by the digital signal reproducing means 800, and the delay signal of the digital input signal is obtained. The delay amount is set to be larger than the signal change cycle.

The digital delay circuit has a terminal si for inputting a delayed input signal DS1, a terminal dat for setting delay data DT for setting a delay amount, and a write control signal WR for writing the delay data DT. Terminal wri for inputting and terminal clk for inputting clock CLK
And a terminal rst for inputting the RST signal for initializing the entire digital delay circuit. Input terminal s
i is connected to the rise / fall detection means 100, and the input terminals clk and rst are connected to the rise / fall detection means 100 and the edge direction storage means 200,
It is connected to the clock count number storage means 300 and the digital signal reproduction means 800. Also, the input terminal da
The t, the input terminal wri, and the input terminal rst are connected to the delay amount setting means 600. The rising / falling detection means 100 detects the rising or falling of the digital input signal DS1 in synchronization with the clock CLK, and outputs the rising detection signal RE if it is rising and outputs the falling detection signal FE if it is falling. To do.
The clock counting means 400 has a bit configuration of at least 1 bit or more and counts in synchronization with the clock CLK. After all the constituent bits are set, that is, after counting the maximum value, the count is automatically returned to 0. When the RE or FE is output, the edge direction storage means 200 stores, for example, "1" in the case of rising, that is, RE, and "0" in the case of falling, that is, FE. Further, the edge direction storage means 200 also includes a portion indicating whether the stored edge direction described later is valid or not. When RE or FE is output from the rise / fall detection means 100, the count value indicated by the clock count means 400 at that time is stored in the clock count number storage means 300 as the number of clocks. The delay data DT is set in the delay amount setting means 600 as a delay amount by the write control signal WR. The delay amount set in the delay amount setting means 600 is sent to the count number measuring means 500.

On the other hand, the clock count storage means 300
The number of clocks stored in is sent to the count measuring means 500 and added to the delay amount. The result of addition by the count measuring means 500 is input to the delay amount detecting means 700 together with the output of the clock counting means 400, and it is detected whether or not they match. Delay amount detecting means 700
Then, when a match is detected, this information is input to the edge direction storage means 200, and the stored part indicating the valid / invalid of the edge direction is cleared. Further, the information is also input to the digital signal reproducing means 800 to reproduce the digital signal.

FIG. 3 shows the rise / fall detection means 1
00 shows one configuration example. The rising / falling detecting means 100 includes a D-type flip-flop (hereinafter referred to as D-FF) 101, a D-FF 102, and a 2-input AND.
It consists of a gate 103 and a 2-input NOR gate 104. Generally, one D-FF is enough, but in this embodiment,
Digital input signal DS asynchronous to clock CLK
Even if it is 1, the D-FF is configured in two stages so that rising or falling can be surely detected. The digital input signal DS1 is completely synchronized with the clock CLK by the D-FF 101 and output as the signal 105. The synchronized signal 105 is taken into the D-FF 102 by the next clock CLK. The logic of the signal 105 delayed by one cycle by the D-FF 102 is inverted,
It is output as the signal 106. AND gate 103 and NOR gate 104 have signals 105 and 10
6 is input. The AND gate 103 generates a rising edge detection signal RE that becomes high level when the digital input DS1 rises. On the other hand, NOR gate 10
In No. 4, when the digital input signal DS1 falls, the fall detection signal FE which becomes high level is generated.

FIG. 4 shows an example of the configuration of the clock counting means 400. The clock counter 401 is initialized to “0” by the initialization signal RST, and keeps counting while the initialization signal RST is “1”. When all bits are set to “1”, that is, (Q0, Q1, Q
2, ..., Qn) = (1,1,1, ..., 1), the next count is (Q0, Q1, Q2, ...
., Qn) = (0,0,0, ..., 0). Therefore, the number of bits of the counter 401 does not need to be larger than the delay data DT, and the same number of bits can be used. The count value is output as Dckout 402.

FIG. 5A shows an edge direction storage means 200.
A configuration example of the clock count number storage means 300 is shown. In this embodiment, the edge direction storage means 200 and the clock count number storage means 300 are integrated into one storage block, but they may be configured as separate storage blocks as in FIG. These two storage means are composed of an n + 2 bit D-FF 301 (hereinafter, storage register 301) which takes in an input only when the take-in permission input EN is at a high level. The Dn + 2nd bit indicates whether or not the stored edge direction is valid. For example, "1" indicates valid, and "0" indicates invalid. The reverse is also acceptable. Dn + 1 represents the stored edge direction,
If it is "1", it means rising, and if it is "0", it means falling. The reverse is also acceptable. From D0 to Dn, the clock counting means 40 when the rising detection signal RE or the falling detection signal FE is input
The count number of 0 is stored. In the present embodiment, the rising edge detection signal RE and the falling edge detection signal FE are connected to the input of the 2-input OR gate 302, and the output of the 2-input OR gate 302 is the acquisition permission input E of the storage register 301.
It is connected to N and bit Dn + 2 of the storage register 301 to set valid / invalid in the edge direction. on the other hand,
The rising edge detection signal RE is Dn of the storage register 301.
It is connected to the + 1st bit and stores the edge direction. All of these signals are taken in in synchronization with the clock CLK. Further, the coincidence detection signal output by the delay amount detecting means 700 is input to the inverter 303,
The output is input to the 2-input AND gate 304 together with the initialization signal CLR. The output of the 2-input AND gate 304 is connected to the RST terminal of the storage register 301,
It is configured to initialize the storage register 301 when a match is detected. When the edge direction storage means 200 and the clock count number storage means 300 are composed of separate storage registers, the storage registers do not necessarily have to be initialized by the coincidence signal as described above.

FIG. 5B is a diagram showing the information stored in the storage register 301. The count number of the clock is stored from 0 bit to n bit, the edge direction is stored in n + 1 bit, and the stored edge direction is stored in n + 2 bit whether it is valid or invalid.

FIG. 6 shows an example of the configuration of the delay amount setting means 600. The delay amount setting means 600 is connected with n-bit delay data as an input, and is connected with the write control signal WR as a clock input of the D-FF. The delay data DL is written by these two input signals. Although the n-bit D-FF is used in this embodiment, an n-bit latch may be used.

FIG. 7 shows an example of the configuration of the count number measuring means 500. As the count number measuring means 500, an adder circuit is used in this embodiment. Count number measuring means 500
A Dmout 502 which is an output of the clock count number storage means 300 and a Ddelay 503 which is an output of the delay amount setting means 600 are connected as inputs to the. Then, Dmout 502 and Ddelay 503 are added, and the addition result is output as Dadd 504.

FIG. 8 shows a configuration example of the delay amount detecting means 700 and the digital signal reproducing means 800. The match detector 701 detects a match between the Dadd 504 and the Dckout 402, and outputs “H” when they match. The match signal SM803, which is the output at the time of this match detection, is connected to the match detection control block 801. The match detection control block 801 synchronizes with the clock CLK and outputs the match signal SM80.
3 is taken in, and at that timing, the edge direction storage means 20
ED, which is bit data representing the edge direction stored in 0, is fetched and output as ED ′ in synchronization with the clock CLK. At this time, 2t at the same timing
The SEL 804 which is a signal which becomes “H” for one cycle of the clock CLK is output to the o1 selector 805. By this operation, the D-FF 802 is set to the value of ED '. After this timing, the SEL 804 becomes "L" and the D-FF 802 outputs the current output DD.
Hold S1.

FIG. 9 is a state transition diagram of the match detection control block 801. The match detection control block 801 in the normal idle state idle sets the SEL to "H" when the match signal SM803 becomes "H", and transits to the match detection state det. The match detection control block 801 that has transited to det transits to the idle state idle at the next clock timing. In this state, the match signal SM
Since 803 has already returned to "L", it does not transition to det again.

FIG. 10 is a block diagram of a digital delay circuit according to the second embodiment of the present invention. In this embodiment, there is provided a rising / falling detecting means 100 for detecting two or more rising / falling edges of the digital input signal DS1. The detected rising signal RE or falling signal FE is connected to the storage means control block 900. The clock counting means 400 uses the initialization signal RST.
Is asynchronously initialized by the initialization signal RST during the period of "L", and then counts in synchronization with the clock input CLK. This count output is the edge direction / clock count number storage means B 220 as Dckout 402.
And a count number measuring means B950. Further, the delay amount setting means 600 is connected with the delay data DT through the terminal dat and is connected with the delay data write control signal WR through the terminal wri. The delay data DT is written by the delay data write control signal WR.
On the rising edge of. Note that writing may be performed at the falling edge. Storage means control block 90
From 0, Mselw to select the write register,
Read register selection signals DR and ENP are output,
It is connected to the edge direction / clock count number storage means B220. The read register selection signal DR is also connected to the count number measuring means B950. The delay data set in the delay amount setting means 600 is Ddelay50.
3 is input to the count number measuring means B950. The count number measuring means B950 outputs a digital signal DDS1 which is a reproduction of the delayed DS1 and outputs a signal R for controlling the read register selection signal DR.
D_buf 951 is output and the storage means control block 9
00 is connected.

The rising / falling detecting means 10
0, the clock counting means 400, and the delay amount setting means 600 have internal configurations shown in FIGS. 3, 4, and 6, respectively.
Is the same as.

FIG. 11 shows an example of the configuration of the storage means control block 900. Rise / fall detection means 100
Rising signal RE and falling signal F detected in
E is input to the 2-input OR gate 901. The counter block 902 outputs the output EN of the 2-input OR gate 901.
It is a 2-bit counter that counts when P is "H". The counter block 902 controls the edge direction / clock count number storage unit B220 to specify a register to be written among two or more storage registers. In this embodiment, a 2-bit counter has been described, but a 1-bit counter can be used and a 3-bit or more counter may be used. The write register control signals DW0 and DW1 output from the counter block 902 are input to the decode block 903. In the decoding block 903, the input DW
The write register selection signal Mselw0 / Mselw1 / Mselw2 / M depends on the combination of 0 and DW1.
Only one arbitrary bit of selw3 is set to "H", and the remaining bits are set to "L". Note that this decoding method is reversed and only one arbitrary bit is "L".
Alternatively, the remaining bits may be set to "H".

On the other hand, the counter block 904 controls the edge direction / clock count number storage means B220 to identify a register to be read from among two or more storage registers. The counter block 904 is
This is a 2-bit counter that performs a count operation and outputs read register control signals DR0 and DR1 when RD_buf 951 is “H”. This counter may be a 1-bit counter or a 3-bit or more counter, but the number of bits needs to match that of the counter block 902. Counter block 904
The outputs DR0 and DR1 of are input to the decode block 905. In the decoding block 905, the read register selection signal Mselr0 / Mselr1 / Mselr2 is set according to the combination of the input DR0 and DR1.
Only one arbitrary bit of / Mselr3 is set to "H", and the remaining bits are set to "L". In addition,
This decoding method may be reversed to set only one arbitrary bit to "L" and the remaining bits to "H".

FIG. 12 shows a configuration example of the edge direction / clock count number storage means B220. Selector 222
At −0, the write register selection signal Mselw0, ENP indicating the rising and falling of the digital input signal DS1, and the output Dck of the clock counting means 400.
out 402 is input. In this embodiment, 2 is used as the counter block 902 in the storage unit control block 900.
Since a bit counter is used, the rising signal R
There are four registers from the storage register 223-0 to the storage register 223-3 for storing the output of the clock counting means 400 when the E or the falling signal FE is generated. The configuration of these storage registers is shown in FIG.
It is the same as FIG. 5A and FIG. Mselw0-M
By the signal of selw3, the storage registers 223-0-2
One of 23-3 is selected and the output Dckout 402 of the clock counting means 400 is stored in the selected storage register. Storage register 223-0-22
The outputs of 3-3 are connected to the count number measuring means B950 as 221-0 to 221-3. Further, the match detection signal SM and the read register selection signals Mselr0 to Ms
When elr3 is input to the 2-input ANDs 224-0 to 224-3 and the output of the 2-input AND becomes "H", VAL505 which is a bit indicating valid / invalid in the storage registers 223-0 to 223-4. Only "L" (see Figure 5)
Reset to.

FIG. 13 shows an example of the structure of the count number measuring means B950. Storage register 223-0 to 223-3
Outputs 221-0 to 221-3 are connected to a 4-input 1-output selector 880. It is the combination of DR0 and DR1 that determines the selection from these four inputs. The selected Dmout 502 is added to the output Ddelay 503 of the delay amount setting means 600 by the adder 501,
It is connected to the match detection block 701 as Dadd 504. In the match detection block 701, Dadd 504 and Dckout 402 are compared, and if they match,
The coincidence signal SM is output as "H". Match signal SM
Is connected to the match detection control block 881. The match detection control block 881 to which the match signal SM is input as "H" sets the SEL 804 to "H" during one clock cycle in synchronization with the next clock CLK, and at the same time, the (n + 1) th storage register indicating the edge direction. Bit ED
Is output as ED ′ to the selector 803. D-FF8
02 captures ED ′ while the SEL 804 is “H” and holds the captured value while the SEL 804 is “L”. At the same time, the match detection control block 881 causes the enable signal RD for counting the counter block 904.
_Buf951 is set to "H" during one clock cycle of the clock CLK.

14 and 15 are state transition diagrams of the counter block 902 and the counter block 904, respectively. The counter block 902 makes a transition to the next state when RE | FE = H, and the counter block 904 makes the RD
When _buf = H, the next transition is made. These counter blocks perform state transitions without being influenced by each other, and writing to and reading from the storage registers 223-0 to 223-3 are also performed by different paths, so that writing and reading can be performed independently. Therefore, in the case of the present embodiment, it is possible to set the delay time for the rising and falling of the digital signal DS1 up to four times in the delay amount setting means 600.

FIG. 16 is a time chart diagram according to the first embodiment. The digital input DS1 input at time t1 is the output D of the clock counting means 400.
The rising edge detection signal RE is generated when ckout is a. The Dckout at this time, a, is taken into the clock count number storage means 300. Since ED of the edge direction storage means 200 is connected to RE,
"H" is set. The delay amount b is set in the delay amount setting means 600.
If is set, the count number measuring means 500 adds a + b and compares it with Dckout. When the time tx has elapsed, the number of clocks of the clock CLK is input b times, and a match is detected. At this time, the coincidence signal SM is output and reproduced as DDS1.

FIG. 17 is a time chart diagram according to the second embodiment. The basic operation is the same as the time chart of FIG. Storage register for writing with DW of counter block 902, and counter block 90
The storage register to be read is designated by DR of 4. The delay amount x can be set within a range y in which the number of rising and falling edges of the digital input signal DS1 falls within the number of storage registers. Next, details will be described. When the digital input signal DS1 is input, the rising signal RE becomes "H" and is input to the storage means control block 900. At this time, the counter block 902 (DW1, DW
0) indicates (0, 0). If the output of the clock counting means 400 at this time is a, then Dckout =
a, and this value is written in the storage register 223-0. At the same time, (DW1, DW0) becomes (0, 1), and preparation for writing to the storage register 223-1 is possible.
It is assumed that b is set as the delay amount in the delay amount setting means 600. Also, (DR1, DR0) = (0,0)
Then, the reading from the storage register 223-0 is designated. Here, when Dckout = Dmout + b, the coincidence signal SM is output, and this signal is taken into the count number measuring means B950. In addition, Dmout
= A. Upon receiving the coincidence signal SM, the count number control means B950 sets RD_buf to "H" for one cycle of the clock CLK, and sets the D-FF 802 to the same value as ED. As a result, the signal DDS1 obtained by delaying the digital signal DS1 by b is reproduced. In this way, every time the edge of the digital input DS1 changes, RE or F
A signal is generated as E, and (DW1, D
W0) changes and the storage register to be written is 223-0 to 223
It is specified from 23-3. On the other hand, each time the coincidence signal SM is generated, the delayed signal DDS1 is reproduced by reproducing the ED stored in the bit n + 1 of the storage register based on (DR1, DR0).

[0027]

As described in detail above, by including the edge direction storage means and the storage means control block, the storage register and the coincidence detection means which have conventionally had to be provided respectively at the rising edge and the falling edge of the signal. Can be combined into one, and the scale and cost of the circuit can be suppressed. Further, by operating all the internal blocks in synchronization with the clock, the skew between the blocks becomes stronger and the design becomes easier.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of a block diagram of a digital delay circuit of the present invention.

FIG. 2 is a diagram showing an example of a block diagram of a conventional digital delay circuit.

FIG. 3 is a diagram showing a configuration of rising / falling detection means according to the present invention.

FIG. 4 is a diagram showing a configuration of clock counting means according to the present invention.

FIG. 5A is a diagram showing a configuration of edge direction storage means and clock count number storage means according to the present invention. (B) is a figure showing the information memorized in the memory register concerning the present invention.

FIG. 6 is a diagram showing a configuration of delay amount setting means according to the present invention.

FIG. 7 is a diagram showing a configuration of a count number measuring means according to the present invention.

FIG. 8 is a diagram showing a configuration of a delay amount detecting means and a digital signal reproducing means according to the present invention.

FIG. 9 is a state transition diagram of a match detection control block according to the present invention.

FIG. 10 is a diagram showing a second embodiment of the block diagram of the digital delay circuit of the present invention.

FIG. 11 is a diagram showing a configuration of a storage unit control block according to the present invention.

FIG. 12 is a diagram showing a configuration of an edge direction / clock count number storage means B according to the present invention.

FIG. 13 is a diagram showing a configuration of a count number measuring means B according to the present invention.

FIG. 14 is a state transition diagram of a write control counter block in the memory control block according to the present invention.

FIG. 15 is a state transition diagram of a read control counter block in the storage control block according to the present invention.

FIG. 16 is a timing chart diagram according to the first embodiment of the present invention.

FIG. 17 is a timing chart diagram according to the second embodiment of the present invention.

FIG. 18 is a block diagram showing mechanism control by digital control.

[Explanation of symbols]

100 Rise / fall detection means 200 Edge direction storage means 300 clock count storage means 400 clock counting means 500 count number measuring means 600 delay amount setting means 700 delay amount detecting means 800 Digital signal reproducing means

Claims (3)

[Claims] 1. A digital delay circuit for delaying a digital signal, edge detecting means for detecting a rising or falling edge of the digital signal, a clock counting means which is a free-run counter of at least 1 bit, and the edge detecting means. Clock count number storage means for storing the clock count number of the clock count means when an edge is detected, a delay amount setting means for setting the delay amount of the digital signal, and a delay set in the delay amount setting means. Count number measuring means for obtaining the sum of the amount and the clock count number stored in the clock count storage means, and a delay amount detection for detecting that the clock count numbers of the count number measuring means and the clock count means match each other. Means and the delay information based on the coincidence information from the delay amount detecting means. Digital delay circuit comprising: the digital signal reproducing means for reproducing a digital signal, a. 2. The edge direction storage means for storing the edge direction of the digital signal is further provided, and the edge direction stored in the edge direction storage means is valid based on the coincidence information from the delay amount detection means. The digital delay circuit according to claim 1, wherein invalid information is cleared. 3. The edge detection means detects a plurality of rising or falling edges of the digital signal, and the clock count number storage means detects a plurality of rising edges or falling edges of the digital signal. 3. A storage unit control block that stores a clock count number and stores the plurality of clock count numbers in a specific storage register of the clock count number storage unit. The digital delay circuit described in.