JP3345501B2 - Delay circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit for delaying a digital signal.

[0002]

2. Description of the Related Art In a digital signal data processing transmission system, when a new processing block is added, data is delayed before and after the added processing block. For example, when processing is performed on a data signal such as a spatial filter process on an image signal, the output of the data signal is delayed by the time required for the processing. Therefore, when a timing signal is attached to a data signal, the entire circuit does not operate normally unless the timing signal is output in accordance with the delay of the data signal. FIG. 2 is a configuration block diagram schematically showing the data signal processing system. The data signal processing system includes a data signal DSA and a timing signal TS.
A, a front block 10 for processing the data signal DSA and the timing signal TSA, and a rear block 30 for inputting the data signal DSB and the timing signal TSB of the processing result in the processing block 20. And Processing block 20
It has a data processing circuit 21 for processing the data signal DSA, and a timing delay circuit 22 for delaying the timing signal TSA in accordance with the delay of the data signal DSA.
Since the processing block 20 is inserted between the pre-block 10 and the post-block 30, the data signal DS
A is output as a data signal DSB delayed by the delay time required for processing in the data processing circuit 21 and input to the post-block 30. At this time, it is assumed that the format such as the data length does not change. Similarly, the timing signal TSA accompanying the data signal DSA is output from the timing delay circuit 22 with a delay of the same delay time as that of the data processing circuit 21. When viewed from the rear block 30, the relative time relationship between the data signal DSB and the timing signal TSB is the same as the time relationship between the data signal DSA and the timing signal TSA.
After the addition of 0, the post-block 30 operates normally.

In recent years, processing such as spatial processing and time axis processing in image processing tends to be complicated, and the number of processing delay stages has increased to several hundred to several 10,000 cycles. In the case of such a long delay, in the related art, a timing signal is delayed by using a memory as a delay circuit. FIG. 3 is a schematic block diagram showing an example of a conventional timing delay circuit. This delay circuit 22
A dual-port memory 23 that stores a timing signal TSA input from an input terminal ta, a write control block 24 that generates a write enable signal WE and a write address WADR of the memory 23 based on a clock CLK, a write address WADR, and an input terminal d
(Hereinafter referred to as a delay parameter) DL for setting the number of delay stages input from the memory 2 and the clock CLK
And a read control block 25 for generating a third readings out address RADR, are provided. Note that the clock CLK
It is configured to be inputted from the input terminal c to the write control block 24 and readings <br/> out control block 25. The dual port memory 23 has a write port 23a and a read port 23b. Further, the delay circuit 22
Is provided with an output terminal tb for outputting, from the output side of the memory 23, a delay signal TSB obtained by delaying the timing signal TSA by the number of cycles set by the delay parameter DL.

FIG. 4 is a time chart for explaining the operation of FIG. 3, in which the horizontal axis represents time and the vertical axis represents a logic level. The operation of FIG. 3 will be described with reference to FIG. The timing signal TSA is input to the input terminal ta in synchronization with the clock CLK. Information of all the cycles of the timing signal TSA is written to the memory 23 by the write enable signal WE and the write address WADR generated in the write control block 24. On the other hand, in the control block 25 out read, the number of cycles was set write address WADR delay parameter DL N
To generate a read of memory only began to address RADR which is delayed only. The read Shi read out <br/> from the memory 23 at the address RADR out viewed by performing a delay signal TSB which the timing signal TSA was N cycles delay is output from the output terminal 17. In the above example, a dual-port memory is used as the memory 23. However, a single-port memory or a first-in first-out memory is used.
st Out) The same can be realized with a memory or the like.

[0005]

However, the conventional delay circuit has the following problems. When the delay time due to the processing is large, there is a problem that the capacity of the memory 23 increases in proportion to the delay time, and the circuit scale becomes large. In addition, there is a problem that power consumption is large because the memory 23 is always operating. Particularly, in a large-scale integrated circuit, it is difficult to realize a delay circuit of thousands of cycles by adding a delay circuit in addition to a data processing circuit in terms of a circuit scale. SUMMARY OF THE INVENTION The present invention provides a delay circuit having a smaller circuit size than conventional ones in order to solve these problems.

[0006]

Means for Solving the Problems] To solve the above problems
In the invention according to claim 1 of the present invention, the delay circuit
The edge detection means, the time code generation means,
Storage means, a determination unit, and a reproduction means. Said d
The edge detection means generates a digital input signal for delay.
The digital input signal is captured in synchronization with the clock.
Rising edge is detected and a rising detection signal is output.
And the falling edge of the digital input signal.
Edge detection and outputs a fall detection signal.
You. The time code generation means includes a delay for setting the number of delay stages.
Input the delay parameter and the clock, and
And the number of clocks and the delay parameter
Time code corresponding to the number of clocks
Generate and output. The storage means stores
A rising detection signal, the falling detection signal, and the
Input a time code, the rising detection signal and the
Holds the time code in synchronization with the falling detection signal.
Output rise time code and fall time code
Input the rising and falling judgment signals.
The holding state is reset when
You. The determination unit is configured to determine the time code and the rising time.
Enter the fall code and the fall time code
Serial time code match with the rise time code / not
Judgment is made and when the two match, a predetermined time
Outputting the rise determination signal indicating the elapsed time;
Match / mismatch between the code and the fall time code
Judgment and when the two match, the elapse of the predetermined time
The falling edge determination signal shown in FIG. Change
The reproducing means may include the rising determination signal and the
Input the falling judgment signal, and
Regenerate the rising edge and the falling edge
The digital input signal is delayed by the predetermined time.
And outputs the delayed signal. Claim 2
3. The delay circuit of claim 1, wherein the time code
When the coincidence detection signal is input, the generation means generates a predetermined initial value.
Reset to the predetermined initial state in synchronization with the clock.
A counter that counts from the period value and outputs the time code
Data, and the match between the delay parameter and the time code /
Judge mismatch, and when both match,
A coincidence detector that outputs a detection signal and supplies the counter to the counter
And In the invention according to claim 3, claim 1
In the delay circuit of
Operates when a detection signal is input and counts the clock.
A two-bit first counter;
The count value is decoded and n (where n is a plurality) first
First decoder with two inputs and n outputs that outputs a decoded signal of
And the rising edge determination signal is input, respectively.
Reset, the time code signal and the rise detection
Outgoing signal and the first decoded signal, respectively.
And outputs the rise time codes respectively.
First registers and the falling detection signal
When it is done, it operates and counts the clock.
2 and the count value of the second counter are decoded.
To output n second decode signals.
A second decoder of the power and the falling judgment signal
Each time the signal is reset, the time code signal is reset,
The falling detection signal and the second decoding signals;
Number and enter the fall time code
And n second registers for outputting respectively.
You. In the invention according to claim 4, the delay circuit of claim 1 has
And the reproducing means comprises a flip-flop.
You.

[0007]

According to the first to fourth aspects of the present invention , since the delay circuit is configured as described above, the digital input signal is
Input to the digital detection means, the digital input signal
A rising edge and a falling edge are detected.
On the other hand, the clock input by the time code generation means
Time codes corresponding to the numbers are sequentially generated. Rise
When an edge or falling edge is detected,
Is stored in the storage means. Retain in storage means
Time code and time code generation means
The match with the time code to be generated is
When the elapse of the fixed time is detected (that is, a predetermined delay).
The same time code is reached again after the number of stages
Time), a judgment signal is output from the judgment unit and the reproduction means
Given to. Then, by the playback means,
Edge and falling edge are reproduced and digital input
A delayed signal obtained by delaying the signal by a predetermined time is output.

[0008]

FIG. 1 is a schematic block diagram showing a delay circuit according to an embodiment of the present invention. Delay circuit of this embodiment, the retarded
Timing signal, which is a digital input signal to extend
The provided edge detection block 40 for detecting the TS edge timing signal TS in the edge detection block 40
Are detected, the register blocks 60, 7
The time code TC at that time is stored in 0, and after the time corresponding to the number of delay stages set in advance elapses, the same time code TC is again used.
In this case, the edge is reproduced to obtain the delay signal TSDL of the timing signal TS , thereby reducing the circuit scale as compared with the related art. That is, this delay circuit has an input terminal ti for inputting a timing signal TS as a delay target signal, an input terminal d for inputting a delay parameter DL for setting the number of delay stages, and an input terminal c for inputting a clock CLK. are doing. The input terminal ti and the input terminal c are
The input terminal c and the input terminal d are connected to the edge detection block 40, and are connected to the time code generation block 50. The edge detection block 40 detects an edge of the timing signal TS from the input terminal ti based on the clock CLK, and detects a rising detection signal REI indicating a rising edge of the timing signal TS and a timing signal TS.
Edge detecting means for generating a falling detection signal FEI indicating the falling edge of the signal. The time code generation block 50 determines the delay parameter DL based on the clock CLK.
Is a time code generating means for generating a time code TC set by the following.

The output side of the edge detection block 40 is connected to a register block 60 and a register block 70, respectively. The output side of the time code generation block 50 is connected to the register block 60 and the register block 70. The register block 60 is a storage unit that holds the time code TC in synchronization with the rising detection signal REI, and the register block 70 is a storage unit that holds the time code TC in synchronization with the falling detection signal FEI. Each output side of the register block 60 and the register block 70 is provided with a match determination block 8 serving as a determination unit.
0 and the match determination block 90, respectively. Further, the output side of the time code generation block 50 is also connected to the match determination block 80 and the match determination block 90. Each output side of the coincidence determination block 80 and the coincidence determination block 90 is feedback-connected to the register block 60 and the register block 70, respectively. The coincidence determination block 80 includes the rising time codes REC0 to REC0 output from the register block 60 and the time code TC.
This is a connection for detecting a match / mismatch with the register block and resetting the register block 60 based on the detection result. The match determination block 90 is a connection for detecting a match / mismatch between the fall time codes FEC0 to FEC0 output from the register block 70 and the time code TC, and resetting the register block 70 based on the detection result. The match determination block 80 and the match determination block 90 are connected to the input terminals J and K of the JK flip-flop 100, respectively. The input terminal c is connected to the JK flip-flop 100. JK flip-flop 10
0 inputs the rising determination signal REO output from the matching determination block 80 and the falling determination signal FEO output from the matching determination block 90, and outputs the clock CLK
Signal TS obtained by delaying timing signal TS based on
It is a reproducing means for outputting a DL.

FIG. 5 shows an edge detection block 40 in FIG.
1 is a schematic configuration block diagram illustrating one configuration example. The edge detection block 40 includes a delay flip-flop (hereinafter, referred to as D-FF) 41, a two-input AND gate 42, and a two-input NOR gate 43. D-FF41
Is an output signal S4 which takes in the timing signal TS in synchronization with the clock CLK, delays it by one cycle, and inverts it.
1 is output. The timing signal TS is input to one input terminal of the AND gate 42, and the output signal S41 is input to the other input terminal.
The timing signal TS is input to one input terminal of the NOR gate 43, and the output signal S4 is input to the other input terminal.
1 is input. The AND gate 42 receives the timing signal TS and the output signal S41 and receives a high level signal (hereinafter, referred to as a rising edge) of the timing signal TS.
This is a means for generating a rising detection signal REI which becomes “H”. The NOR gate 43 receives the timing signal TS and the output signal S41 and receives the timing signal TS.
Is a means for generating a falling detection signal FEI which becomes "H" at the falling edge of "."

FIG. 6 is a schematic block diagram showing a configuration example of the time code generation block 50 in FIG. The time code generation block 50 counts from the initial value “1” in synchronization with the clock CLK, and the time code T
A counter 51 for generating C is provided. Counter 51
Is connected to one input side of a two-input coincidence detector 52. The delay parameter DL is input to the other input side of the coincidence detector 52. Match detector 5
The output side of 2 is connected to the counter 51. The coincidence detector 52 outputs “H” when the delay parameter DL and the time code TC coincide, and the counter 51 starts counting from the initial value “1” again. Therefore, the bit width of the counter 51 needs to be larger than the value set by the delay parameter DL.

FIG. 7 is a schematic block diagram showing an example of the register block 60 in FIG. This configuration block diagram assumes a case where the number of rising edges of the timing signal TS is four or less within the delay time. The register block 60 includes a first counter 61 having an enable input terminal EN.
Is a 2-bit counter that counts in synchronization with the clock CLK when the rising detection signal REI from the edge detection block 40 is input from the enable input terminal EN. The output side of the counter 61 has two inputs and four outputs.
It is connected to the input side of the first decoder 62. The decoder 62 decodes the output signal S61 of the counter 61 to obtain n (for example, four) first decode signals SEL0.
To SEL3. The four decode signals SEL0 to SEL3 of the decoder 62 correspond to the n first signals.
Registers (for example, four first register circuits )
6, respectively. Each of the register circuits 63 to 66 includes a time code TC output from the time code generation block 50, a rising detection signal REI output from the edge detection block 40, and the decoder 6.
2 to generate the rise time codes REC0 to REC3, respectively. Similarly, the register block 70 has a first counter, a second decoder,
And n second registers (eg, four second registers)
) , With the following differences. That is, the rising detection signal REI in the register block 60 becomes the falling detection signal FEI, and the rising detection signal REI becomes the falling detection signal FEI. Further, the rise time codes REC0 to REC3 in the register block 60 are set to fall time codes FEC0 to FEC0.
3 and the rise determination signals REO0 to REO3 are the fall determination signals FEO0 to FEO3. In FIG. 7, R, FEI, etc. are indicated by REI or FEI.
Represents

FIG. 8 shows each of the register circuits 63 to 6 in FIG.
6 is a schematic configuration block diagram showing one configuration example of FIG. Each of the register circuits 63 to 66 has a two-input AND gate 67 and a D
-FF 68 and its AND gate 67
Receives the rise detection signal REI or the fall detection signal FEI and the decode signals SEL0 to SEL3, generates an output signal S67, and supplies the output signal S67 to the D-FF 68.
The D-FF 68 receives the time code TC by inputting the output signal S67 as a clock, and generates rise time codes REC0 to REC3 or fall time codes FEC0 to FEC3. Further, the D-FF 68 is reset by a rise determination signal REO0 to REO3 or a fall determination signal FEO0 to FEO3. In FIG. 8, R, FEI and the like are indicated by R
Indicates EI or FEI. That is, in the circuit included in the register block 60, the initial character is only the symbol of R. or,
In the circuits included in the register block 70, the initials are F
Symbol only.

FIG. 9 is a schematic block diagram showing an example of the configuration of the coincidence determination block 80 in FIG. 1. As in FIG. 7, the number of rising edges of the timing signal TS within the delay time is four. It is assumed that it is within. This coincidence determination block 80 is provided for each rise time code REC.
When the time code TC coincides with the time code 0 to 3, there are coincidence detectors 81 to 84 which output respective coincidence detection signals REO <b> 0 to 3. Each output side of the coincidence detectors 81 to 84 is connected to each input terminal of a 4-input OR gate 85. The OR gate 85 is a circuit that receives the match detection signals REO0 to REO3 and outputs a rise determination signal REO. Each of the coincidence detection signals REO0-3 is fed back to the register block 60 to reset the register block 60. The match determination block 90 is also the match determination block 8
The configuration is the same as that of 0, except for the following. That is, the rise time codes REC0 to REC3 in the coincidence determination block 80 are set to fall time codes FEC0 to FEC3.
And the coincidence detection signals REO0 to REO3 become coincidence detection signals FE.
O0-3. Further, the rising determination signal RE
O is the falling determination signal FEO. In FIG. 9, indications such as R and FEI indicate REI or FEI.

FIG. 10 is a time chart for explaining the operation of FIG. 1, in which the horizontal axis represents time and the vertical axis represents a logic level. The operation of FIG. 1 will be described with reference to FIG.
For simplicity, it is assumed that a rising edge and a falling edge each occur only once within the delay time. In the edge detection block 40, the timing signal TS
, The rising edge and the falling edge are detected, and at that time, the rising edge detection signal REI or the falling edge detection signal FEI is output as “H”. On the other hand, the time code generation block 50 creates and outputs a time code TC having one cycle with the number of cycles N given by the delay parameter DL based on the clock CLK. In the present embodiment, the time code TC is a signal in which 1 to N are defined as one cycle and are repeated. In FIG. 10, the rising detection signal R
When EI is "H", the value of the time code TC is "a", and this value "a" is stored in the register block 60,
Time code T as rise time codes REC0-REC
The value "a" of C is output. Similarly, when the falling detection signal FEI is “H”, the value of the time code TC is “b”.
The value “b” is stored in the register block 70, and the time code T is used as the fall time code FEC0.
The value "b" of C is output. These time codes “a” and “b” are held until the time code TC makes one round.

Here, register blocks 60 and 7 in FIG.
0 and the operation of the register circuit of FIG. 8 will be described. The counter 61 performs a counting operation when the rising detection signal REI or the falling detection signal FEI input to the enable terminal EN becomes “H”. Further, since the counter 61 is a 2-bit counter, the counting operation in the range of 0 to 3 is repeated. The decoder 62 decodes the output signal S61 of the counter 61, and one of the decode signals SEL0 to SEL3 is at "H" and the others are at low level (hereinafter, referred to as "L"). Assuming that the output signal of the counter 61 is 0 in the initial state, the decode signal SE
In L0 to SEL3, SEL0 becomes “H” and SEL1
SEL3 becomes “L”. Since the clock CLK input to the D-FF 68 in FIG. 8 is the output signal S67 of the AND gate 67, the decode signal SEL of the decoder 62
When both 0 to SEL3 and the rising detection signal REI or the falling detection signal FEI are both "H", the time code TC is held in the D-FF 68. Therefore, the decode output SEL0 becomes “H” and the rising detection signal R
When the EI or the falling detection signal FEI becomes “H”,
The time code TC at this time is written in the register circuit 63. When the rise detection signal REI or the fall detection signal FEI becomes “H”, the counter 61 performs a count operation, and the output signal S61 becomes “1”. Therefore, the decode signal S of the decoder 62
EL1 becomes “H” and the remaining decode signals SEL0, SEL0,
SEL2 and SEL3 become "L" and wait. Again, the rise detection signal REI or the fall detection signal FEI
Becomes "H", the time code TC at this time is held in the register circuit 64, the count operation is performed, and the state becomes a standby state. Since the counter 61 has 2 bits, the rising detection signal REI or the falling detection signal FEI is set to “H”.
Is input four times, the first register circuit 63 enters a state where the time code TC is written and waits. Therefore, when the rising detection signal REI or the falling detection signal FEI becomes “H” more than five times within the delay cycle set by the delay parameter DL, the register circuit 63 in which the first time code TC is written corresponds to the fifth time. The time code TC is overwritten, and the change information written first is lost. Therefore, in FIG. 7, the number of rising edges and the number of falling edges within the delay time are each limited to four or less. The time code TC held in the register circuits 63 to 66 is held until the coincidence detection signals REO0 to FEO3 and FEO0 to FEO3 set by the delay parameter DL are input, and the rise time codes REC0 to REC3 or the fall time code FEC0 ３3 continue to be output. When the match detection signals REO0-3 and FEO0-3 are input after the time set by the delay parameter DL elapses,
The contents of the register circuits 63 to 66 corresponding to these are reset, and the rise time codes REC0 to REC3 or the fall time codes FEC0 to FEC3 become "0".

Returning to the description of the time chart of FIG. When N cycles elapse after the timing signal TS first rises, the time code TC from the time code generation block 50 takes the value "a" again. At this time,
Since the rise time code REC0 and the time code TC match, the rise determination signal REO of the match determination block 80 becomes “H”. Similarly, the timing signal TS
When N cycles have passed since the first fall, the time code TC from the time code generation block 50 takes on the value "b" again. At this time, since the fall time code FEC0 and the time code TC match, the fall determination signal FEO of the match determination block 90 becomes “H”. Therefore, the rising determination signal REO and the falling determination signal FEO are signals delayed by N cycles from the rising detection signal REI and the falling detection signal FEI, respectively. When the rise determination signal REO and the fall determination signal FEO are output, the register blocks 60 and 70 are reset and the rise time code R
EC0 and the fall time code FEC0 become "0" to prepare for the input of the next rise detection signal REI and fall detection signal FEI.

Next, by inputting the rise determination signal REO and the fall determination signal FEO to the input terminals J and K of the JK flip-flop 100, respectively, the delay signal TSDL obtained by delaying the timing signal TS by (N + 1) cycles is obtained. And output from the output terminal td. In this configuration, (the number of cycles set by the delay parameter DL + 1)
A cycle delay occurs. When delaying the timing signal TS by N cycles, the delay parameter DL given to the input terminal d may be set to (N-1) cycles. FIG.
FIG. 4 is a correlation diagram showing the result of comparing the circuit scales of the delay circuit of the present embodiment shown in FIG. 1 and the conventional delay circuit shown in FIG. 3, where the horizontal axis indicates the number of delay stages and the vertical axis indicates the circuit scale. ing.
In the conventional circuit shown in FIG. 3, the number of signal edges within the delay time is the same as the maximum number of delay stages. For example, when the number of delay stages is 64 (= 2 ⁶ ), the number of edges is also 64 (=
²⁶ ). As the number of delay stages increases and the number of edges decreases, the circuit scale of the present embodiment is smaller than that of the related art. In this embodiment , the increase in the scale of the circuit is more gradual than the increase in the number of delay stages compared to the prior art. With the point F as a boundary, the present embodiment has a smaller circuit scale. Further, in this embodiment , the circuit scale depends on the number of edges rather than the number of delay stages.

As described above, in this embodiment, as the number of delay stages increases and the number of edges decreases, the circuit scale of this embodiment becomes smaller than that of the prior art. Furthermore, in the present embodiment, the increase in the circuit scale with respect to the increase in the number of delay stages is more gradual than in the prior art, and the boundary between the point where the ratio of the number of edges to the number of delay stages becomes approximately 1/256 is defined as In this embodiment, the circuit size can be reduced. Also, in this embodiment,
The circuit scale depends on the number of edges rather than the number of delay stages. In particular, when dealing with an image signal, the rate of change of the timing signal is often once per line, for example, once per 858 cycles. Therefore, in a delay circuit of several lines,
The number of edges is reduced to several thousandths compared to the delay time, and by storing only the input information of the edges, the input can be performed with a smaller storage capacity than in the conventional case where all the input information is stored. The signal can be stored. Furthermore, the real
In the embodiment, the rising of the input timing signal TS
Edge and falling edge are detected by the edge detection block 40.
When detected and output from the time code generation block 50
The intercode TC (ie, the time information at each edge)
Information) in the register blocks 60 and 70.
ing. Therefore, when there are multiple edges during the delay time,
Even if the time code is the time information of each edge
Since TC is held in the register blocks 60 and 70,
Delay signal with the same waveform as the original timing signal TC
No. TSDL can be generated. The present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications. In the configuration examples of the register blocks 60 and 70 shown in FIG. 7 and the match determination blocks 80 and 90 shown in FIG. 9, it is assumed that the rising edge and the falling edge of the timing signal TS are four or less within the delay time. . If there is only one edge, the counter 61, the decoder 62, and the AND gate 67 in the register circuits 63 to 66 in FIG. Conversely, when the number of edges is large, it can be dealt with by increasing the number of bits of the counter 61 and the number of register circuits 63 to 66. In FIG. 9, the coincidence detectors 81 to 84 are used.
And the number of inputs of the OR gate 85 can be changed.

[0020]

As described in detail above, claims 1 to 5
According to the fourth aspect, the rising of the digital input signal is
Edge and falling edge are detected by edge detection means
And store the time code, which is the time information at that time, in the storage means.
Hold, and after the time corresponding to the preset number of delay stages elapses,
And when the same time code is reached,
Digital input by reproducing edge and falling edge
The signal delay signal is output, so the conventional delay
The delay circuit can be realized on a smaller scale than the circuit ,
Also does not use a conventional memory, so that it consumes less power. In particular, it is disadvantageous in terms of circuit size and cost to configure a delay circuit with a memory corresponding to the processing of thousands of cycles in addition to a data processing circuit on a large-scale integrated circuit. Then it can be easily realized. And the book
According to the invention, the rising edge of the digital input signal is
The falling edge is detected by the edge detection means and the time code
The time code output from the generator (ie, each
Time information at the edge) in the storage means
are doing. Therefore, there are multiple edges during the delay time
Even if the time code is the time information of each edge,
The digital input signal is stored in the storage means.
A delayed signal can be generated with the same waveform as the signal.

[Brief description of the drawings]

FIG. 1 is a schematic configuration block diagram of a delay circuit showing an embodiment of the present invention.

FIG. 2 is a schematic block diagram of a data signal processing system.

FIG. 3 is a schematic block diagram of a conventional timing delay circuit.

FIG. 4 is a time chart for explaining the operation of FIG. 3;

FIG. 5 is a schematic configuration block diagram of an edge detection block in FIG. 1;

FIG. 6 is a schematic configuration block diagram of a time code generation block in FIG. 1;

FIG. 7 is a schematic configuration block diagram of a register block in FIG. 1;

8 is a schematic configuration block diagram of a register circuit in FIG. 7;

FIG. 9 is a schematic configuration block diagram of a match determination block in FIG. 1;

FIG. 10 is a time chart for explaining the operation of FIG. 1;

11 is a correlation diagram comparing the circuit scales of the delay circuit of FIG. 1 and the delay circuit of FIG. 3;

[Explanation of symbols]

40 edge detection block 50 time code generation block 60,70 register block 80,90 coincidence determination block 100 JK flip-flop

Claims (4)

(57) [Claims] 1. A digital input signal for delaying
Captures in synchronization with lock
Detect rising edge and output rising detection signal
The falling edge of the digital input signal.
Edge detection that detects edge and outputs falling detection signal
Means, a delay parameter for setting the number of delay stages, and the clock.
Input, count the number of clocks, and
Corresponds to the number of clocks based on the delay parameter
Time code generation that sequentially generates and outputs the time code
Means, the rise detection signal, the fall detection signal, and
And the time code.
And the time code in synchronization with the falling detection signal.
Hold the rise time code and fall time code
Output, and the rise judgment signal and the fall judgment signal are output.
When the signal is input, the storage state is reset.
Means, the time code, the rise time code, and
Enter the fall time code, and enter the time code and the
Judgment of match / mismatch with rise time code
When they match, the above-mentioned stand indicating the lapse of a predetermined time has elapsed.
Outputs the rise judgment signal, and the time code and the fall
Judgment of coincidence / non-coincidence with the time code
When coincident, the falling indicating the lapse of a predetermined time
A determination unit that outputs a determination signal, the rising determination signal and the falling determination signal
The rising edge and the
And the falling edge, and
Output a delay signal obtained by delaying the force signal by the predetermined time.
And a reproducing means . 2. The time code generation means resets to a predetermined initial value when a coincidence detection signal is input.
Counting from the predetermined initial value in synchronization with the clock.
And a counter for outputting the time code, and matching / mismatch between the delay parameter and the time code
And when they match, the match detection signal
2. A delay circuit according to claim 1 , further comprising: a coincidence detector for outputting a signal to the counter . 3. The storage means operates when the rising detection signal is input and operates when the rising edge detection signal is input.
A 2-bit first counter for counting locks, and decoding the count value of the first counter to n (where
And a plurality of (n; plural) output first decode signals.
The first decoder having a power n output and the rising edge determination signal are respectively reset to be reset.
The time code signal and the rising edge detection signal.
And the first decode signal, respectively.
N output of each of the rise time codes
The first register operates when the falling detection signal is input, and operates when the falling edge detection signal is input.
A 2-bit second counter for counting locks, and n second second counters for decoding the count value of the second counter.
2 input / n output second decoder that outputs a decoded signal of
And the falling judgment signal are reset, respectively.
The time code signal and the falling detection signal.
And the second decode signal, respectively.
N output of each of the fall time codes
2. The delay circuit according to claim 1 , further comprising a second register . 4. The reproducing means comprises a flip-flop.
2. The delay circuit according to claim 1, wherein the delay circuit is implemented.