CN116760985A - Video input circuit of DSC encoder, DSC encoder system and video input method - Google Patents

Video input circuit of DSC encoder, DSC encoder system and video input method Download PDF

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Publication number
CN116760985A
CN116760985A CN202310812350.7A CN202310812350A CN116760985A CN 116760985 A CN116760985 A CN 116760985A CN 202310812350 A CN202310812350 A CN 202310812350A CN 116760985 A CN116760985 A CN 116760985A
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pixel
clock
data
module
sampling
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王非
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Beijing Jirui Zhiyuan Technology Co ltd
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Beijing Jirui Zhiyuan Technology Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
    • H04N19/136—Incoming video signal characteristics or properties
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/65—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using error resilience
    • H04N19/68—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using error resilience involving the insertion of resynchronisation markers into the bitstream
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/85—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression

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  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)

Abstract

The present invention relates to the technical field of DSC encoders, and in particular, to a video input circuit of a DSC encoder, a DSC encoder system, and a video input method. The circuit comprises a prime packaging module and a synchronous clock sampling module; the pixel packaging module is used for generating a data packet every three beats of pixel clocks, and the data width of each data packet is three pixel data; the synchronous clock sampling module is used for generating one third of pixel clock signals based on the clock signals of the pixel clock domains and the frequency relation between one third of pixel clock domains and the pixel clock domains so as to directly sample the data packet generated by the pixel packing module by utilizing one third of pixel clock signals, and storing the sampled data packet on a sampling register of the synchronous clock sampling module so as to output the sampled data packet to the DSC encoder. Compared with the traditional asynchronous FIFO, the synchronous clock sampling module of the scheme omits a read-write pointer and combinational logic, reduces the use of a register, and can save the chip area and the chip cost.

Description

Video input circuit of DSC encoder, DSC encoder system and video input method
Technical Field
The embodiment of the invention relates to the technical field of DSC encoders, in particular to a video input circuit of a DSC encoder, a DSC encoder system and a video input method.
Background
Since an encoder of DSC (display stream compression) generally operates in one third of a pixel clock domain, one clock processes 3 pixels, and video image data input to the DSC encoder generally operates in the pixel clock domain, i.e., one clock outputs 1 pixel, 1 video input circuit is generally designed in front of the DSC encoder to complete the clock domain conversion work.
However, the video input circuit of the existing DSC encoder typically uses an asynchronous FIFO (first in first out data buffer) to complete the conversion of video data from the pixel clock domain to one third of the pixel clock domain. To reduce the probability of metastability, asynchronous FIFOs typically have multiple depth registers configured to slow down the rate of register change, thereby reducing the probability of reading erroneous data as the registers change, which requires more registers and combinational logic, resulting in a larger chip area and chip cost for the video input circuitry of existing DSC encoders.
Therefore, a new video input circuit of DSC encoder is needed.
Disclosure of Invention
In order to solve the problems of large chip area and large chip cost required by a video input circuit of an existing DSC encoder, the embodiment of the invention provides the video input circuit of the DSC encoder, a DSC encoder system and a video input method.
In a first aspect, an embodiment of the present invention provides a video input circuit of a DSC encoder, including:
the pixel packaging module and the synchronous clock sampling module; wherein,,
the pixel packing module is connected between the synchronous clock sampling module and an external video data input device; the video data input device works in a pixel clock domain and is used for outputting pixel data to the pixel packing module under each beat of pixel clock; the pixel packing module works in the pixel clock domain and is used for generating a data packet every three beats of pixel clocks, and the data width of each data packet is three pixel data;
the synchronous clock sampling module is connected between the pixel packing module and the DSC encoder, and is used for generating one third of pixel clock signals based on the clock signals of the pixel clock domains and the frequency relation between one third of pixel clock domains and the pixel clock domains so as to directly sample the data packet generated by the pixel packing module by utilizing the one third of pixel clock signals, and storing the sampled data packet on a sampling register of the synchronous clock sampling module so as to output the data packet to the DSC encoder; wherein the number of the sampling registers is 1.
In a second aspect, an embodiment of the present invention further provides a DSC encoder system, including: a video data input unit, a DSC encoder, a DSC output module, and a video input circuit as described in any one of the embodiments of the present specification;
the video data input device is connected with the input end of the video input circuit and is used for outputting one pixel data to the video input circuit under each beat of pixel clock;
the DSC encoder is connected with the output end of the video input circuit and is used for encoding the video data output by the video input circuit;
the DSC output module is connected with the DSC encoder and is used for performing clock domain conversion on the encoded data output by the DSC encoder.
In a third aspect, an embodiment of the present invention further provides a video input method based on the video input circuit described in any one embodiment of the present specification, including:
the method comprises the steps of packaging pixel data input by a video data input unit every three beats of pixel clocks by using a pixel packaging module, and generating a plurality of data packets with data width of three pixel data;
the synchronous clock sampling module generates one third of pixel clock signals based on clock signals of a pixel clock domain and frequency relations between one third of pixel clock domains and the pixel clock domain, so that one third of pixel clock signals are utilized to directly sample the data packet generated by the pixel packing module, and the sampled data packet is stored in a sampling register of the synchronous clock sampling module to be output to the DSC encoder; wherein the number of the sampling registers is 1.
The embodiment of the invention provides a video input circuit of a DSC encoder, a DSC encoder system and a video input method, wherein the circuit comprises the following components: the pixel packaging module and the synchronous clock sampling module; firstly, a pixel packing module is used for packing pixel data input by every third pixel clock of a video data input device to generate a plurality of data packets with data width of three pixel data, then a synchronous clock sampling module is used for generating a third pixel clock signal according to clock signals of a pixel clock domain and frequency relations between the third pixel clock domain and the pixel clock domain, the third pixel clock signal can be used for directly sampling the data packets generated by the pixel packing module in the pixel clock domain, and as the third pixel clock signal and the clock signals of the pixel clock domain are the same clock source, the metastable state can be avoided as long as the frequency relations between the third pixel clock signal and the pixel clock signal are kept unchanged strictly, the synchronous clock sampling module only needs to be provided with 1 sampling register to store the sampling data of one third pixel clock of each beat, so that the sampling data can be output to a DSC encoder in each beat. Therefore, compared with the asynchronous FIFO used by the traditional video input circuit, the synchronous clock sampling module omits the asynchronous FIFO read-write pointer and the combination logic, and reduces the use of registers, so that a large amount of chip area can be saved by the scheme, and the chip cost and the power consumption can be saved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of the composition of a video input circuit of a DSC encoder of the prior art;
FIG. 2 is a schematic waveform diagram of a video input circuit of a DSC encoder of the prior art;
FIG. 3 is a prior art memory schematic of an asynchronous FIFO;
fig. 4 is a schematic diagram illustrating a video input circuit of a DSC encoder according to an embodiment of the present invention;
FIG. 5 is a schematic waveform diagram of a pixel packing module according to an embodiment of the present invention;
FIG. 6 is a schematic waveform diagram of a video input circuit of a DSC encoder according to an embodiment of the present invention;
FIG. 7 is a schematic waveform diagram of a video input circuit of another DSC encoder according to an embodiment of the present invention;
FIG. 8 is a schematic waveform diagram of a video input circuit of yet another DSC encoder provided in accordance with an embodiment of the present invention;
fig. 9 is a flowchart of a video input method according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments, and all other embodiments obtained by those skilled in the art without making any inventive effort based on the embodiments of the present invention are within the scope of protection of the present invention.
As shown in fig. 1, the video input circuit of the existing DSC encoder generally includes a pixel packing module and an asynchronous FIFO, and the pixel packing module includes a video receiving unit and a packing unit. Referring to the waveform diagram of fig. 2, pixel_clock is a pixel clock, pixel_data receives pixel data from one video data input unit at each beat of pixel_clock, and transfers each received pixel data to a packetizing unit, pixel_data_en is a received video data valid indication, and pixel_data is valid only when pixel_data_en is high. The pixel_data_3p and pixel_data_en_3p are the outputs of the packing units and are also inputs to the asynchronous FIFO. Here also pixel_data_3p and pixel_data_en_3p operate in the pixel clock domain. The data width of pixel_data_3p is three times that of pixel_data, and only 3 pixels are output at the third beat clock of every 3 beats of pixel clocks. The pixel_data_en_3p is an indication signal that the pixel_data_3p is valid, and when the pixel_data_en_3p is high, it means that the pixel_data_3p data is valid.
The asynchronous FIFO is a video data clock domain conversion module of the video input circuit of a conventional DSC encoder. The input port of the asynchronous FIFO, namely the writing port, works in the pixel clock domain, the writing clock of the input port of the asynchronous FIFO is connected with the pixel clock, the writing data port of the input port of the asynchronous FIFO is connected with the pixel_data_3p signal, and the writing effective port of the input port of the asynchronous FIFO is connected with the pixel_data_en_3p signal. DSC _pixel_clock in fig. 2 is one third pixel clock, it connects the read clock of asynchronous FIFO output port, DSC _pixel_data is the read video data of asynchronous FIFO output port, it works in one third pixel clock domain, one beat clock can output 3 pixels, DSC _data_en is the data valid indication signal of asynchronous FIFO output video data DSC _pixel_data, also works in one third pixel clock domain, DSC _pixel_data and DSC _data_en are simultaneously as the output signal of video input circuit to connect the input of DSC encoder, provide video data to be encoded for DSC encoder.
Typically, two clock domain signals are accessed into the asynchronous FIFO, one is a pixel clock domain and the other is a third pixel clock domain, and since these two clock domain signals may not be homologous clocks, the DSC encoder is likely to sample data in metastable state due to clock errors or error accumulation, i.e. read data when registers change, so that multiple depth registers need to be set to buffer data packets, so as to reduce the probability of metastable state occurrence.
For example, each beat dsc _pixel_data is sequentially stored in the registers of the asynchronous FIFO in output order, as shown in fig. 3, the asynchronous FIFO has 8 depth registers, the data packets pixel0,1,2 and pixel3,4,5 are respectively written into the register 0 and the register 1, until the data packet is written into the register 7, and then the register 0 is rewritten to cover the video data originally stored in the register 0, and similarly, the read data is read from the beginning after the read round, so that the asynchronous FIFO configured with the multi-depth registers can delay the change of the registers. The original 1-beat clock is written once, namely, the 1-beat clock of the data in the register is changed once. By writing 1 turn, the clock of 8 beats of data in each register is changed once, so that the register changes slowly, and reading when the register changes can be avoided.
Therefore, the conventional video input circuit uses an asynchronous FIFO to complete the conversion of video data from the pixel clock domain to one third of the pixel clock domain, in order to reduce the probability of occurrence of metastability, the asynchronous FIFO is generally configured with a plurality of deep registers to delay the change speed of the registers, thereby reducing the probability of reading out error data when the registers change, but at this time, the asynchronous FIFO needs more registers and combinational logic, which results in larger chip area and chip cost required by the video input circuit of the conventional DSC encoder.
In order to solve the above technical problem, the inventor can consider that one third of the pixel clock signal is generated based on the clock signal of the pixel clock domain, keep the frequency of the one third of the pixel clock signal to be one third of the pixel clock signal, and can accurately control the DSC encoder to read out data without changing the sampling register, so that multiple depth registers and control logic of the asynchronous FIFO are not needed to be used for buffering the data packet, and at the moment, one third of the pixel clock signal can be used for directly sampling the data packet generated by the pixel packing module, and the sampled data packet is stored in the unique sampling register of the synchronous clock sampling module. According to the scheme, the asynchronous FIFO is replaced by the synchronous clock sampling module, the pixel packing module is properly modified, the synchronous clock sampling module is very simple to internally realize, the asynchronous FIFO is far less complex in logic, and 3 pixel width data under a pixel clock domain are directly sampled by using one third of pixel clock signals. Taking a single pixel with a width of 24 bits as an example, the synchronous clock module only downsamples 3 pixels in each one third pixel clock signal, and uses 1 beat of sampling register buffer for the 3 pixels, namely, only 1×3×24=72 bits of sampling register storage space, and the depth of the asynchronous FIFO is usually set to 8, then the memory unit required by the asynchronous FIFO is 8×3×24=576 bits of register storage space, and the read-write pointer and the control logic in the asynchronous FIFO also need a large number of registers and combination logic, so that the chip area, the chip cost and the power consumption of the video input circuit can be greatly reduced.
Referring to fig. 4, an embodiment of the present invention provides a video input circuit of a DSC encoder, which includes: the pixel packaging module and the synchronous clock sampling module; wherein,,
the pixel packing module is connected between the synchronous clock sampling module and an external video data input device; the video data input device works in a pixel clock domain and is used for outputting pixel data to the pixel packing module under each beat of pixel clock; the pixel packaging module works in a pixel clock domain and is used for generating a data packet every three beats of pixel clocks, and the data width of each data packet is three pixel data;
the synchronous clock sampling module is connected between the pixel packing module and the DSC encoder, and is used for generating one third of pixel clock signals based on the clock signals of the pixel clock domains and the frequency relation between one third of pixel clock domains and the pixel clock domains so as to directly sample the data packet generated by the pixel packing module by utilizing one third of pixel clock signals, and storing the data packet obtained by sampling on a sampling register of the synchronous clock sampling module so as to output the data packet to the DSC encoder; wherein the number of sampling registers is 1.
In the embodiment of the invention, firstly, the pixel data input by the video data input unit in every three beats of pixel clocks is packed by the pixel packing module to generate a plurality of data packets with the data width of three pixel data, and then, one third of pixel clock signals are generated by the synchronous clock sampling module according to the clock signals of the pixel clock domains and the frequency relation between one third of pixel clock domains and the pixel clock domains, so that the data packets generated by the pixel packing module in the pixel clock domains can be directly sampled by the one third of pixel clock signals. Compared with the asynchronous FIFO used by the traditional video input circuit, the synchronous clock sampling module omits the asynchronous FIFO read-write pointer and the combination logic, and reduces the use of registers, so that the invention can save a large amount of chip area, thereby saving the chip cost and the power consumption.
In some embodiments, the pixel packing module is specifically configured to store three pixel data input by the video data input unit every three beats of pixel clock in a register with a width of three pixels, so as to output a data packet; meanwhile, a first indication signal indicating that the data packet is valid is output every beat of pixel clock after the start of the packing of the pixel data.
In this embodiment, the waveform diagram may be output by referring to the pixel packing module of fig. 5, where pixel_data_en is the first indication signal and pixel_data is the data packet, and compared with pixel_data and pixel_data_3p data in fig. 2, the pixel packing module of this embodiment directly stores three pixel data input by the video data input unit in a register with three pixel widths, and generates the data packet, where the data packet is valid under the three beats of pixel clocks, so that the synchronous clock sampling module may perform synchronous acquisition on the pixel data stored preferentially in the process of generating the data packet, and it is not necessary to send the write enable signal to the asynchronous FIFO after the pixel packing module needs to generate the data packet like that shown in fig. 2. In addition, the pixel packing module of fig. 2 stores each pixel data input by the video data input unit by using the video receiving unit, and then packs each three pixel data into a data packet by using the packing unit when the pixel clock is last shot, and the pixel packing module of this embodiment does not need the video receiving unit, and directly writes each three pixel data on a register with three pixel widths, so the pixel packing module of this embodiment omits the combination logic of the video receiving unit and a plurality of registers with single pixel width, and reduces the chip area and the chip cost.
In some embodiments, the synchronous clock sampling module comprises: a counting clock unit and a synchronous sampling unit;
the counting clock unit is connected with the pixel clock and used for counting the received clock signals, and each three beats of clock signals are used as one third of pixel clock signals to be output to the synchronous sampling unit;
the input end of the synchronous sampling unit is connected with the pixel packing module and the counting clock unit, the output end of the synchronous sampling unit is connected with the DSC encoder, and the synchronous sampling unit is used for sampling the data packet output by the pixel packing module based on one third of the pixel clock signal output by the counting clock unit and the first indication signal output by the pixel packing module, and storing the sampled data packet on the sampling register for outputting to the DSC encoder; meanwhile, each beat of pixel clock after the data packet output by the pixel packing module is sampled outputs a second indication signal for indicating that the video data on the sampling register is valid.
In this embodiment, the count clock unit counts the received clock signals, and outputs each three beats of clock signals as one third of the pixel clock signals to the synchronous sampling unit, so that the synchronous sampling unit samples the data packet generated by the pixel packing module according to the one third of the pixel clock signals and the first indication signal, and generates the second indication signal.
In addition, the third pixel clock used by the DSC encoder and the third pixel clock of the synchronous clock sampling module are one clock source, and it is understood that the counting clock unit of the clock sampling module simultaneously transmits the generated third pixel clock signal to the DSC encoder as the working clock of the DSC encoder.
In this embodiment, the counter mode is used to generate a third of the pixel clock signal which is the same source clock as the pixel clock domain, and the logic of the counter mode is simpler. It will be appreciated that, under the condition of ensuring a strict third proportion clock relationship, the third pixel clock signal can be generated by other methods, for example, a phase-locked loop is used for inputting the pixel clock, and the output clock can be configured to be the third pixel clock signal of the third frequency of the input clock, so long as the phase-locked loop is locked, the method can be realized; alternatively, a dedicated clock divider may be used to divide the pixel clock by three to generate one third of the pixel clock signal.
In an embodiment of the present invention, the phase relationship between the pixel clock and one third of the pixel clock includes at least three typical types:
first kind: the start rising edge of each one third of the pixel clock signal of the counting clock unit is the start rising edge of the second beat clock signal of the corresponding data packet in the pixel packing module.
First type as shown in fig. 6, each start rising edge of one third of the pixel clock signal dsc _pixel_clock of the count clock unit is a start rising edge of the second beat clock signal of the corresponding data packet pixel_data in the pixel packing module, for example, the synchronous clock sampling module may start synchronous sampling after pixel0 is written into the three-pixel width register of the pixel packing module, generating dsc _pixel_data and the second indicator signal dsc _data_en in fig. 6.
Second kind: the start rising edge of each one third pixel clock signal of the counting clock unit is the start rising edge of the third beat clock signal of the corresponding data packet in the pixel packing module.
Second type as shown in fig. 7, each start rising edge of one third pixel clock signal dsc _pixel_clock of the count clock unit is a start rising edge of a third beat clock signal of the corresponding data packet pixel_data in the pixel packing module, for example, the synchronous clock sampling module may start synchronous sampling after pixel1 is written into the three-pixel width register of the pixel packing module, generating dsc _pixel_data and the second indication signal dsc _data_en in fig. 7.
Third kind: the start rising edge of each one third of the pixel clock signal of the count clock unit is the start rising edge of the first beat clock signal of the next data packet of the corresponding data packet in the pixel packing module.
Third type as shown in fig. 8, each start rising edge of one third pixel clock signal dsc _pixel_clock of the count clock unit is a start rising edge of a third beat clock signal of the next data packet pixel_data of the corresponding data packet in the pixel packing module, for example, the synchronous clock sampling module may start synchronous sampling after pixel2 is written into the three-pixel width register of the pixel packing module, generating dsc _pixel_data and the second indication signal dsc _data_en in fig. 8.
In some embodiments, the sampling registers are required to meet the setup time and hold time requirements of the sampling register design.
In this embodiment, the synchronous clock sampling module must check the setup time and hold time of the sampling register. That is, the pixel clock and one third of the pixel clock are in a synchronous clock relationship, and the sampling registers located at the pixel clock and one third of the pixel clock across the clock boundary must meet the setup and hold time requirements of the register design so that the video data can be sampled correctly.
Referring to fig. 4, an embodiment of the present invention further provides a DSC encoder system, including: a video data input unit, a DSC encoder, a DSC output module and a video input circuit as described in any of the embodiments of the present specification;
the video data input device is connected with the input end of the video input circuit and is used for outputting pixel data to the video input circuit under each beat of pixel clock;
the DSC encoder is connected with the output end of the video input circuit and is used for encoding the video data output by the video input circuit;
the DSC output module is connected with the DSC encoder and is used for performing clock domain conversion on the encoded data output by the DSC encoder.
The content of the above system is based on the same concept as the circuit embodiment of the present invention, and the specific content can be referred to the description of the circuit embodiment of the present invention, which is not repeated here.
As shown in fig. 9, the embodiment of the present invention further provides a video input method based on the video input circuit according to any one of the embodiments of the present specification, including:
step 900, using a pixel packing module to pack the pixel data input by the video data input unit every three beats of pixel clocks, and generating a plurality of data packets with data width of three pixel data;
step 902, the synchronous clock sampling module generates a third pixel clock signal based on the clock signal of the pixel clock domain and the frequency relation between the third pixel clock domain and the pixel clock domain, so as to directly sample the data packet generated by the pixel packing module by using the third pixel clock signal, and stores the sampled data packet on a sampling register of the synchronous clock sampling module to output to the DSC encoder; wherein the number of sampling registers is 1.
The content of the above method is based on the same concept as the circuit embodiment of the present invention, and the specific content can be referred to the description of the circuit embodiment of the present invention, which is not repeated here.
It is noted that relational terms such as first and second, and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the above method embodiments may be implemented by hardware related to program instructions, and the foregoing program may be stored in a computer readable storage medium, where the program, when executed, performs steps including the above method embodiments; and the aforementioned storage medium includes: various media in which program code may be stored, such as ROM, RAM, magnetic or optical disks.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (9)

1. A video input circuit of a DSC encoder, comprising: the pixel packaging module and the synchronous clock sampling module; wherein,,
the pixel packing module is connected between the synchronous clock sampling module and an external video data input device; the video data input device works in a pixel clock domain and is used for outputting pixel data to the pixel packing module under each beat of pixel clock; the pixel packing module works in the pixel clock domain and is used for generating a data packet every three beats of pixel clocks, and the data width of each data packet is three pixel data;
the synchronous clock sampling module is connected between the pixel packing module and the DSC encoder, and is used for generating one third of pixel clock signals based on the clock signals of the pixel clock domains and the frequency relation between one third of pixel clock domains and the pixel clock domains so as to directly sample the data packet generated by the pixel packing module by utilizing the one third of pixel clock signals, and storing the sampled data packet on a sampling register of the synchronous clock sampling module so as to output the data packet to the DSC encoder; wherein the number of the sampling registers is 1.
2. The circuit according to claim 1, wherein the pixel packing module is specifically configured to store three pixel data input by the video data input unit every three beats of pixel clock in a register with a width of three pixels to output a data packet; meanwhile, a first indication signal indicating that the data packet is valid is output every beat of pixel clock after the start of the packing of the pixel data.
3. The circuit of claim 2, wherein the synchronous clock sampling module comprises: a counting clock unit and a synchronous sampling unit;
the counting clock unit is connected with the pixel clock and used for counting the received clock signals, and each three beats of clock signals are used as one third of pixel clock signals to be output to the synchronous sampling unit;
the input end of the synchronous sampling unit is connected with the pixel packing module and the counting clock unit, the output end of the synchronous sampling unit is connected with the DSC encoder, and the synchronous sampling unit is used for sampling the data packet output by the pixel packing module based on the one third pixel clock signal output by the counting clock unit and the first indication signal output by the pixel packing module, and storing the sampled data packet on the sampling register to be output to the DSC encoder; and simultaneously, outputting a second indication signal for indicating that the video data on the sampling register is valid every beat of pixel clock after the data packet output by the pixel packing module is sampled.
4. A circuit according to claim 3, wherein the start rising edge of each one third of the pixel clock signal of the count clock unit is the start rising edge of the second beat clock signal of the corresponding data packet in the pixel packing module.
5. A circuit according to claim 3, wherein the start rising edge of each one third of the pixel clock signals of the count clock unit is the start rising edge of the third beat clock signal of the corresponding data packet in the pixel packing module.
6. A circuit according to claim 3, wherein the start rising edge of each one third of the pixel clock signal of the count clock unit is the start rising edge of the first beat clock signal of the next data packet of the corresponding data packets in the pixel packing module.
7. The circuit of any of claims 1-6, wherein the sampling register is required to meet setup and hold time requirements of the sampling register design.
8. A DSC encoder system, comprising: a video data inputter, a DSC encoder, a DSC output module and a video input circuit as claimed in any one of claims 1 to 7;
the video data input device is connected with the input end of the video input circuit and is used for outputting one pixel data to the video input circuit under each beat of pixel clock;
the DSC encoder is connected with the output end of the video input circuit and is used for encoding the video data output by the video input circuit;
the DSC output module is connected with the DSC encoder and is used for performing clock domain conversion on the encoded data output by the DSC encoder.
9. A video input method based on the video input circuit of any one of claims 1-7, comprising:
the method comprises the steps of packaging pixel data input by a video data input unit every three beats of pixel clocks by using a pixel packaging module, and generating a plurality of data packets with data width of three pixel data;
the synchronous clock sampling module generates one third of pixel clock signals based on clock signals of a pixel clock domain and frequency relations between one third of pixel clock domains and the pixel clock domain, so that one third of pixel clock signals are utilized to directly sample the data packet generated by the pixel packing module, and the sampled data packet is stored in a sampling register of the synchronous clock sampling module to be output to the DSC encoder; wherein the number of the sampling registers is 1.
CN202310812350.7A 2023-07-04 2023-07-04 Video input circuit of DSC encoder, DSC encoder system and video input method Pending CN116760985A (en)

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