JPS58184555A - Pulse counter - Google Patents

Abstract

PURPOSE:To prevent possible pulse counting errors between the generation and recovery of power failure by inputting only a logic of an input signal direct into the preceding memory as sampled by the initial sampling pulse following the recovery of the power failure. CONSTITUTION:A microcomputer 7 handles a power failure detection circuit 21 and the processing for the generation and recovery of power failure. Steps 41-44 are executed in the operation other than the recovery of the power failure and when YES is given at the step 40, a logic of the input signal sampled by a sampling pulse at the moment is inputted direct into the preceding memory. When the power failure is recovered at the time 51e, the output logic of a flip-flop 20 at the pulse sampling time immediately after the time 51e is inputted into a preceding memory irrelevant to the contents of the preceding memory and the output logic of the flip-flop 20 at the pulse sampling time is inputted into the current memory. This eliminates counting errors free from the setting of the output logic of the flip-flop 20 with the recovery of the power failure.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention tfr) A signal having two voltage levels represented by IJ and rLJ varies from level "H" to level rLJ.
Regarding a pulse counting device that counts the number of times the level changes from level "L" to level rHJ (hereinafter referred to as "rising"), especially when the waveform of the input binary signal is a narrow pulse shape. This is related to the processing of

FIG. 21 is a block diagram showing an example of a pulse counting device configured using a microcomputer.

+21 is a signal input terminal, 13+ is a photocoupler, +41
, +51 is a resistor, (6) is an inverter with a binarization function, (7) is a microcomputer, (7a) is a negative output unit (hereinafter abbreviated as I10), and (7b) is a processor unit (hereinafter referred to as CPU). (abbreviated) and (7c) are memories.

Figure 2 is a flowchart showing the mounting operation in Figure 1, and shows the falling point of the signal (the point of change from level "H" to level "L").
The following shows each step when counting the number of . Inverter (
For each sampling pulse, the CPU (7b) measures the level of the input signal at the time of the sampling pulse and writes it to the memory (step 61). (9)).

Next, the contents of this memory and the previous memory (explained later)
Step 11(1): If they match, the process moves to step a4, where the contents of the current memory are written to the previous memory. In the initial state, it is always YFS in step times.
It is essential to control so that That is, the previous memory is a register that holds the contents of the current memory one sampling pulse ago.

When the step response is NO and the content of memo 1 shows the level rLJt at step aυ, it means that the column input signal has fallen from rHJ to rLJ, so add the value l to the counting memory (step (2)) , and performs the process of step fi1. At the point where W is folded, the next sampling pulse is waited for, and when the next sampling pulse arrives, the process starts from step (9). Also, step (111
If NO, it indicates the rising point, so go through step α1 and go to NE.
Transfer to XT.

Figure 3 is a waveform diagram showing the relationship between the input signal and the sampling pulse. Figure 23 (a) and (C) are the input signal, Figure 23 (b) 4 sampling pulses, Figure 23 (d) 1.
Falling point (31b) of the input signal shown in 11mJ diagram (c)
, (31a).

(31f) and (31h) show the output logic of a flip-flop whose logic is inverted when triggered by. Figure 3 (&
) for the input signal shown in
a).

(aob), (30e), (30d), (30
Between e) and (3Of), step shout in Figure 2 (equipment),
YES in step aυ, and falling points are counted in step (6), but the peak of the sampling pulse for the input signal shown in Figure 3) is the pulse of the input signal. Since the sampling pulse is longer than the width, there is no sampling pulse within the pulse width of the input signal, so the falling points (31b), (31d).

Among (31f) and (31h), some count omissions occur.

In such a case, the waveform shown in Fig. 3(d) is generated from the Fig. 3 (00 waveform), and (32b), (32d), (32
f) , (32h) can be counted.

Figure 4 is a block diagram showing another example of the conventional device;
? The same symbols as in Figure 1 indicate the same parts, and ■ indicates the T-type fritz 17.
It is 0. The output of inverter +61 is shown in Figure 3(c).
, the logic of the output terminal Q of the flip-flop ■ becomes as shown in FIG. 3(d), and if this is input and step ant in FIG.
), (32f), and (32h) can be detected.

However, assuming that a power outage occurs again on road (b) shown in Figure 24 and then the power outage is restored, the microcomputer (7
) has measures against power outages, such as saving the data immediately before the power outage to non-volatile memory and returning the saved data to the original register after the power outage is restored.
Since the output logic of the flip-flop (2) is uncertain, according to the circuit shown in Figure 4, the output logic of the flip-flop (2) is 7.
This has the disadvantage that a counting error of one pulse may occur depending on the state of the pulse.

In the conventional device of this inventor. The present invention has been made in order to eliminate the above-mentioned drawbacks, and it is an object of the present invention to provide a pulse counting device in which a pulse counting error does not occur between the occurrence of a power outage and the exit after a power outage.

Hereinafter, the present invention will be explained in detail with reference to the drawings. Fig. 5 is a waveform diagram showing signal waveforms during power outage and power outage recovery. , (50c).

(sOf), (5cg), shows the output of 7 1J tube 70 tube whose output logic is inverted by triggering, (50d)
, (51d) indicate the occurrence of a power outage, and (sow) and (ste) indicate the power outage recovery point. FIG. 6 is a block diagram showing an embodiment of the present invention, in which the same reference numerals as in FIG. 4 indicate the same parts, and (2
This is a power outage detection circuit. Since the power failure detection circuit (21) and the processing at the time of power failure and power failure recovery are generally known, their explanation will be omitted, but it is assumed that the microcomputer (71) is equipped with such a processing device.

The off-line diagram is a flowchart showing the operation of Figure 6, and shows the steps from ('') to (4).
5) T! Each shows a program step, and the second
Comparing with the figure, 9) and (41), Q(l and (42)
, 62 (43), α (44) correspond, and the step (quit) is omitted and steps (40) and (45) are added. Therefore, except for the recovery from a power outage, the steps ( 41) to (44) are executed, but if YES in step 4, the logic of the input signal sampled by the sampling pulse at that time is directly input into the previous memory. In other words, in (51e) the power outage is restored. At that time, no matter what the contents of the memory were last time (51
e) Step (
45) ) % Since the output degree logic of 7 rip 70 tube (4) at the time of the next sampling pulse is entered into the memory this time (step (41)), the 7
How is the output logic of the lipflop □□□ set: 111
・No matter what happens, no counting error will occur.

In the above embodiment, the case where there is one input signal circuit has been described, but in the case of a plurality of input signal circuits, the same procedure may be performed for each circuit. Furthermore l10 (7a)
When noise is superimposed on the signal waveform input to the input signal, the input signal may be processed as having the same logic only when the same logic continues for multiple sampling pulses. , the present invention can be utilized even in such cases.

Although FIG. 6 shows an embodiment using the microcomputer 171t, it is also easy to construct a dedicated circuit for executing the operations shown in the off-line diagram.

As described above, according to the present invention, narrow pulse-like two
Even when counting pulses in a value signal, it is possible to provide a pulse counting device that does not generate v4 counting due to power outage and power outage recovery.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a conventional pulse counting device configured using a microcomputer, Fig. 2 is a flow diagram showing the operation of the device shown in Fig. 1, and Fig. 3 is a block diagram showing an example of a conventional pulse counting device configured using a microcomputer. 4 is a block diagram showing another example of a conventional device, FIG. 5 is a waveform diagram showing signal waveforms including power outage and power restoration, and FIG. 6 is a waveform diagram showing an example of the present invention. The block diagram and off-line diagram shown are flowcharts showing the operation of FIG. 6. ! 11, +21...signal input terminal, (3;...
Photocoupler, (61... Inverter, (7)... Microcomputer 1, (7a)... Ilo 1 (7b
) -CPLT, (7c) -・-1-E 17
, (20)-T type flip-flop, (21)...
Power failure detection circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts. Agent Makoto Kuzuno - Figure 5 Figure 6 Figure 7 NEX'r Commissioner of the Japan Patent Office 6.1 (
1) Il 1, 'INi□,,□g 57-0690
No. 24 (2, Name of the invention Pulse stitch count device 3, Person making the amendment Representative Hitoshi Katayama Part 4, Detailed explanation of the invention that is the object of the agent I! Aos+ 1 Positive O Contents Qait Book Page 3, No. 16 Line ``Tokyo KYFSJ and Aruhi''
Always correct with YES J. that's all

Claims (1)

[Claims] In a pulse counting device that counts the number of times a signal having a binary voltage level inverts its voltage level to reach a predetermined voltage level, the point at which the signal is input and its voltage level inverts to reach the predetermined voltage level. a flip-flop whose output logic is inverted when triggered by a signal change; a current memory that samples the output logic of the flip-flop using a sampling pulse having a predetermined period and stores the logic at the latest sampling point; The previous memory is input at a time point nine sampling cycles later than the time when the contents were input to the memory this time,
A counter to which a value l is added each time the contents of the current memory have a different logic from the contents of the previous memory, and the contents of the current memory, the previous memory, and the counter are saved to nonvolatile memory in the event of a power outage of the device. and a means for setting the current memory, the previous memory, and the counter from the nonvolatile memory, respectively, when the power is restored, and a means for setting the logic of the input signal sampled by the first sampling pulse after the power is restored directly to the previous memory. A pulse counting device comprising: means for inputting information.