JPS58197535A - Data transfer circuit - Google Patents

Abstract

PURPOSE:To prevent the occurrence of an error, by detecting the source voltage of a device when data in a memory is transferred from the 1st processor to the 2nd processor, and inhibiting the data transfer if the detected voltage is less than a threshold value. CONSTITUTION:Transfer data D is transferred from the memory 5 of the 1st processor 1 to the memory of the 2nd processor 2 through a data line 3 while controlled by a write signal S6. The voltage Va at a terminal A is detected by a detector 10 and when it is less than a rated value, a write inhibiting signal S4 is generated and inverted by a TR11 into a signal S5, which is pulled up by a resistance 12, so that an AND circuit 13 inhibits the transfer of a write signal S3 to an input memory 7 when the level of the inverted signal S5 is L. Consequently, malfunction which occurs when the source voltage is less than the rated value is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer circuit that performs data transfer between processing devices. The present invention relates to a data transfer circuit provided with a mechanism.

As a conventional data transfer circuit, there is one shown in FIG. ) are connected to each other by.

In the following description, the first processing device (1) is assumed to be a data transfer side device, and the second processing device (2) is assumed to be a data transferred side device. The first processing device (1) has an output memory (6) that stores data to be transferred, and a power supply voltage from a terminal. (The one shown is a TTL with rated value +5V)
Inverter C) (6). Also, the second
The processing device (2) includes an input memory (γ) into which data D delivered via data @ (8) t- is written;
It has an integrated circuit (the one shown is an IC inverter) (8) which receives the above-mentioned signal 82i and sends the write signal 83t to the input memory (γ). Note that (9) is a pull-up resistor for the write control signal 82 mentioned above.

Next, the operation of the data transfer circuit having the above configuration will be explained with reference to the second figure (C) to (C)t- which intersect the operation waveform diagram of each part of the circuit.

The data D for transfer is stored in the output memory (
5) through the data line (8) to the second processing device (2)
input memory (7). Figure 2 (When the power supply voltage of the first processing device (1) shown in (turn) ■1 is the rated value (period T - T2), the cough data D is Figure 2 + C)
The %HI pulse of Kanakomigo 83 shown in (period 1.-14.
1. -1. ) is written to the input memory (7).

A method of sending the above-mentioned write signal S6 to the input memory (γ) will be described. The signal 81 formed for write control in the first processing device (1) is inverted by an IC inverter (6),
This inverted signal 82 shown in FIG. 2(B) is connected to the signal line (
4) and is input to the second processing scissors (2). Second
In the processing device (2), 1. First, the signal 82t is pulled up to the pull amplifier resistor (9), then inverted again by the IC inverter (8), and the write signal s3 (Fig. 2 (C)
)? Send to input memory (7). Note that the power supplies for operation of the IC inverters (6) and (8) are provided through terminals M and B, respectively.

As explained above, the conventional circuit includes a first processing device (1)
If the power supply voltage va is at the rated value, it will operate normally. However, this power supply voltage va is
. -T, -T, has the disadvantage that it may malfunction if it is less than the rated value. That is, the current TTL I used in the inverter (6)
Taking the ct example, if the rated voltage value is +5■, it will turn on when the power supply voltage reaches +2.5 to 5V.7) 1 unrelated to the signal.
Since the output signal 82 of the inverter (6) has the property of producing an output of the Ll level, the output signal 82 of the inverter (6) is generated during the period t knee 1. of FIG. 2(B). ．． 1. -1. There is a drawback that an incorrect pulse may be generated and, as a result, incorrect data may be written to the input memory (γ) of the second processing device (2).

The present invention has been made in view of the above points, and further includes a voltage detection circuit that detects that the power supply voltage is less than the rated value and generates a write protect signal, and a write protect signal for the write protect signal. A fail-safe mechanism consisting of an AND circuit that prevents the above-mentioned write signal from being transmitted to the input memory when the voltage is input is installed, and a fail-safe mechanism is provided to prevent unauthorized writing that occurs when the voltage is less than the rated value. The purpose of the present invention is to provide a data transfer circuit that can prevent errors and ensure accurate data transfer.

Hereinafter, an embodiment of the data transfer circuit according to the present invention will be described with reference to FIG. 5, in which the same parts as in FIG. 1 are denoted by the same reference numerals. In Figure 3, the newly established 7j (11)
I C11) e (18, (1'J is a voltage detection circuit, transistor, resistance, AND) 1
It is a gl road.

These achieve failsafe data transfer. Step 9 Specifically, the voltage detection circuit (to) detects the power supply voltage vI! It detects that L is less than the rated value (in the illustrated embodiment, it is in the range of +1.5V to 3.5V) and generates a write-inhibit signal B4, and the transistor αη detects this write-inhibit signal. The signal 84i is inverted and the drive ability is increased, and the resistor (2) is connected to this inverted signal 5.
The AND circuit θ controls the transmission of the write signal S3 to the input memory (γ), which is applied to the level of the inverted signal S5.

Next, the operation of the illustrated embodiment equipped with this fail-safe mechanism is illustrated in FIGS.
Refer to and explain.

The transfer data between the processing devices (i) * ('') is the same as in the conventional circuit. That is, the transfer data D is transferred from the output memory (6) of the first processing device t (1) to the data line (8). The data is transferred to the input memory (γ) of the second processing device (2) via slj<4, and reverse writing is controlled by the write signal 86 shown in FIG.

However, the final write signal 860 input memory (γ
The data transfer circuit according to the present invention differs from conventional circuits in one respect of sending control to the input terminal.

The power supply voltage va of the first processing device is
□-T, when the rated value +5V, the voltage detection circuit sends an output signal of 1LI level to the transistor CIη, and the transistor C11) outputs this signal B.
4f Invert. As a result, the 1 inverted signal 85 is shown in FIG. 4(C).
During the period T□-T, the level becomes %H# as shown in FIG. 4(D).
The write signal s is not blocked from passing the write signal S3.
6 (FIG. 4(E)) to the input memory (γ). Thus, normal writing of the transfer data) D is performed in the input memory (7).

On the other hand, the '1 source voltage V of the first escape device (1). is period T in FIG. 4(A). -T1. Or, if the rated value is less than +5V as shown in T and -T, in the illustrated embodiment, if the power supply voltage is between +1.5v and 6.5V, the voltage detection circuit detects this fact. A write inhibit signal at the %Hl level is sent to the 84t transistor (b). Therefore,
The inverted signal S of the current signal S4 by the transistor C11)
5 is the period t knee t4.1. of FIG. 4(C). -1 work, the work shown in will be %'L rubel. As a result, the AND circuit (18) receiving the signal S5 closes and prevents transmission of the write signal S5. That is, the period T of the AND circuit (in this case, the output signal S6 is 1m regardless of the write signal S3). -T, T, -Ts indicates %L rubel. In addition, step 9 prevents the transfer data D from being written to the input memory (7) below the rated value,
Accurate transfer of data is guaranteed.

It goes without saying that the present invention is not limited to the data transfer circuit using the TTL inverter of the illustrated embodiment even if the power supply voltage is less than the rated value. Furthermore, in the explanation of the two illustrated embodiments, the case of data transfer from the first processing device to the second processing device has been dealt with, but the present invention can of course be applied to the reverse case as well.

As described above, the data transfer circuit of the present invention includes, in addition to the conventional circuit, a voltage detection circuit that detects that the power supply voltage of the transfer side processing device is less than the rated value and generates a write inhibit signal. If the write inhibit signal is received, a 7-function mechanism consisting of an AND circuit that blocks the transmission of the write signal to the input memory is provided.1 With this, when the power supply voltage is not at the rated value, This prevents unauthorized writing to the friend's memory.

This has the advantage that accurate data transfer is guaranteed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional data transfer circuit. In one example. A block diagram showing the data transfer circuit shown in FIGS.
The figure is a waveform diagram showing the operation of each part of the data transfer circuit shown in FIG. (1), (2): Processing device ii (8B data line (51I (γ): Memory (6) I (8): Engineering C inverter UO+: Voltage detection circuit α1): Transistor aal: AND (A
Nn) Circuit In Figure 5, the same reference numerals indicate the same or corresponding parts. Agent Shin Kuzuno - 9- Figure 1 Figure 2

Claims (1)

Scope of Claims: Storage data 1 of the output shaving circle of the first processing device 1 is delivered to the input memory of the second processing device via a data line, and writing of this data to the input memory 1-. In a data transfer circuit configured to perform a convolution 1M signal input via an integrated circuit that operates in response to a power supply voltage value of the first processing device, the power supply voltage value is input and the voltage section 1 is applied to the integrated circuit. A voltage detection circuit is provided that outputs a warning signal when the rated value of the circuit is not fully met, and a voltage detection circuit is provided that outputs a warning signal when the circuit is not fully satisfied with the rated value. A data transfer circuit is provided in series between the integrated circuit and the input memory. .