JPH0268527U - - Google Patents

Info

Publication number
JPH0268527U
JPH0268527U JP14830488U JP14830488U JPH0268527U JP H0268527 U JPH0268527 U JP H0268527U JP 14830488 U JP14830488 U JP 14830488U JP 14830488 U JP14830488 U JP 14830488U JP H0268527 U JPH0268527 U JP H0268527U
Authority
JP
Japan
Prior art keywords
source voltage
outputs
voltage
integrated value
internal counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14830488U
Other languages
Japanese (ja)
Other versions
JPH0733464Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988148304U priority Critical patent/JPH0733464Y2/en
Publication of JPH0268527U publication Critical patent/JPH0268527U/ja
Application granted granted Critical
Publication of JPH0733464Y2 publication Critical patent/JPH0733464Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Power Sources (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Measurement Of Current Or Voltage (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の1実施例を示すブロツク図、
第2図は第1図に示す実施例の動作を説明する波
形図である。 10……検出部、11……変換回路、12……
カウンタ、13……メモリ、14……マイクロプ
ロセツサ、17……LCD、18……DC/DC
コンバータ、19……遅延回路、20……EEP
ROM、Vs……ソース電圧、Vc……回路電圧
、Es……設定回路、RST……リセツト信号、
NMI……ノンマスカブルインタラプト信号NM
I。
FIG. 1 is a block diagram showing one embodiment of the present invention.
FIG. 2 is a waveform diagram illustrating the operation of the embodiment shown in FIG. 1. 10...Detection unit, 11...Conversion circuit, 12...
Counter, 13...Memory, 14...Microprocessor, 17...LCD, 18...DC/DC
Converter, 19...Delay circuit, 20...EEP
ROM, Vs...source voltage, Vc...circuit voltage, Es...setting circuit, RST...reset signal,
NMI...Non-maskable interrupt signal NM
I.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 測定値を積算する内部カウンタと、ソース電圧
が入力されこのソース電圧を変換してこれより小
さい回路電圧を作つて出力するDC/DCコンバ
ータと、前記ソース電圧を保持する大容量のコン
デンサと、前記ソース電圧に関連した電圧と前記
ソース電圧よりは小さい設定電圧とを比較して誤
差信号を出力する比較器と、この誤差信号に対し
て所定の時間だけ遅れたリセツト信号を出力する
遅延回路と、前記誤差信号とほぼ同時にレベル変
動を生じるノンマスカブルインタラプト信号が入
力されることにより積算データを格納させる格納
指令を出し前記リセツト信号により格納されたデ
ータを読み出す読出指令を出力するマイクロプロ
セツサと、前記格納指令に基き前記内部カウンタ
の積算値がデータバスを介して格納されるEEP
ROMと、前記リセツト信号に関連して前記EE
PROMに格納された積算値を前記内部カウンタ
に復帰させることを特徴とする積算値バツクアツ
プ装置。
an internal counter that integrates measured values; a DC/DC converter to which a source voltage is input and converts the source voltage to create a smaller circuit voltage and output it; a large-capacity capacitor that holds the source voltage; a comparator that compares a voltage related to the source voltage with a set voltage smaller than the source voltage and outputs an error signal; a delay circuit that outputs a reset signal delayed by a predetermined time with respect to the error signal; a microprocessor that outputs a storage command to store integrated data by receiving a non-maskable interrupt signal that causes a level change almost simultaneously with the error signal; and outputs a read command to read the stored data in response to the reset signal; EEP in which the integrated value of the internal counter is stored via a data bus based on a command;
ROM, and the EE in relation to the reset signal.
An integrated value backup device characterized in that an integrated value stored in a PROM is returned to the internal counter.
JP1988148304U 1988-11-14 1988-11-14 Integrated value backup device Expired - Lifetime JPH0733464Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988148304U JPH0733464Y2 (en) 1988-11-14 1988-11-14 Integrated value backup device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988148304U JPH0733464Y2 (en) 1988-11-14 1988-11-14 Integrated value backup device

Publications (2)

Publication Number Publication Date
JPH0268527U true JPH0268527U (en) 1990-05-24
JPH0733464Y2 JPH0733464Y2 (en) 1995-07-31

Family

ID=31419503

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988148304U Expired - Lifetime JPH0733464Y2 (en) 1988-11-14 1988-11-14 Integrated value backup device

Country Status (1)

Country Link
JP (1) JPH0733464Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110385507A (en) * 2018-04-18 2019-10-29 株式会社达谊恒 Wire feed unit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58184555A (en) * 1982-04-22 1983-10-28 Mitsubishi Electric Corp Pulse counter
JPS61191631U (en) * 1985-05-21 1986-11-28

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58184555A (en) * 1982-04-22 1983-10-28 Mitsubishi Electric Corp Pulse counter
JPS61191631U (en) * 1985-05-21 1986-11-28

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110385507A (en) * 2018-04-18 2019-10-29 株式会社达谊恒 Wire feed unit
CN110385507B (en) * 2018-04-18 2022-02-01 株式会社达谊恒 Welding wire feeding device

Also Published As

Publication number Publication date
JPH0733464Y2 (en) 1995-07-31

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