JPH03194476A - Measuring circuit for j-k flip-flop - Google Patents

Abstract

PURPOSE:To facilitate repetition measurements by making the change of stage return to the initial state by the detection performed in a setting device when the output state of J-K flip-flop which is a circuit to be measured is changed. CONSTITUTION:By the J-K FF 1, the input signal of input terminal J is fetched at the rise of clock signal CLK and outputted to an output terminal Q after a specified time. By a D FF 2, the input signal is fetched at the rise of signal CLK and outputted to an output terminal DQ after the specified time. The output of output terminal DQ is added to a reset terminal R of the J-K FF 1 to reset the J-K FF 1, then this procedure is repeated. Consequently, when the output of an output terminal OUT is measured, a phase of input signal at the input terminal J is made to advance or delay in the condition that the clock signal CLK is fixed, then a set-up time and hold time can be measured continuously and repeatedly, and when the output state of J-K FF is changed, the change can be returned to the initial state.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention provides a method for setting up the J-K flip-flop from an output state that changes depending on the phase difference between an input signal applied to the J-K flip-flop and a clock signal. This invention relates to a flip-flop measuring circuit for measuring time and hold time.

[Conventional technology]

FIG. 5 is a block diagram showing a conventional example of this type of J-type flip-flop measuring circuit, and FIG. 6 is a waveform diagram showing the operation of the conventional example of FIG.

Conventionally, the input time difference (phase difference) between the input signal and the clock signal required to obtain the expected output corresponding to the input signal applied to the input terminals J and K is measured as the setup time and hold time. .

With the clock signal CLK fixed, if the input signal S1 at the input end J is shifted in phase to the right as shown by the arrow to become the input signal S2, then when a certain point is exceeded, the waveform of the output from the output end Q becomes H11. Instead of , it becomes 111 I+. On the other hand, if the input signal S1 is shifted in phase to the left as indicated by arrow B and becomes the input signal 83, the output waveform similarly inverts from "L" to "H" after a certain point. The time difference between signals 82, 83 and clock signal CLK is the setup time and hold time.

[Problem to be solved by the invention]

The conventional J-type flip-flop measurement circuit described above uses the J-type circuit under test when measuring the setup time and hold time from the phase difference between the input signal and the input signal.
If the state of the output of the flip-flop changes even once, it is necessary to change the input signal to the input terminal J again and reset the initial settings, which makes it difficult to repeatedly measure to improve measurement accuracy. There are drawbacks.

SUMMARY OF THE INVENTION In view of the above-mentioned drawbacks, it is an object of the present invention to provide a flip-flop measuring circuit in which repeated measurements can be easily performed.

[Means to solve the problem]

The J- flip-flop measurement circuit of the present invention detects a change in the output state of the J- flip-flop, which changes in synchronization with a clock signal, in synchronization with the clock signal. It has a setting means for returning the output state to the initial state before the output state was changed.

[Effect]

When the output state of the flip-flop changes in J-, which is the circuit under test, the setting means detects this and returns it to the initial state.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention;
The figure is a waveform diagram showing the operation of the embodiment of FIG. 1.

Flip-flop 1 at J- is the object of measurement, and the input @J
1. An input signal is applied to l, the input terminal is fixed at a logic level "OII", and a clock signal CLK is applied to the clock terminal CK.

The D flip-flop 2 has an input terminal connected to J-, an output terminal GQ of the flip-flop [1 block 1, an output terminal 0 (JT), and an output terminal D
Q is connected to the reset terminal R of the knob 70 and knob 1, respectively, and the terminal CK of the terminal CK inputs the clock signal CLK.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 2.

The flip-flop 1 receives the input signal at the input terminal J at the rising edge of the clock signal CLK, and outputs the received signal to the output terminal Q after a predetermined period of time. D flip-flop [l-tube 2 takes in the output of the output end Q at the rising edge of the clock signal CLK, and outputs the taken signal after a predetermined time]
Output to J end DQ.

The output of the output terminal DQ is applied to the reset terminal R of the flip-flop 1 at the J- terminal, and the flip-flop 1 at the J- terminal is reset. These operations are then repeated.

Therefore, when measuring the output of the output terminal OUT, the set-up time and hold time are can be measured continuously and repeatedly.

FIG. 3 is a block diagram showing a second embodiment of the present invention, and FIG. 4 is a waveform diagram showing the operation of the embodiment of FIG.

J-, flip-flop 1 has input terminal J at logic level "
The input terminal K inputs the input signal, the clock terminal CK inputs the clock signal CLK, and the output terminal Q
is connected to the output terminal OUT. D flip-flop 2 has an input end J- and an output end Q of flip-flop 1.
, the output terminals DQ are connected to the J- and Z terminals S of the flip-flop 1, respectively, and the clock CK is connected to the clock signal C
Entering LK.

Next, the operation of this embodiment will be explained with reference to FIG.

A clock signal CI-K is applied to the J-K flip-flop 1 and the D-flip 70 terminal CKk, and an input signal is applied to the input terminal K. Then, after a predetermined period of time, outputs appear from Q and Q. The D flip-flop takes in the output of the output terminal Q at the rising edge of the clock signal CLK, outputs it from the output terminal DQ after a predetermined time, and uses this output to
Flip-flop 1 is set again.

Therefore, when measuring the output at the output terminal OUT, by advancing or delaying the phase of the input signal at the input terminal J with the input signal CLK fixed,
Set-up time and hold time can be continuously and repeatedly measured.

(Effects of the Invention) As explained above, the present invention allows the setting means to detect a change in the output state of the flip-flop in J-, which is the circuit under test, and return it to the initial state.
Set-up and hold times can be measured continuously, and most of the measurement data needed to determine set-up and hold times, which usually have a certain time width, i.e., are measured as probability distributions, can be collected. This has the effect of significantly improving the collection efficiency, and furthermore, it has the effect of improving the accuracy of the characteristic display value of the J2-K flip-flop based on the measurement.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
1 is a waveform diagram showing the operation of the embodiment of FIG. 1, FIG. 3 is a block diagram showing the second embodiment of the present invention, and FIG. 4 is a waveform diagram showing the operation of the embodiment of FIG. 3. Figure 5 is a block diagram showing a conventional example of this type of J-type flip-flop measuring circuit.
FIG. 6 is a waveform diagram showing the operation of the conventional example shown in FIG. 1...J- to flip [1 knob, 2...D flip 70 knobs, J, to D...input end, Q, Q, DQ...output end, S...set end, R...Reset end, CK...Clock end, CLK...Clock signal.

Claims (1)

[Claims] 1. J-K measuring the setup time and hold time of the J-K flip-flop from the output state that changes depending on the phase difference between the input signal applied to the J-K flip-flop and the clock signal. In the flip-flop measurement circuit, a change in the output state of the J-K flip-flop that changes in synchronization with the clock signal is detected in synchronization with the clock signal, and when detected, the J-K flip-flop changes the output state. A J-K flip-flop measuring circuit characterized by having a setting means for returning to an initial state before being changed.