JPH09197024A - Testing circuit and digital ic incorporating the testing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to measure the frequency locked by PLL in a short time and to simplify a measuring system by counting PLL operation signals by each equal period from a different time point and comparing to detect the counted result. SOLUTION: Counters A and B count signals S output from a PLL circuit 11. The counter A counts the fetched signals from the circuit 11 for the time of a high level of a counter enable signal CE, and outputs the number to counters QAO to QAn. The counter B counts the fetched signals from the circuit 11 for time of the low level of the signal CE, and outputs the number to counters QAO to QAN. In this case, n is natural number, and (n+1) becomes bit number. A comparator 13 compares the counted results of the counters A with B in the counting time. A decoder 14 fetches the decision pulse DP from the comparator 13, reads the outputs of the counters A and B, and outputs the result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention particularly relates to a test circuit used in an LSI (digital IC) having a built-in PLL and a digital IC having such a test circuit built-in.
About.

[0002]

2. Description of the Related Art In a test circuit for an LSI having a built-in PLL, as a method for testing the PLL, it is common to measure the frequency when the PLL is locked by using an analog tester and inspect whether it is a desired value. Is. Therefore, in a digital IC, it is necessary to measure twice with the analog tester in the PLL section and the digital tester in the other digital sections.

The problems of the above test circuit are that the analog tester and the digital tester are expensive, and that it takes a long time for measurement, that is, waiting for the PLL to become sufficiently stable.

7 and 8 respectively show an L having a built-in PLL.
It is the 1st circuit block diagram and the 2nd circuit block diagram which show the conventional test circuit in SI. Both figures are L
SI1 is configured to be measured by a digital tester only. In FIG. 7, the frequency measuring device 31 is connected to the outside of the digital tester 21 by using an external communication means, and the frequency value when the frequency of the PLL is sufficiently stable is taken into the tester 21 by the external communication means and judged. In FIG. 8, a digital tester 22 incorporating a frequency measuring device 32 is used, and the frequency value when the frequency of the PLL is sufficiently stable is taken into the tester 22 through a specific terminal to make a determination.

As a problem of the test circuit as shown in FIGS. 7 and 8, in FIG. 7, since the frequency measuring instrument is connected to the outside of the digital tester by using the external communication means, the frequency is taken in and judged. The measurement system becomes complicated, and P
It is necessary to secure sufficient time for the frequency of the LL to stabilize before preparing for frequency measurement.
The time when the PLL locks is not clearly known, and there is a time difference in the lockup time of the PLL due to a change in the Vth of the sample. Therefore, the test was started after a sufficient time had elapsed after the PLL locked. As described above, since the external communication means is used, the test cost becomes high and the test time becomes long.

A problem with FIG. 8 is that in the case of a digital tester with a built-in frequency measuring device, there are many restrictions such as limited terminals of the tester that can measure the frequency, and it cannot be used. To be

[0007]

As described above, conventionally,
When testing a PLL, a digital IC uses expensive analog testers and digital testers and waits until the PLL is sufficiently stable for measurement. Therefore, a long test time and a high test cost are problems. There is.

Further, even when the measurement is performed only by the digital tester, the measuring system becomes complicated due to the external equipment, and the problem of increasing the test time and increasing the test cost is a problem.
Even when using a digital tester with a built-in frequency measurement device,
There is a problem that it is not versatile because the terminals of the tester that can measure the frequency are limited.

The present invention has been made in consideration of the above circumstances, and an object thereof is to measure a frequency locked by a PLL in a short time and to simplify a measuring system, and a built-in test circuit. The purpose of this is to provide a digital IC.

[0010]

A test circuit according to the present invention comprises means for counting PLL operation signals for the same period from different time points, and comparison means for comparing and detecting the counting result by the means. To do.

According to the present invention, the time when the PLL is locked is detected by comparing the count results in the same period from different times. Such a test circuit can be easily incorporated in a digital IC.

[0012]

1 is a circuit diagram showing a configuration of a PLL test circuit according to a first embodiment of the present invention.
It is composed of two counters A (12-1) and B (12-2), a comparator 13 and a decoder 14. The counter A and the counter B are counters that count the signal S output from the PLL circuit 11, and the result is Q in the counter A.
A0 to QAn, and the counter B outputs QB0 to QBn. Here, n is a natural number and n + 1 is the number of bits. The counter A and the counter B are selected by the counter enable signal CE.

The counter enable signal CE is a signal with a duty of 50%, and the output signal S (P
LL clock) is set. Signal C
The period of E is set longer than that of the signal S. As shown in FIG. 2, when the “H” (high) level period Ta of CE is assigned to the counting period of the counter A and the “L” (low) level period Tb is assigned to the counting period of the counter B, the counter A is -Counters B are alternately selected at the same time.

The counter A has a PLL circuit 11 at time Ta.
It counts the number of the signals received from and outputs the same to QA0 to QAn. Further, the counter B is T
It counts how many signals from the PLL circuit are taken in at the time of b, and outputs to QB0 to QBn by that number.

FIG. 3 is a timing chart for explaining the circuit operation of FIG. Comparator 13 is Ta of counter A
The outputs QA0 to QAn in the period and the outputs QB0 to QBn in the Tb period of the counter B are compared. That is, when the value (An) of QA0 to QAn and the value (Bn) of QB0 to QBn in the count period of the same length are equal, the PLL circuit
The output signal at 11 is stable. At this time, the comparator 13 outputs the determination pulse DP.

The values (An) of QA0 to QAn and QB0 to Q
When the values of Bn (Bn) are not equal, it indicates that the output signal of the PLL circuit 11 is not stable. At this time, the judgment pulse is not output (131).

The decoder 14 receives the decision pulse D from the comparator 13.
P is taken in and outputs QA0 to Q of counter A at this time
An and the outputs QB0 to QBn of the counter B are read,
Output the result. That is, the value corresponding to the frequency of the output signal of the PLL circuit 11 is output.

By measuring the number of clocks from the PLL circuit 11 in the Ta period and the Tb period as described above, the frequency of the PLL circuit 11 can be measured based on this value. Therefore, Ta and Tb of the counter enable signal CE
The longer the, the higher the test accuracy.

According to the present invention, an L having a built-in PLL is used.
In SI, in order to measure the oscillation frequency of the PLL,
Conventionally, a dedicated tester is used or an external circuit is added to the outside, but the configuration is remarkably simplified. That is, the configuration of the test circuit in FIG.
Can be built into (digital IC 1),
It can also be configured as an external digital tester as shown in FIG. Moreover, it does not have a special configuration in which analog testers are mixed as in the conventional case.

FIG. 6 shows the P according to the second embodiment of the present invention.
It is a circuit diagram which shows the structure of the test circuit of LL. The difference from FIG. 1 is that only one counter 12 is used, a delay circuit 15 is provided, and a count value of the counter 12 in the same period in different time phases is compared by a comparator 13. The counter 12 inputs the counting result of counting for a predetermined period from the first time point and the counting result of counting for the same predetermined period from the second time point after the first time point to the comparator 13, and counts them. In response to the match detection of the result, the decoder 14 outputs a signal corresponding to the frequency of the PLL operation signal based on the counting result. The configuration of the test circuit shown in FIG. 6 can be built in the LSI as shown in FIGS. 4 and 5, or can be built in an external digital tester.

According to each of the above-mentioned embodiments, conventionally, the time when the PLL is locked for the measurement of this frequency is not clearly known, and there is a time difference in the lock-up time of the PLL due to the change of Vth of the sample. The test was started after a sufficient time had elapsed after the PLL was locked. However, by applying the present invention, the test can be performed from the time when the frequency is locked, and the frequency can be measured. Very effective for simplification.

It should be noted that rather than determining that the frequency at which the PLL is locked when the determination pulse DP is first output, it is determined that the frequency at which the PLL is locked at the time when the DP is continuously output a plurality of times. By doing so, erroneous determination due to the influence of noise or the like can be prevented.

[0023]

As described above, according to the test circuit of the present invention and the digital IC incorporating the test circuit, it is indicated that the time when the two measurement results match is the time when the PLL is locked. Is possible. Also,
Since this time point is the time point at which the frequency is measured at the same time, a simplified test circuit measurement system can be realized in a short time.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a PLL test circuit according to a first embodiment of the present invention.

2 is a waveform diagram of a counter enable signal in the circuit of FIG.

FIG. 3 is a timing chart for explaining the circuit operation of FIG.

FIG. 4 is a first circuit diagram showing an application example to which FIG. 1 is applied.

FIG. 5 is a second circuit diagram showing an application example to which FIG. 1 is applied.

FIG. 6 is a circuit diagram showing a PLL test circuit according to a second embodiment of the present invention.

FIG. 7 is a first circuit block diagram showing a conventional test circuit in an LSI incorporating a PLL.

FIG. 8 is a second circuit block diagram showing a conventional test circuit in an LSI incorporating a PLL.

[Explanation of symbols]

 1 ... Digital IC, 11 ... PLL circuit, 12, 12-1, 12-2 ... Counter, 13 ... Comparator, 14 ... Decoder, 15 ... Delay circuit.

Front page continuation (72) Inventor Yukihiko Yabe 3-3-9 Shimbashi, Minato-ku, Tokyo Toshiba Abu E. Co., Ltd.

Claims (10)

[Claims] 1. A test circuit comprising: means for counting PLL operation signals from different points of time for the same period; and comparing means for comparing and detecting respective counting results by the means. 2. A means for counting PLL operation signals from different time points in the same period, a comparing means for detecting a coincidence of count results in the same period from the different time points, and a coincidence detection of the count results in the comparing means. And a means for outputting a signal corresponding to the frequency of the PLL operation signal based on the counting result. 3. A means for counting PLL operation signals in a digital IC for each same period from different time points, a comparing means for detecting coincidence of count results in the same period from the different time points, and the counting result in the comparing means. A test circuit having means for outputting a signal corresponding to the frequency of the PLL operation signal based on the counting result in accordance with the coincidence detection of the digital IC having a built-in test circuit. IC. 4. A first and second counting means for alternately counting the PLL operation signals for the same period, and a comparing means for comparing and detecting the counting results of the first and second counting means. Characteristic test circuit. 5. A first and a second counter for alternately counting the PLL operation signals for the same period, a comparing means for detecting a coincidence of the counting results by the first and the second counter, and the above-mentioned in the comparing means. A test circuit, comprising: a decoding unit that outputs a signal corresponding to the frequency of the PLL operation signal based on the counting result in response to the coincidence detection of the counting result. 6. The first and second counters are alternately controlled by a control signal having a duty of 50%, and the control signal has a cycle longer than that of the PLL operation signal. 5. The test circuit according to 5. 7. A first and a second counter for alternately counting the PLL operation signals in the digital IC for the same period, and a comparing means for detecting the coincidence of the counting results by the first and the second counters, A test circuit having a decoding means for outputting a signal corresponding to the frequency of the PLL operation signal based on the counting result in response to the coincidence detection of the counting result in the comparing means is built in the digital IC. Digital IC with built-in test circuit. 8. The first and second counters are alternately operated and controlled by a control signal having a duty of 50%, and the control signal has a cycle longer than that of the PLL operation signal. A digital IC incorporating the test circuit according to 7. 9. A counter for counting a PLL operation signal at a first time point and at a second time point thereafter for a predetermined period, and a delay for delaying the output of the counting result of the counter for a predetermined period from the first time point. A circuit, comparing means for detecting a match between the counting result of the counter for a predetermined period from the second time point and the counting result which is the delay circuit output, and the comparing means for inputting the output signal of the counter And a decoding means for outputting a signal corresponding to the frequency of the PLL operation signal based on the counting result in accordance with the coincidence detection of the counting result in the test circuit. 10. A counter that counts a PLL operation signal in a digital IC at a first time point and at a second time point thereafter by a predetermined period, and an output of a counting result of the counter that has counted for a predetermined period from the first time point. A delay circuit for delaying, a comparing means for detecting a match between a counting result of the counter for a predetermined period from the second time point and a counting result which is the output of the delay circuit, and an input signal of the counter. A test circuit having a decoding means for outputting a signal corresponding to the frequency of the PLL operation signal based on the counting result in response to the coincidence detection of the counting result in the comparing means, A digital IC with a built-in test circuit.