JPH0210625B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data receiving circuit for a polling-type abnormality monitoring device that intensively monitors abnormalities such as fires and gas leaks.

Recently, computers have been introduced into equipment for monitoring abnormalities such as fires and gas leaks, and a polling method has been used to collect abnormality information from a plurality of terminal devices. In the above-described system, a high-quality transmission path is required to accurately receive return data from each terminal. However, in fire alarm systems and the like, a data collection device and a plurality of terminal devices are generally connected by balanced lines. Balanced lines cause distortion in transmission waveforms due to electrostatic capacitance and the like, and are susceptible to noise interference, making it difficult to obtain sufficient reliability.

In view of the above-mentioned circumstances, an object of the present invention is to provide a data receiving circuit for an abnormality monitoring device that can improve the reliability of data received through a low-quality transmission line.

The receiving circuit of the present invention calls a plurality of terminal devices connected to a transmission path using an address signal from the data collection device side, and receives fire information from the called terminal devices.
In a polling-type abnormality monitoring device that returns abnormality information such as gas leak information, the data collection device sends a synchronization signal and an address signal to the transmission path, and the data acquisition device transmits a synchronization signal and an address signal to the transmission path,
a timing pulse generating means for generating a plurality of delayed timing pulses of mutually different phases; a plurality of flip-flops for respectively setting return data from the terminal device according to timing pulses output from the timing pulse generating means; The present invention is characterized in that it includes an adder that adds the outputs of the plurality of flip-flops, and the return data is identified based on the output of the adder.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. That is, the clock oscillator 1 generates a clock pulse train of a constant period. The ripple counter 2 sends a synchronizing signal from the output terminal Q ₁ to the line L ₁ by the first pulse of the clock pulse train.
The outputs Q ₂ to Q _o of the ripple counter 2 are at a high level for one clock period by the second to nth pulses, respectively. However, only the latter half Q _o , Q _o-1 and Q _o-2 are output. At the n+1st pulse, the output Q ₁
becomes high level, and the ripple counter 2 operates cyclically. Figure 2a shows the output pulse train of the clock oscillator 1, and figure 2b shows the ripple counter 2.
The waveform of the output _Q1 , that is, the synchronization signal, is shown, and c, d, and e in the figure are the outputs of the ripple counter 2, respectively.
The waveforms of Q _o-2 , Q _o-1 , and Q _o are shown. That is, a synchronization signal is output every n clocks, and the output Q _o-2 ,
Timing pulses are output from Q _o-1 and Q _o , each of which lags behind the synchronizing signal by more than 1/2 of the synchronizing signal cycle, and whose phases differ by one clock. In this embodiment, the oscillator 1 and the ripple counter 2 constitute a timing pulse generating means that generates a plurality of timing pulses of mutually different phases delayed from the synchronization signal.

A start signal, an address signal and a stop signal to be sent to the line are input in parallel to the shift register 3, and are set by the output Q _n of the counter 4. The counter 4 sets the output _n to a high level when it counts m synchronization signals. The signal set in the shift register 3 is serialized bit by bit using the synchronizing signal as a clock and sent to the line.
The _next address signal is set by the (m+1)th synchronization signal and sent out again as a serial signal. The value of m above is the start signal,
The total number of bits is greater than the total number of bits of the address signal, stop signal, and return data. Therefore, as shown in FIG. 2f, an address signal is output to the line _L2 following the start signal, and a stop signal (not shown) is also output.

Each of the plurality of terminal devices 5 uses the synchronization signal on line _L1 as a clock signal and monitors the address signal on line _L2 , and when it receives an address signal specifying itself, it outputs fire information etc. as a digital data signal. Send onto track L ₃ . Of course, the data signal is serially transmitted bit by bit in synchronization with the synchronization signal. The return data signal is transmitted on the line _L3 and input to the data collection device side. In a region where the transmission line is used for a short transmission distance compared to the wavelength of the signal pulse and the transmission line acts capacitively or inductively, the received pulse waveform exhibits charging characteristics at the rising edge and discharge characteristics at the falling edge. Therefore, the waveform of the input signal is as shown in Fig. 2g.
The waveform has a slow rise and a trailing fall, and the signals of adjacent bits overlap each other. Such received data signals are input to data inputs D of a plurality of flip-flops 6, 7, and 8. The flip-flop 6 takes in the input signal by the Qo _-2 output of the ripple counter 2, and
Flip-flop 7 receives an input signal through its Qo _-1 output, and flip-flop 8 receives an input signal through its _Qo output. Therefore, the outputs of flip-flops 6 to 8 are h, i, and h, i, respectively in FIG.
It becomes as shown in j. The data acquisition point of each flip-flop is at the end of the synchronization signal that is delayed by 1/2 or more of the synchronization signal period, so the previous received signal has sufficiently disappeared, and the current received signal has risen sufficiently. Accurate data can be imported from Then, the outputs of flip-flops 6 to 8 are
The signals are input to a comparator 9 through resistors R ₁ , R ₂ , and R _3, respectively, and the comparator 9 outputs a high level when the sum of the input signals is greater than a certain value, as shown in FIG. 2k. For example, resistance
When the values of R ₁ , R ₂ , and R ₃ are equal, the input signals are separated by a majority vote of the outputs of flip-flops 6-8. Furthermore, by making the resistance values of the resistors R ₁ , R ₂ , and R ₃ different, for example, the output of the flip-flop 8 can be treated as the most weighted signal. In this case, the received pulse waveform of the return pulse output between sync signals is less affected by the previous signal the closer it is to the end between sync signals, so the closer it is to the end between sync signals, the more weight is added. This enables more accurate data identification. Comparator 9
The output signal of is set in the flip-flop 10 by the next synchronizing signal as shown in FIG.
Output as received data.

In this embodiment, the timing for setting the received signal in the plurality of flip-flops 6 to 8 is given by the timing pulse outputted in the latter half of the synchronization signal period outputted by the ripple counter 2, so that the received signal has a sufficient rising edge. In addition, data is taken in when the received signal one bit before has sufficiently disappeared, which has the effect of being less susceptible to distortion of the received waveform due to line capacitance, etc. Further, by taking in the received signal with a plurality of flip-flops at different timings, it is possible to reduce the influence of noise. In other words, the effects of distortion and noise on received waveforms are reduced, and received data can be obtained with high reliability even if a low-quality transmission path is used.

Figure 3 shows a synchronization signal transmitted by a pair of transmission lines.
FIG. 7 is a signal waveform diagram showing another embodiment of the present invention in which an address signal and a return signal are exchanged.
In this case, one data section T as shown in Figure a
Data "1" is represented by signal A having a low level period of 1/4 section at the rear end, and one data section T is divided into four as shown in Figure b and output as high, low, high, low. The data “0” is represented by signal B, and from the data collection device side,
As shown in FIG. 2, a synchronization signal is sent out after a star bit by signal A, an address signal consisting of a combination of signals A and B, and a stop bit by signal B. The synchronization signal is a waveform in which signal B is continuously transmitted. During the low level period of the synchronization signal, the output of the sending circuit (not shown) is grounded, and a current flows in due to the return data signal shown in FIG. 4D sent out from the terminal device. If this inflow current is detected by, for example, a photodiode inserted in series with the line, and the light emitted from the photodiode is photoelectrically converted, an electrical signal corresponding to the data current can be obtained by return. This electrical signal is used as a received data signal by a plurality of flip-flops 6 to 8 shown in FIG.
By inputting the data into the signal, it is possible to restore correct data from a received signal with waveform distortion using the same timing as in the above-described embodiment.

The above-mentioned classification of the received signals is achieved by, for example, reading one bit of the returned data from the input port multiple times at different timings in synchronization with the synchronization signal and with a delay, and calculating the result of the multiple read data. It is also possible to perform this by software, such as determining ``1'' and ``0''.

As described above, in the present invention, a synchronization signal is sent from the data collection device side, return data is sent out from the terminal side in synchronization with the synchronization signal, and the received signal is sent to a plurality of channels delayed from the synchronization signal. Since the received data is sorted by combining the results of sampling at different timings, accurate data restoration is possible by reducing the effects of waveform distortion and noise caused by the capacitance of the transmission line. Therefore, even if a low-quality transmission path is used, highly reliable received data can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a type chart showing various signals of the above embodiment, and FIG. 3 is a time chart showing another embodiment of the present invention. In the figure, 1... clock oscillator, 2... ripple counter, 3... shift register, 4...
Counter, 5...Terminal, 6-8, 10...Flip-flop, 9...Comparator (adder).

Claims (1)

[Claims] 1. Polling in which a plurality of terminal devices connected to a transmission path are called by an address signal from the data collection device side, and abnormal information such as fire information and gas leak information is returned from the called terminal devices. In the data receiving circuit of the abnormality monitoring device according to the above-mentioned method, the data collecting device sends a synchronization signal and an address signal to the transmission path, and collects a plurality of timing pulses of mutually different phases concentrated on the terminal side between the synchronization signals. a timing pulse generating means for generating a synchronizing signal; and a timing pulse generating means for transmitting one bit of data from the terminal device over the period of the synchronizing signal, and transmitting data returned from the terminal device by a timing pulse output from the timing pulse generating means. a plurality of flip-flops that are set respectively, and an adder that adds the outputs of the flip-flops that are taken in by the timing pulses nearer to the terminal portion between the synchronization signals, with a weight given to the outputs of the flip-flops; A data receiving circuit for an abnormality monitoring device characterized by sorting data. 2. In the data receiving circuit of the abnormality monitoring device according to claim 1, the data collecting device sends out the address signal and the synchronization signal in series, and between the synchronization signals, the data is returned from the terminal device. The device is characterized in that it comprises a current detection means for detecting a current signal, and the output of the current detection means is inputted to the plurality of flip-flops.