JPH0135420B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a disk rotation servo device that controls the rotation of a disk on which digital signals are recorded.

In recent years, analog signals such as audio signals are converted to digital signals of 1 or 0 by pulse code modulation (PCM), recorded in the digital signal format on recording media such as disks and tapes, and the digital signals are reproduced from the recording media again. The technology of converting the signal into the original analog signal using a D/A converter is being actively researched.

Such digital signals have recording density, frequency characteristics,
In order to improve the code error rate and the like, it is common that the signal is further digitally modulated and recorded on the recording medium. As such a digital modulation method, NRZI
(Non Return to Zero Inverse), ZM (Zero
Modulation), 3PM (Three Position)
Modulation), EFM (Eight to Fourteen)
However, a self-clock method is recommended in order to facilitate signal readout during playback. In addition, for reasons such as facilitating error correction, data signals corresponding to audio signals to be recorded and reproduced are divided into multiple frames, and frame synchronization signals, address signals, code correction signals, etc. are controlled for each frame. The signal is added and recorded.

Such digital signals are recorded on a disk in a format as shown in FIG. 1, for example. That is, one frame consists of, for example, 588 channel bits, and the data signal is converted into 14 channel bits every 8 bits using the EFM method according to a predetermined conversion table (not shown), and adjustment bits of 3 channel bits are added. With 17 channel bits as one unit, when it is 1, there is an inversion from a logic H level to a logic L level or vice versa, and when it is 0, there is no inversion, that is, it is recorded in the form of NRZI.

At the beginning of each frame, the first channel bit is 1, the second to 10th channel bits are 0, and the 11th channel bit is 0.
The frame synchronization signal is recorded so that the channel bit is 1, the 12th to 21st channel bits are 0, and the 22nd channel bit is 1. Control signals are placed at predetermined positions of the 588 channel bits using this frame synchronization signal as a reference. Throughout the signal processing, signal processing is performed such that 2 or more and 10 or less 0's are placed between 1's. That is, the minimum inversion interval is 3T (T is the period of one channel bit) and the maximum inversion interval is 11T. Furthermore, in parts other than the frame synchronization signal, the maximum inversion interval is not set twice in succession. Note that whether the frame synchronization signal starts with a positive inversion from L to H or a negative inversion from H to L depends on the state of the signal immediately before that, and is not constant.

In addition, in locations where the musical sound data has a fixed pattern equivalent to zero level (silence), such as between so-called songs, or in the lead-in and lead-out portions on the outermost and outermost peripheries of the disc, the EFM modulated signal is, for example, 7T,
The signal is inverted every 3T and 7T, resulting in a time-series signal containing many repeating waveforms with one period of 17T. The signal obtained by differentiating and full-wave rectifying this modulated signal contains, in addition to the bright line spectrum at the clock frequency, so-called spurious signals with a considerably high energy level at frequencies that are integral multiples of 1/17 of the clock frequency. has.

In such a disc playback device, it is necessary to extract a clock in order to convert (read) a digital modulation signal into a logical pattern of 1s and 0s. By rectifying the clock frequency, the bright line spectrum of the clock frequency is extracted and supplied to a clock extraction circuit consisting of a phase-locked loop (PLL) or the like. The clock is also compared with a reference signal of a predetermined frequency, and the difference signal is used to control the rotation of the disk. However, a clock extraction circuit such as a PLL is generally unable to extract the clock when the bright line spectrum of the input signal deviates significantly from the correct frequency. Therefore, at startup,
On a disk where signals are recorded so that the linear velocity is constant, when the rotational speed of the disk is significantly different from the predetermined speed, such as when the pickup is moved greatly in the radial direction of the disk to search for a predetermined address. If this happens, there is a risk that it will not be possible to extract the clock. Furthermore, even if the emission line spectrum of the clock frequency component is relatively close to the correct frequency, if it is not a single emission line spectrum but accompanied by spurious, the spurious is closer to the true clock frequency. If so, there is a risk that the clock extraction circuit will be erroneously tuned to that spurious signal.

The present invention was made in view of the above situation, and an object of the present invention is to provide a disk rotation servo device that controls the disk to a substantially appropriate rotational speed even when the clock cannot be extracted, thereby making it easier to extract the clock. shall be.

Embodiments of the present invention will be described in detail below with reference to the drawings.
FIG. 2 is a block diagram of a disk rotation servo device, in which 1 is a disk rotated by a motor 2, and a digital modulation signal is recorded, for example, so that the linear velocity is constant. 3 is a pickup for reproducing the digital modulation signal recorded from the disk 1, and the RF output signal thereof is waveform-shaped by a waveform shaping circuit 4 and then supplied to a synchronization signal detection circuit 5. The synchronization signal detection circuit 5 includes, for example, a retriggerable mono multivibrator (MMV) 6 that is triggered by a positive inversion of an input signal and outputs a logic L signal for a predetermined period _T0 , and a retriggerable mono multivibrator (MMV) 6 that is triggered by a negative inversion and outputs a logic L signal for a predetermined period T0. a retriggerable mono multivibrator (MMV) 7 that outputs a logic L signal during ₀ ;
It is composed of an OR gate 8 which receives the output signals of MMV6 and MMV7. The predetermined period T ₀ is the frame synchronization signal period (double the maximum inversion interval) 22T
(strictly speaking, 21T<T ₀ ≦22T). The output of the synchronization signal detection circuit 5 is, for example, a retriggerable or non-retriggerable type mono multivibrator (MMV) that emits a logic H output signal for a predetermined period _T1 upon positive inversion of the input signal.
9 and a low-pass filter 10 that integrates the output signal of the MMV 9. MMV9 predetermined period
_T1 is set smaller than the period of the frame synchronization signal (for example, 163 μs if the frequency of the frame synchronization signal is 7.35 KHz). The output signal of the F-V conversion circuit 11 is supplied to a voltage comparator circuit 12, and a comparator 13
is compared with a predetermined reference voltage of the reference voltage source 14, and the output signal of the comparison circuit 12 is supplied to the motor 2, and the linear velocity of the disk 1 is controlled to be constant, for example (of course, if the disk 1 rotates at a constant speed) If the number of revolutions is recorded, the number of revolutions is controlled to be constant).

Next, its operation will be explained. The RF signal reproduced from the pickup 3 is waveform-shaped by a waveform shaping circuit 4 to become a substantially rectangular wave as shown in FIG. MMV6 is triggered by a positive inversion from L to H, and MMV7 is triggered by a negative inversion from H to L, each outputting an L signal for a period T ₀ . The period T ₀ is approximately equal to the period 22T of the frame synchronization signal, and the period from one positive inversion to the next positive inversion or from one negative inversion to the next negative inversion in each frame is frame synchronization. Since the case in the signal is the longest, now disk 1
If the relative speed of is slower than the normal predetermined speed v ₀ , then at least the period during which the frame synchronization signal exists
During 22T, the output signal of MMV6 or 7 changes from L to H.
Flip to . This reversal occurs via OR gate 8.
Trigger MMV9 (of course, if MMV9 has two input terminals and one input terminal is supplied with an L signal (or H signal), the other input terminal is supplied with a signal from L to H (or from H to L). ) If it is a type that essentially has a built-in OR gate that is triggered when an inverted signal is input,
The outputs of MMV6 and 7 can be input directly to MMV9, and the OR gate 8 can be omitted).
When triggered, the MMV 9 outputs an H signal for a predetermined period _T1 , and the output signal is integrated by the LPF 10 and compared with a reference voltage. Assuming that the reference voltage is set to a voltage V ₀ corresponding to the voltage generated by the F-V conversion circuit 11 when disk 1 is running at the normal speed V ₀ , the speed of disk 1 is now normal. Since the speed of V is slower than ₀ , comparator 13
e.g. issues a positive output signal and increases the rotational speed of the motor 2.

On the other hand, if the speed of disk 1 is faster than the regular speed V ₀ , MMV6 or 7 is the timing period.
It is retriggered by a positive or negative inversion after the frame synchronization signal before the end of T ₀ , and from then on it again performs the timing operation for the period T ₀ , so its output remains an L signal. Therefore, MMV 9 is not triggered, the output of F-V conversion circuit 11 becomes less than the reference voltage, comparator 13 issues a negative output signal, for example, and reduces the rotational speed of motor 2.

In this way, the motor 2 is controlled so that the disk 1 rotates at the normal speed _V0 .

However, if the rotation of the disk becomes extremely slow, for example by 4.5%, and a portion with a playback period of 21T was once played back at 22T, the synchronization signal detection circuit 5 will detect this as a frame synchronization signal. , the servo is applied using the rotational speed at this time as the normal rotational speed, and there are multiple stable points for the servo.

Therefore, by narrowing the pulse width obtained from the synchronization signal detection circuit and setting it so that the probability of triggering the next stage MMV9 is about 1/2, the reference voltage can be set to the voltage V corresponding to the normal speed V ₀ . It can be approximately 1/2 of ₀ .

To explain this in detail, MMV9 naturally has a higher probability of being triggered when a wide pulse is applied, and conversely, the thinner the pulse, the lower the probability of being triggered. Therefore, the probability that MMV9 will be triggered by a thin pulse generated every frame synchronization signal at normal rotation speed is approximately 1/1.
2, the error voltage is designed to be zero volts.

In other words, the output of LPF10 indicates the average level of the output of MMV9, and if MMV9 is triggered with a probability of 1/2 at the normal rotation speed, the F-V conversion output is 1/2V ₀ Therefore, the comparison voltage _V0 can be set to 1/ _2V0 .

If the rotation speed becomes even slightly slower, the pulse width generated by the synchronization signal detection circuit 5 becomes larger, so the probability of triggering the MMV 9 becomes higher, and the F-V conversion output also becomes larger. A positive voltage is obtained from 13 to control the motor to rotate quickly. Therefore, since the rotation speed is controlled by following the slight delay in the rotation speed,
The servo will no longer become stable at other servo stability points (for example, the point where it becomes stable at 21T).
On the other hand, when the rotation speed becomes even slightly faster, the pulse obtained from the synchronization signal detection circuit 5 becomes extremely thin, and the probability that MMV9 is triggered becomes extremely low. level) decreases, and the comparison output generates a negative voltage to control the motor rotation to slow down.

FIG. 3 shows another embodiment of the synchronizing signal detection circuit 5, in which the input signal is supplied to the positive inversion detection circuit 15, and when positive inversion is detected, the normally open switch 17 of the charging/discharging circuit 16 is instantaneously closed. constant current source 18
This allows the capacitor 19 to be charged from the initial state. (Of course, charging may be performed via a resistor using a constant voltage source.) The charging voltage of the capacitor 19 is inputted to a comparator 21 of a comparator circuit 20 and is compared with a reference voltage of a reference voltage source 22. The charging/discharging circuit 16 and the comparison circuit 20 constitute a timer circuit compatible with MMV6. When the charging voltage becomes equal to or higher than the reference voltage, an output is generated via the OR gate 8. The input signal is also supplied to the negative inversion detection circuit 23, and the switch 2
4. A charging/discharging circuit 27 having a constant current source 25 and a capacitor 26, and a comparison circuit 30 having a reference voltage source 28 and a comparator 29 are provided.

Next, the operation will be described. When a positive inversion occurs in the input signal, the positive inversion detection circuit 15 detects it and outputs a pulse. The switch 17 is instantaneously closed by this pulse, and after the electric charge stored in the capacitor 19 is instantaneously discharged, the constant current source 1
8 charges the capacitor 19 again. The reference voltage of the reference voltage source 22 is set approximately equal to the voltage when the capacitor 19 is charged during the period _T0 , so that the arrival of a positive inversion after the frame synchronization signal is equal to that of the previous positive inversion. If it is within the period T ₀ after arrival, the charging voltage of the capacitor 19 does not exceed the reference voltage,
The output of the comparator 21 remains the L signal, but the period
If it is after T ₀ , it exceeds the reference voltage and the comparator 2
The output of 1 is inverted from an L signal to an H signal. Further, when a negative inversion occurs in the input signal, the negative inversion detection circuit 23, charge/discharge circuit 27, and comparison circuit 30 operate in the same manner.

FIG. 4 shows an embodiment of the positive inversion detection circuit 15 in FIG.
The signal is supplied to one input terminal of , and is supplied to the other input terminal via an inverter 32 and an integrating circuit comprising a low resistor 33 and a capacitor 34 .

To explain the operation with reference to FIG. 5, point P
When a positive inversion occurs, the inverter 32 is connected to point Q.
A negative inversion occurs. Since this negative inversion appears at point R according to the time constant determined by the resistor 33 and capacitor 34, the AND gate 31
An H signal is applied to the input terminal when a positive inversion of the input signal occurs, and a pulse is output to the point S. When a negative inversion occurs in the input signal, both inputs become L signals, and the AND gate 31 does not generate an output pulse.

FIG. 6 shows an embodiment of the negative inversion detection circuit 23 in FIG. The signal is supplied to the other input terminal of the AND gate 36 via a circuit.

To explain the operation with reference to FIG. 7, point P
When a negative inversion occurs, a positive inversion appears at point Q due to the inverter 35. On the other hand, a positive inversion appears at point R according to a time constant determined by resistor 37 and capacitor 38. Therefore, and gate 2
3, a pulse is output to the conduction point S for a period determined by a time constant. When a positive inversion arrives at point P, both inputs of the AND gate 36 become L signals, so no pulse is output.

As described above, in the present invention, one of the positive and negative inversions (transitions) of the digital signal in which the synchronization signal is recorded in the form of two consecutive inversions at the maximum interval.
Trigger the timer circuit to start the timing operation from the initial state every time the signal is input, and cause the timer circuit to generate an output if the next inversion does not arrive within a period approximately twice the maximum inversion interval. Since the synchronization signal is detected and the rotation of the disk is controlled by this output, it is possible to control the rotation of the disk even if the clock is not extracted, and there is little possibility that it will be difficult to extract the clock.
In particular, by setting the reference value to approximately 1/2 of the normal frequency of the synchronization signal, it becomes possible to extract the clock more accurately.

[Brief explanation of drawings]

The figures are all related to the present invention; Fig. 1 is a waveform diagram of a signal format, Fig. 2 is a block diagram of a disk rotation servo device, Fig. 3 is a synchronization signal detection circuit diagram of another embodiment, and Fig. 4 is a diagram of a synchronous signal detection circuit of another embodiment. FIG. 5 shows a detailed circuit diagram of the positive inversion detection circuit, FIG. 5 shows its waveform diagram, FIG. 6 shows a detailed circuit diagram of the negative inversion detection circuit, and FIG. 7 shows its waveform diagram. 1... Disk, 2... Motor, 3... Pickup, 5... Synchronous signal detection circuit, 11... F-
V conversion circuit, 12...comparison circuit.

Claims (1)

[Claims] 1. Reproducing a digital signal from a disk, including an analog signal converted into a digital signal that is inverted at a predetermined position by PCM or the like, and a digital signal as a synchronization signal that is inverted twice at the maximum interval, Each time one of positive or negative inversions is input, the timer circuit is triggered to start timing operation from the initial state each time, and the next inversion of one of them is input during a period approximately twice the maximum inversion interval. A disk rotation servo device, characterized in that the timer circuit generates an output when the timer circuit is not used, the average level of the output is compared with a predetermined reference value, and the rotation of the disk is controlled according to the comparison output. 2. The disk rotation servo device according to claim 1, wherein the reference value corresponds to a frequency that is approximately 1/2 of the normal frequency of the synchronization signal. 3. The average level of the output of the timer circuit is a signal obtained by frequency/voltage conversion of the output of the timer circuit, and the reference value is a predetermined reference voltage. The disk rotation servo device according to item 2. 4. The frequency/voltage conversion includes a mono multivibrator triggered by the output of the timer circuit;
4. The disk rotation servo device according to claim 1, further comprising a low-pass filter that outputs an average level of the output of the mono-multivibrator. 5. The timer circuit includes a first means for generating the output based on the positive inversion, a second means for generating the output based on the negative inversion, and a logic feather of the outputs of both the means. A disk rotation servo device according to any one of claims 1 to 4, characterized in that it has means. 6. The disk rotation servo device according to any one of claims 1 to 5, wherein the timer circuit is comprised of a retriggerable mono-multivibrator. 7. The timer circuit is characterized by comprising a capacitor that is charged and discharged, a switch that controls charging and discharging of the capacitor, and a comparison circuit that compares the charging voltage of the capacitor with a predetermined reference voltage. A disk rotation servo device according to any one of claims 1 to 5.