JPS6083258A - Disk driving system - Google Patents

Abstract

PURPOSE:To drive securely different kinds of disk and a disk recorded at a different linear speed at a constant linear speed by varying the frequency division ratio of a frequency divider which divides the frequency of a data signal detected from a disk, and making comparison in phase between the frequency division output of the frequency divider and a reference frequency signal, and controlling a motor. CONSTITUTION:Frequency division ratio data from a frequency division ratio varying means 9 which increases or decreases the frequency division ratio of a programmable frequency divider 11, one by one, through the operation of a break key is inputted to the programmable frequency divider 11 through an OR circuit 12. The frequency division ratio data is stored in an ROM13 and a frequency division ratio is set in the programmable frequency divider 11 with the break key 14. The output frequency of a reference frequency oscillator 15 is divided by 160 through a frequency divider 16, and the reference frequency signal is supplied to a phase comparing circuit 17. The phase comparing circuit 17 makes comparison in phase and frequency between the reference frequency signal and the frequency-division output of a data signal S2 detected from the disk 2 by the programmable frequency divider 11, to generate a difference output in phase and frequency, controlling the rotating speed of the motor 20.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a disk drive system that provides good playback characteristics.

(b) Conventional technology Compact disc digital audio systems, which are configured to record information signals such as video or music in bits on a disc and read and reproduce the recorded information using radiation such as a laser beam, have a recording density. In order to increase the speed, information signals are recorded at a constant linear velocity. For this reason, regeneration +4
Even at rζ, the disk must be driven at a constant linear velocity.

By the way, according to the data signal encoding method of the compact disc digital audio system, the data signal reproduced from the disc has a frequency of approximately 400 to 500 KHz centered around approximately 430 KHz, as shown in Figure 1.
Hz (distributed vertically (half width: lower limit 355K)
Hz, upper limit 565KHz).

This is a compact disc, digital audio,
This is based on the encoding method of the system, and the frequency component of the center frequency of 4:0 KHz is a signal corresponding to the size of 5 bits of the reference frequency signal.

Therefore, if you look at it continuously, it will be 430KH from the disk.
The frequency component of z will be reproduced stochastically with a certain probability of occurrence.

Therefore, the applicant focused on this 430KHz frequency spectrum and determined the reference oscillation frequency (4,3218MHz).
) 27KH2 oscillation frequency obtained by dividing the signal by 160,
A phase comparator compares the phase with a frequency of about 27 KHz, which is obtained by dividing the frequency of 430 KHz by 16, and uses the error voltage to drive the disk at a constant linear velocity.

Figure 2 “ is the reference oscillation frequency (4!l 218MHz)
This is a circuit diagram for driving a disk at a constant linear velocity using a frequency divider that divides a signal by 160 and a frequency divider that divides a data signal reproduced from a disk by 16.

In the drawing, a data signal (SO) detected by a pickup (80) is amplified by a high frequency amplifier (81) (Sl) and then passed through a waveform shaping circuit (82) (S2).
, is input to a programmable frequency divider (86). next(
84) is a phase comparator, and the reference frequency (4,3218MH
z) Oscillator (85) (7) The output of the frequency divider (86) that divides the frequency by 160 and the ROM (88) with the frequency division ratio set to "16" by operating the play key (87). Programmable frequency divider (86
) and compare the phase and frequency with the output of

Then, in this phase comparator (84), until the divided output of the programmable frequency divider (84) matches the divided output of 27 KHz of the reference frequency oscillator (85), in other words, the data of 430 KHz is input from the disk (90). The phase comparator (84) generates an error voltage until a signal is detected by the pickup (80). This error voltage is converted into a direct current through a low-pass filter (89) and then supplied to a motor drive circuit (92) that drives a motor (91), which drives the motor (91) and drives the disk (90). Since it drives β
Ru.

In this way, the disk (90) was driven at a constant linear velocity.

However, it has been found that the frequency spectrum distribution of the data signal shown in FIG. 1 differs depending on the type of disc and also differs depending on the information signal such as recorded music.

Furthermore, the disk records information signals at a linear velocity of 12 to 1.4.
Since it is standardized to be recorded between m/s, the center frequency of the data signal detected on the disc may differ from 4KHz.

Therefore, if the frequency division ratio of the programmable frequency divider (83) that divides the frequency of the data signal detected from the disk is fixed to a constant value, an error voltage will continue to be generated from the phase comparator (84), and the disk will not function properly. It cannot be expected to drive at a constant linear velocity.

In addition, the demodulation circuit (93) generates a demodulation clock frequency (free-running oscillation frequency of the voltage controlled oscillator with a center frequency of 4,3218 MHz) signal (
S3) Detect the length of the data signal (S2) based on vc,
Binary data is output according to the length of the data signal (S2), but if the disk (9o) is not driven at a constant linear velocity, the length of the data signal (S2) will change, making demodulation impossible. .

(c) Purpose of the Invention The present invention has been made in view of the above-mentioned drawbacks, and is an attempt to reliably drive different types of discs and discs recorded at different linear velocities at a constant linear velocity.
The objective is to obtain good reproduction characteristics.

B) Structure of the Invention The present invention makes the frequency division ratio of a frequency divider that divides the frequency of a data signal detected from a disk variable, and divides the frequency division output of the frequency divider that frequency divides this data signal and a reference frequency signal. The motor is controlled by phase comparison, and the disk is driven at a constant linear velocity.

(e) Embodiment FIG. 6 is a circuit diagram showing a disk drive system according to the present invention.

(1) is a pickup that emits a laser beam to the disk (2) and reproduces the information recorded on the disk (2).The data signal (SO) detected by the pickup (11)
is supplied to the waveform shaping circuit (4) via the high frequency amplifier circuit (3) (Sl), and then to the demodulation circuit (5) and the demodulation clock signal generation circuit (6).

In the demodulated clock signal generation circuit (6), the data signal (S
2) demodulation clock frequency (4,3218MH
z) is configured to generate a signal (S3), and the generated pulse output is supplied to a demodulation circuit (5), thereby
The demodulation circuit (5) detects the length of the data signal (S2) based on the demodulated clock signal (Sl), and
) outputs binary data according to the length. The data signal (SO) detected by the pickup (1) is transmitted to the reference station eti (4,'6218 MHz) depending on the signal level.
), and the length of the data signal (SO) from the p1 demodulation circuit (5).
That is, binary data corresponding to the signal level is output.

(7) is a digital-to-analog converter that converts the binary digital data from the demodulation circuit (5) into an analog signal, and the analog signal is amplified by an amplifier (not shown) and then reproduced by a speaker. (8) is a lock detection circuit which is supplied with a data signal (SO) and a demodulated clock signal (S6) synchronized with the data signal (So), and detects rotation at a constant linear velocity. Then, when the data signal (S2) becomes an integral multiple of the demodulated clock signal (the oscillation frequency of the voltage controlled oscillator that oscillates in the vicinity of 45213 MHz), the output becomes "H".
occurs.

Next, in (9), the frequency division ratio of the programmable frequency divider Uυ is changed from the minimum "10" to the maximum [52,
Jt is a frequency division ratio variable means that increases or decreases the frequency by 1, and the frequency division ratio data from this frequency division ratio variable means (9) is inputted to a programmable frequency divider; 1υ via an OR circuit 2.

On the other hand, 03 is a ROM in which division ratio data "5" is stored.
By operating the stop key I, the frequency division ratio "5" is set in the programmable frequency divider 0η.

A reference frequency oscillator that oscillates the next K (tFjH reference frequency (4,3218MHz) signal), and its output or frequency divider f
A reference frequency signal of about 27 KHz, which is divided by 160 from t61 K, is supplied to the phase comparator circuit (171).

This phase comparator circuit (L7) uses a reference frequency signal of about 27 KHz and a disk (
2) The output of the data signal (S2) detected from
z) to generate a phase and frequency error output of the frequency-divided output of the data signal (S2).

Then, this phase error output is converted into a direct current by the reducing material wave j (Y), and then supplied to the motor drive circuit (19) that drives the motor (201), which controls the rotational speed of the motor +21j.

Next, FIG. 4 shows the configuration of a frequency division ratio variable means (9) for varying the division ratio of a programmable frequency divider circle that divides the data signal (S2) detected from the disk 12), which is the essential part of the present invention. FIG.

In the figure, (90) is a division ratio setting counter for setting the division ratio of the programmable frequency divider aυ, which is composed of an up/down counter and is controlled by pulses from the pulse generation circuit (91). There are things that will be done. (92) is a ROM (read only memory) in which the minimum and maximum values of the division ratio of the data signal (S2) detected from the disk (2) are set, and the output is the counter for setting the division ratio. (90) and a matching circuit (93) K, which will be described later, are connected to each other via a gate circuit (94×95).

(96) arbitrarily controls the counting direction of the frequency division ratio setting counter (90), and when counting in the upward direction toward the maximum value of the division ratio stored in ROM (92) K, the maximum frequency division ratio is set in the ROM. When counting down toward the minimum value of the division ratio stored in (92), the minimum division ratio is set to RO
This is an amplifier Φ down mode selection circuit that controls the gate circuit (95) so as to output from M (92) to the matching circuit (96), and is composed of a clip-flop.

(97) is a sawtooth wave sweep that varies the frequency division ratio, and only when the minimum frequency division ratio or maximum frequency division ratio is reached, the maximum frequency division ratio or minimum frequency division ratio is stored from the ROM (92). Setting counter (90) Gate circuit (to set K)
This is a sawtooth wave sweep control circuit that controls 94) and is composed of an AND circuit.

The up/down mode selection circuit (96) is connected to a control signal (UPλ) for varying the division ratio in the up direction and a control signal (DN) for varying the division ratio in the down direction and a triangular wave and sawtooth wave sweep switching terminal (98). ) and is connected to be controlled by the matching output from the matching circuit (96). Also, the sawtooth wave sweep control circuit (97)
is the output of the up/down mode selection circuit (96),
It is connected so as to be controlled by the switching operation of the triangular wave and sawtooth wave sweep switching terminal (98) and by the matching output from the matching circuit (96). Therefore, when the division ratio is counted at the minimum division ratio or the maximum division ratio of 1 in the programmable frequency divider [υ], the output from the matching circuit (93) is output from the up/down mode selection circuit (96) and The state of the sawtooth wave sweep control circuit (97) is automatically reversed, and counting of the division ratio is started in the opposite direction or from the beginning.

Next, the operation of the present invention having such a configuration will be explained. In this practical example, it is assumed that the minimum and maximum values of the frequency division ratio stored in the ROM (92) are set to "10" and "62".

First, the operation in a triangular wave sweep state where the switching terminal (98) is connected to the voltage (+V) will be explained.

Now, assuming that a control signal (UP) in the shift direction is output by pressing the play key (Iω), the up/down mode selection circuit (96) is not in the up mode, and the division ratio setting counter ( 90) operates as an up counter.Also, since the gate circuit (95) opens at the same time, the ROM
From (92) to -number circuit (96), the maximum frequency division ratio is "62"
is output. Further, the gate circuit (94) is opened and the minimum division ratio "10" is set in the division ratio setting counter (9o). The frequency division ratio setting counter (9o) counts up for each pulse applied from the pulse generation circuit (91), and changes the frequency division ratio of the programmable frequency divider αυ.

On the other hand, before the play key 11G is suppressed, the disk (2) has stopped rotating, and the motor QQl is not rotating at the end, so the data signal (So) cannot be detected from the disk (2). , or even if it is detected (due to vibration, etc.)
Since the frequency is low, it is not processed as data and is sent to the lock detection circuit [
The output of 81 is rLJ.

However, the programmable frequency divider (1) J has a frequency division ratio variable means + 9, and the frequency division ratio is increased by 1 from "1o" to "6".
A branching ratio that changes up to 2 is set over time, but
Since the data signal (So) is not detected from the disk (2), the data signal (S4) frequency-divided by the programmable frequency divider j is the frequency-divided output of the reference frequency oscillator [lj].
The frequency is lower than 27KHzJ. Therefore, in the phase comparison circuit ση, a programmable frequency divider (1
Since the frequency of the divided output of 1) is low, a phase error voltage is generated to increase the rotation speed of the motor (2G). Therefore,
A driving voltage is supplied to the motor via the low-pass filter and the motor driving circuit σ9. That is, motor 4 is activated.

As the motor 4 is started and the rotational speed gradually increases, a signal with a high frequency is detected from the pickup (1).

Therefore, as the rotational speed of the motor (to) increases, the frequency division output from the programmable frequency divider (Iυ) changes to phase comparator 0.
It is now supplied to η.

In the programmable frequency divider αυ, the frequency division ratio is increased by the frequency division ratio variable means (9), but the minimum frequency division ratio is "10".
Since the frequency division output of the programmable frequency divider S2 that divides the data signal (S2) is lower than the frequency division output of the reference oscillator α9, the rotation speed of the motor 4 further increases from 32 to the maximum frequency division ratio of 32. I'll go.

For example, if the center frequency of the currently rotating disk (2) is 405 KH, z, and the frequency division ratio of the programmable divider is "15", the divided output will be 27K.
Hz, no error voltage is generated from the phase comparator (17), and the disk (2) rotates at a constant linear velocity.

At this time, the lock detection circuit (8) detects the data signal (SO) from the disk [21] with the correct length, so that the length of the data signal (S2) is an integral multiple of the demodulated clock signal. Lock detection output "H" is output.

Therefore, the division ratio "15" is set to the division ratio setting counter (90) K once the pulse generation circuit (91) is stopped.

Therefore, the disk (2) is driven at a constant linear velocity.

Note that the frequency division ratio set in the frequency division ratio setting counter (90) is equal to the maximum frequency division ratio "32" set in the coincidence circuit (93) Ic.
'', the -number circuit (96) generates an output, the up/down mode selection circuit (96) switches to the down mode, and the division ratio setting counter (90) operates as a down counter (90). It can be switched to or,
The gate circuit (95) is opened, and the minimum division ratio "10" is output from the ROM (92) to the minus number circuit ('93) Ic. From now on, the pulse generation circuit (91) will count down and sweep from the maximum frequency division ratio to the minimum frequency division ratio using the pulses from the pulse generation circuit (91). And when the minimum division ratio is reached,
This time, the sweep direction is automatically reversed and a triangular wave sweep is performed.9
゜Although the frequency division ratio set in the frequency division ratio setting counter (90) is configured to increase or decrease by 1 from "10" to "62", the division ratio is It is even more preferable to finely adjust the value.

Furthermore, when the play key u1 is pressed, the control signal (D
N), the sweep of the division ratio will start from the maximum division ratio "62" and the minimum division ratio "10".
When the frequency division ratio reaches the maximum frequency division ratio of 1-32J, the frequency division ratio is varied toward the maximum frequency division ratio of 1-32J.

Next, when the switching terminal (98) is grounded, the frequency division ratio variable means (9) is switched to sawtooth wave sweeping.

If the play key 11 is operated in this state, the up/down mode selection circuit (96
) is outputted with an up direction control signal (UP). Then, when the maximum frequency division ratio [2J i/C is reached, - several circuits (9
3) The sawtooth wave sweep control circuit (97
) is opened, the write signal (99) is sent through the gate circuit (94) k, and the division ratio setting counter fi (9
0) The minimum frequency division ratio "10" is set from icROM (92). At this time, the up/down mode selection circuit (
96) continues in the up mode, the sweep of the frequency division ratio in the up direction starts again. Therefore, when the programmable frequency divider I detects the frequency division ratio from "10" to "32" and "62", the frequency division ratio is varied from "10" to "32" again.

At this time as well, the optimum frequency division ratio is set in the programmable frequency divider U based on the output of the lock detection circuit (8).

Furthermore, if the control signal (DN) in the down direction is configured to be output by operating the play key 110, the frequency division ratio will be changed from the maximum division ratio "62" toward "10", and the minimum division ratio "10". Upon detection of , the maximum frequency division ratio is changed again from ``32'' to the minimum frequency division ratio ``10'', and the lock detection circuit (
The optimum frequency division ratio is set in the programmable frequency divider 0.13 by the output of 8).

Next, to end the performance, press the stop key
The frequency division ratio "5" may be set in the programmable frequency divider U from OM (92). At this time, the divided output of the programmable frequency divider Uυ is approximately f30 KHz, which is much more advanced in phase and frequency than the reference frequency signal 27 KHz, which is equivalent to a faster motor speed. Since the phase comparator circuit +171 generates an error voltage that reduces the speed of the motor t201, the speed of the motor t201 is rapidly reduced, which is equivalent to applying a brake. In this way, it rapidly [(comes to a halt state.

In this embodiment, a sweep circuit capable of switching between triangular wave sweep and sawtooth wave sweep is used as the frequency division ratio variable means, but the present invention is not limited to this. Since a sawtooth wave sweep in which the frequency division ratio rapidly changes from a minimum value to a maximum value places a burden on the phase comparator, it is preferable to use a triangular wave sweep sound.

(f) Effects of the Invention According to the present invention, the frequency division ratio of the frequency divider that divides the frequency of the data signal detected from the disk is varied, and the frequency division output of the frequency divider that frequency divides the data signal is The motor is controlled by comparing the phase with the reference frequency signal, and the disc is driven at a constant linear velocity. Therefore, different types of discs and discs recorded at different linear velocities can be reliably driven at a constant linear velocity. It is possible to obtain good reproduction characteristics.

However, the means to vary the division ratio of the frequency divider that divides the data signal is to use a sweep circuit that changes the division ratio of the programmable frequency divider of the digital synthesizer receiver, and a compact disc with a tuner can be used. - A digital audio system can be easily configured, and the number of parts can be reduced because the sweep circuit can be used in common.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the frequency spectrum distribution of data signals detected from the disk, Fig. 2 is a circuit diagram showing a conventional driving method for driving a motor at a constant linear velocity, and Fig. 6 is a diagram showing a driving method for driving a conventional motor at a constant linear velocity. A circuit diagram showing the drive method of the disk,
FIG. 4 is a block diagram of a division ratio variable means for varying the division ratio, showing the main part of the present invention. (2)...Disc, (8)...Lock detection circuit,
(9)... Frequency division ratio variable means, (lυ... Programmable frequency divider, u51... Reference frequency oscillator, (17)
...Phase comparator circuit, 4...Motor Q ■1 Kubeika method

Claims (1)

[Claims] (1) The frequency division ratio of the frequency divider that divides the frequency of the data signal detected from the disk is made variable, and the phase of the frequency division output of the frequency divider that frequency-divides this data signal is compared with the reference frequency to control the motor. A disk drive system that drives at a constant linear velocity.