JPS59186109A - Digital data producing device - Google Patents

Abstract

PURPOSE:To produce an accurate digital data by applying an output of a detecting means extracting an envelope component of an input data and an output of a circuit converting the former output into a DC voltage to a level comparator so as to change over a feedback loop characteristic by the output of the level comparator. CONSTITUTION:An envelope signal outputted from a detecting circuit 19 is applied to one input terminal of the level comparator 20 as it is. This signal is divided by a voltage dividing and integration circuit 21 and integrated and converted into a DC voltage as shown in a dotted chain line and applied to the other input terminal of the comparator 20. The comparator 20 outputs an L level when the level at a point A is higher than the level at a point B and outputs an H level when lower. When a rapid level fluctuation is caused in an RF signal 11 and an output level of the detecting circuit 19 is lower than an output level of the voltage dividing integration circuit 21, the comparator outputs the H level. The H level signal is applied to a base of a transistor(TR)Q2 via a resistor R8 so as to conduct the TRQ2. Then, the resistance value of an R3 of an inverse amplifier circuit 18 is lowered and the gain is varied. Thus, the DC level of the RF signal is changed and the digital data always accurate is produced.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a CD (optical compact disc), for example.
The present invention relates to a digital data generation device suitable for use in a digital audio disc (DAD) playback device or the like.

[Technical background of the invention]

Recently, in the field of audio equipment, PCM (pulse code modulation) is being used to achieve as high fidelity reproduction as possible.
Digital recording and playback methods using technology are being adopted. This technology is called digital audio, and the audio characteristics do not depend on the characteristics of the recording medium and are far superior to those using conventional analog recording and playback methods. This is because it is established in principle.

In this case, the system that targets all disks as a recording medium is called a DAD system, and various recording and reproducing methods have been proposed such as optical, electrostatic, and mechanical. Even if all the methods of Izun are adopted, as a playback device that embodies the method, it will still be able to satisfy advanced control functions and performance not found in conventional Son. That is what is required.

In other words, if we take the CD system as an example,
A specified EFM (Eight to Fou) is placed on a transparent resin disk with a diameter of 12 [tyn3, thickness 1.2 Cam].
rfeenModulation P of the audio signal to be reproduced in the form with modulation and interleaving
Approximately 500 discs are coated with thin metal bullets that form bits (irregularities with different reflectances) corresponding to the digitized data converted into commercials using the CLV (constant linear velocity) method.
A device that is driven to rotate at a variable rotational speed of ~200 [r, p, m), and has a built-in semiconductor laser and photoelectric conversion element, and reproduces it in a linear tracking method from the inner circumference side toward the outer circumference extension using a dimensional pickup. However, the track pitch of this disc is 1.6 [μm], and the program area (radius 25 to 58 [m]) contains a huge amount of information that can be played in stereo for about an hour on one side. This can easily be seen from the fact that their index data and the like are recorded in the lead-in area (radius 23 to 25 [m]).

By the way, in the above-mentioned CAD playback device, first the f'L* signal (hereinafter referred to as RF) obtained from the optical pickup is
A data slicing circuit separates the double signal) into an unnecessary analog component and a necessary data component C (hereinafter referred to as an EFM signal), and this EFM signal is guided to a synchronous clock regeneration PLL circuit (phase synchronized loop 13 circuit). By generating a synchronous clock signal synchronized with the EFM signal and matching the phase of the EFM signal with this synchronous clock signal, digital data that can be used for demodulation and reproduction processing is generated.

Here, the digital data recorded on the above disc is
In order to facilitate the demodulation and reproduction process described above, digital modulation is applied so that the DC component becomes "0". In the above explanation, as this digital modulation, EF'M
A modified method is used.

Figure 1 shows a conventional digital data generation system as described above.
It shows. That is, n supplied to input terminal 1
The above RP multiplied signal is supplied to one input terminal of the level comparator 13 via the variable DC bias amplifier 12, and is supplied to the other input terminal of the level comparator 13.A7'C slice level (0 level) By comparing the level with
It is converted into a rectangular EFM signal (digital data).

In this case, the level comparator 13 outputs an H level (Vl) when the RF signal level is higher than the slice level,
When the RF (F!r level) is lower than the slice level, it outputs L level (0 level).And,
The output signal (digital data) of the level comparator 13 is supplied via an output terminal 14 to a circuit (not shown) that performs the demodulation and reproduction process.

Further, the digital data outputted from the level comparator 13 is converted into a current voltage by an integrating circuit 15 consisting of a resistor R1 and a capacitor C1.

In this case, the direct current voltage output from the integrating circuit 15 is such that the direct fM component of the digital data is "0".
” If it is correctly generated so that it is pointed, it will be (vy2).

The output of the integrating circuit 15 is fed back to the amplifier 12 via an inverting amplifier circuit 18 formed from an operational amplifier 16 and an integrating circuit 17 including a resistor R2 and a capacitor C2. This inverting amplifier circuit 18 is an integral circuit 1
The gain is determined according to the constant of 7, and when the output level of the integrating circuit 15 is (vV2), it outputs O level, and the output level of the integrating circuit 15 fluctuates from (■4). It outputs a voltage corresponding to that variation. Then, the DC bias of the amplifier 12 is varied by the output voltage from the inverting amplifier circuit 18.
The level of the F-fold signal changes as a whole.

For this reason, the digital data output from the level comparator 13 is correctly generated as the DC component becomes "0", and the output voltage of the inverting amplifier circuit 18 is also "0".
”, and the center level of the RF multiplied signal 6 becomes 10”, and the level comparator 13 outputs “
Slice at level 0. Furthermore, if a fluctuation in the RF multiplied signal level occurs due to the influence of disturbance, for example, the DC component of the digital data output from the level comparator 13 will be
0'', and the output voltage of the integrating circuit 15 fluctuates from (V%). Then, the inverting amplifier circuit 18
A heavy pressure corresponding to the variation in the output voltage is output, and the RF multiplied signal @flow bell is corrected so that it is at the "0" level.

Therefore, even if the RF signal level fluctuates, correct digital data such that the DC component is always "0" is generated.

[Problems with background technology]

However, in the conventional digital data generation device as described above, there is a problem in that it is impossible to make the RF multiplied signal DC level follow so as to be able to cope with both gradual level fluctuations and rapid level fluctuations of the RF multiplied signal. There is.

In other words, the followability of a series of feedback loops that feed back the digital data output from the level comparator 13 to the amplifier 12 via the integrating circuit 15 and the inverting amplifier circuit 18 is determined by the characteristics (gain, etc.) of the entire feedback loop. This is because it is determined by the frequency characteristics, etc.). Since the characteristics of this feedback loop are determined by the constant of the integrator circuit 15.17, once the constant of the integrator circuit 15.17 is determined, the feedback loop naturally follows the RF multiplied signal level fluctuation. Gender is determined uniquely.

Here, in order to make the RF multiplied signal follow a gradual level change, for example, the above gain is made small, and in order to make the RF multiplied signal follow a rapid level change, the above gain is increased.

[Purpose of the invention]

This invention was made in consideration of the above circumstances,
It is an object of the present invention to provide an extremely good digital data generation device that can always generate accurate and correct digital data without being affected by the speed of level fluctuation of input data (for example, RF signal noise).

[Summary of the invention]

That is, the present invention includes a comparing means for generating digital data by level comparing input data and a required slice level, and a DC component of the digital data is always determined based on the digital data outputted from the comparing means. A digital data generation device comprising a feedback loop for controlling the input data to a predetermined value, comprising: a detection means for extracting an envelope component of the input data; a DC voltage conversion means for converting the output of the detection means into a DC voltage; It is characterized by comprising level comparison means for comparing the levels of the output of the DC voltage conversion means and the output of the detection means, and switching means for switching the characteristics of the feedback loop based on the level comparison means. It is something.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. In FIG. 2, parts that are the same as those in FIG. 1 are indicated by the same symbol as -j=rTh, and only the different parts will be explained here. That is, assume that the RF@ signal supplied to the input terminal 11 undergoes a rapid level change as shown in FIG.
Detection circuit 1 consisting of resistors R4, R6 and capacitor C3
By performing the peak detection in step 9, an envelope component of the RF multiplied signal peak value is generated at the idle point in FIG. 2, as shown by the line in FIG. 3(b).

The envelope signal output from this detection circuit 19 is supplied as is to one input terminal of the level comparator 20, and is also supplied to one input terminal of the level comparator 20, and is also connected to the resistor R61R7 and the capacitor C4.
By dividing and integrating the voltage in a different voltage dividing/integrating circuit 21, the voltage is converted into a DC voltage as shown by the dashed line in FIG. End (second
It is supplied to point (B) in the figure. This level comparator 20d
When the level at point (4) in FIG. 2 is higher than the level at point (B) in the figure, L level is output, and when it is lower, H level is output.

Therefore, as shown in FIG. 3<8), a rapid level change occurs in the RF multiplied signal, and as shown in FIG. When the output level becomes lower than the output level of level comparator 2,
0 outputs H level as shown in FIG. 3(C).

The H level signal outputted from the level comparator 20 is supplied to the base of the transistor Q2 via the resistor Rek, and makes the transistor Q2 conductive.Then, the inverting amplifier circuit 18 The resistance value of the integrator circuit 17 that connects the resistor to the bottom of the tank is converted to the parallel composite resistance value of the resistor R3, the resistor Rs, and the resistor, and as a result, the characteristics of the feedback loop (gain in this case) is variable.

Therefore, the constants of capacitor C2 and resistor R3 should be set to a value that increases the gain of the feedback loop, and the parallel combined resistance value of capacitor C2 and resistors R3 and R9 should be set to a value that increases the gain of the feedback loop. In this case, the RF multiplier signal will follow the gradual level fluctuations and the sudden level fluctuations.
It is possible to change the F-fold signal DC level and always generate accurate digital data.

Here, assuming that there is a long shallow (gentle) level fluctuation of the above RF multiplied signal, the levels at the idle point and point (B) in Figure 2 will be as shown by the solid line and dotted line in Figure 4 (8). In other words, the level at point (4) in Figure 2 is lower than the level at point (B) only at the first point in time when the RF signal level fluctuation occurs, as shown in Figure 4 (b). The level comparator 2o outputs the H level, and from then on, the level at point CB) becomes lower than the level at the idle point in Figure 2, so that the gain of the feedback loop follows the original state. It is something that Therefore, when a long and gradual level fluctuation occurs in the RF multiplied signal, accurate digital data can be generated without being followed up with the gain of the feedback loop being small.

FIG. 5 shows another embodiment of the invention. In other words, the changeover switch 2 depends on the output of the level comparator 2o.
2, the capacitor C1 constituting the integrating circuit 15 can be switched to another capacitor C1/. Of course.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the spirit of the invention.

〔Effect of the invention〕

Therefore, as described in detail above, according to the present invention, it is possible to generate extremely good digital data that can always generate accurate and correct digital data without being affected by the speed of level fluctuation of input data (for example, RF multiplied signal). equipment can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block circuit configuration diagram showing a conventional digital data generation device, FIG. 2 is a block circuit configuration diagram showing an embodiment of the digital data generation device according to the present invention, and FIGS. 3 and 4 are schematic diagrams thereof. FIG. 5 is a block circuit diagram showing another embodiment of the present invention. 13- 11... Input terminal, 12... Amplifier, 13... Level comparator, 14... Output terminal, 15... Integrating circuit, 16... Operational amplifier, 17... Integrating circuit , 18・
... Inverting amplifier circuit, 19... Detection circuit, 2o... Level comparator, 21... Voltage integrating circuit, 22... Changeover switch. Applicant's agent Patent attorney Takeshi Suzue Examination 14- Figure 1 Figure 2 Figure 3 Figure 4 Figure 53 Figure 5

Claims (1)

[Claims] Comparing means for level-comparing input data and a predetermined slice level to generate digital data; and control so that the DC component of the digital data is always at a predetermined value based on the digital data output from the comparing means. A digital data generation device comprising a feedback loop that includes a detection means for extracting an envelope component of the input data;
DC voltage conversion means for converting the output of the detection means into a weighted voltage; level comparison means for level comparing the output of the voltage conversion means with the output of the detection means; 1. A digital data generation device comprising: switching means for switching the characteristics of the feedback loop based on the feedback loop characteristics.