JPS58111156A - Servo device for disc rotation - Google Patents

Abstract

PURPOSE:To control the rotation of a disc, by triggering a timer circuit in every input of one inversion of a digital signal, and actuating the circuit timer to output signals, when the succeeding one inversion does not reach during the period of about two times the maximum inversion interval. CONSTITUTION:If the relative speed of the disc 1 is lower than a regularly prescribed speed vo, the output signal of a triggerable monomultivibrator (MMV) 6 or 7 is inverted from ''L'' to ''H'' at least during the period when a frame synchronous signal exists. The inversion triggers an MMV 9 through an OR gate 8. Triggered, the MMV 9 outputs an H signal during a prescribed period and the output signal is integrated by an LPF 10 to be compared with reference voltage. If the reference voltage is set up to a half of the voltage Vo corresponding to the voltage generated by an F/V converting circuit 11 when the disc 1 travels at the regular speed vo, a comparator 13 outputs a positive signal to increase the rotational speed of a motor 2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a disk rotation servo device that controls the rotation of nine disks on which digital signals are recorded.

In recent years, analog signals such as audio signals are converted into digital signals of L1 or O using pulse code modulation (PCM), which are recorded in the digital signal format on recording media such as disks and tapes, and then the digital signals are converted back into the recording media. Play D／▲
A technique of converting the original analog signal into κ using a converter is being actively researched.

Such digital signals have different recording density and frequency characteristics.

In order to improve the code error rate, etc., it is common that the signal is further digitally modulated and recorded on the recording medium. As such a digital modulation method, NRZI (Nail Rs't
urn to Z@ro Inverts), ZM(
Z＠ro Modulatlon), 3 P M
(ThreePosition Modulation
), EFM (Eight to Fourt@en
liodulatton), etc., but a self-clock system is recommended in order to facilitate signal readout during playback. In addition, in order to facilitate error correction, the data signal corresponding to the audio signal that should originally be recorded and played back is divided into multiple frames, and each frame contains a frame synchronization signal, address signal, code correction signal, etc. A control signal is added and recorded.

Such digital signals are recorded on a disk in a format as shown in FIG. 1, for example. .

That is, one frame consists of, for example, 588 channel bits, which are converted into 14 channel bits every 8 bits using the aEFM data signal method according to a predetermined conversion table (not shown), and 3 channel bit adjustment bits are added to form 17 channel bits. With channel bits as one unit, when it is 1, there is no inversion to logic H level or logic L level, or vice versa, and when it is 0, there is no inversion, that is, NRZ
It is recorded in the form of I.

At the beginning of each frame, the first channel bit is 1, the second to 10th channel bits are 0, the 11th channel bit is 1, and the 12th to 21st channel bits are 0.
, the frame synchronization signal is recorded so that the 22nd channel bit is 1. Control signals are placed at predetermined positions of 588 channel bits using this frame synchronization signal as a reference. Throughout the signal processing, signal processing is performed such that 2 or more and 10 or less O's are placed between 1's. That is, the minimum inversion interval is 3T (the period of the Tut channel bit), and the maximum inversion interval is IIT. Furthermore, in parts other than the frame synchronization signal, the maximum inversion interval is not set twice in succession.

Note that whether the frame synchronization signal starts with a positive inversion from L to H or a negative inversion from H to L depends on the state of the signal just before that, and is not constant.

In addition, between so-called songs or in places where the lead-in and lead-out partial pressure sound data on the innermost and outermost edges of the disc have a fixed pattern of zero level (silence), the EFM modulated signal is, for example, 7T, 3T, 7T. 17
This becomes a time-series signal that includes many repeating waveforms with T as one period. The signal obtained by differentiating the modulated signal of ζ and performing full-wave rectification includes, in addition to the bright line spectrum of the clock frequency, so-called spurious components with a relatively high energy level at frequencies that are integral multiples of 1/17 of the clock frequency. has.

In such a disc playback device, it is necessary to extract a clock in order to convert (read) a digital modulation signal into a logical pattern of 1 and O. The bright line spectrum of the clock frequency is extracted by full-wave rectification, and is supplied to a clock extraction circuit such as a 7-point lock loop (PLL) for extraction. The clock is also compared with a reference signal of a predetermined frequency, and the difference signal is used to control the rotation of the disk. However, a clock extraction circuit such as a PLL is generally unable to extract a clock when the bright line spectrum of an input signal deviates significantly from the correct frequency. Therefore, at startup, or when the pickup is moved largely in the radial direction of the disk to search for a predetermined address in a disk where signals are recorded so that the linear velocity is constant, the rotational speed of the disk is set to a predetermined speed. If the condition is significantly different from the above, there is a risk that it will not be possible to extract the beam. Furthermore, even if the emission line spectrum of the clock frequency component is relatively close to the correct frequency, if it is not a single emission line spectrum but includes spurious, the spurious is closer to the true clock frequency. In this case, the clock extraction circuit may be erroneously tuned to the spurious signal.

The present invention was made in view of the above situation, and an object of the present invention is to provide a disk rotation servo device that controls the disk to a substantially appropriate rotational speed even if the clock cannot be extracted, thereby making it easier to extract the clock. do.

Embodiments of the present invention will be described in detail below with reference to the drawings.

Figure 2 is a block diagram of the disk rotating device.
A digitally modulated signal is recorded on the disk rotated by the disk 2) so that the linear velocity is constant, for example. Reference numeral 3 denotes a pickup for reproducing the digital modulated signal recorded from the disc 1, and its RF output signal is waveform-shaped by a waveform shaping circuit 4 and then supplied to a synchronizing signal detection circuit 5. The synchronization signal detection circuit 5 is triggered by, for example, a positive inversion of the input signal, and is -111 for a predetermined period To.
A retriggerable mono multiviprator (MMV) 6 that outputs a 1L signal, and a predetermined period T that is triggered by negative inversion.
It is composed of a retriggerable multivibrator (MMV) 7 that outputs a logic signal during the period 0, and an OR gate 8 that receives the output signals of the MMVs 6 and 7 as input. The predetermined period T is roughly the period of the frame synchronization signal (double the maximum inversion interval) 22T (strictly written, 21T<To≦2
2T) Selected. The output of the synchronization signal detection circuit 5 is, for example, a retriggerable or non-triggerable type mono-multivibrator (MMV) 9 that emits a logic H output signal for a predetermined period T upon positive inversion of the input signal;
The signal is supplied to a frequency-to-electronic EE (F-V) conversion circuit 11 comprising a low-pass filter lO that integrates the output signal of the MV9. The predetermined period T of MMV9 is the period of the 7-ray 15 synchronization signal (for example, the frequency of the frame synchronization signal is 7.35 KHz).
If so, it is set smaller than 163s1). The output signal of the F-V conversion circuit 11 is supplied to the voltage comparison circuit 12,
The comparator 13 compares it with a predetermined reference voltage of the reference voltage source 14, and the output signal of the comparison circuit 12 is supplied to the motor 2, which controls the linear velocity of the disk 1 to be constant, for example (of course, the linear velocity of the disk 1 is is controlled so that it is a constant number of rotations divided by a constant number of rotations if recorded.

Next, its operation will be explained. The nine RF signals reproduced by the pickup 3 are waveform-shaped by the waveform shaping circuit 4 to become a substantially rectangular wave as shown in FIG. MMV6 is triggered by a positive flip from L to H) and MMV7 is triggered by a negative flip from H to L (?). ) is triggered and outputs an interval signal for each period T. The period T is approximately equal to the period 22T of the frame synchronization signal, and the period from one positive inversion to the next positive inversion in the frame, or from one negative inversion to the next negative inversion, is Since the case where the frame synchronization signal is used is the longest, if the relative speed of the disk l is slower than the normal predetermined speed, the output of MMV 6 or 7 is at least during the period 22T in which the frame synchronization signal exists. The signal is inverted from high to high. This reversal triggers MMV9 via OR gate 8 (of course MMV9
has two input terminals, and one input terminal receives an L signal (or
signal) is supplied from L to the other input terminal.
If it is of the type that has a built-in OR gate that is triggered when an inverted signal is input (or from H to L), you can convert the output of MMV6.7 to MMV9. (The OR gate 8 can be omitted by allowing direct input.) When MMV9 is triggered, the predetermined period T1
During this period, an H signal is output, and the output signal is integrated by LPF10 and compared with a reference voltage. Assuming that the reference voltage is set to the voltage E V which corresponds to the voltage generated by the F-V conversion circuit 11 when the disk 1 is running at the normal speed who, the speed of the disk 1 is now normal. The speed W of
o, the comparator 13 issues, for example, a positive output signal and increases the rotational speed of the motor 2.

On the other hand, if the speed of disk 1 is faster than the normal speed νO, MMV4i or 7 will be activated by a positive or negative inversion after the 7-ray synchronization signal before the end of its tying period T. Since it is re-triggered and performs the timing operation for the period T again from that time, its output becomes tiLli.ott. Therefore, MMV9 is not triggered and F-V conversion circuit 11
The output of the comparator 13 becomes smaller than the reference voltage, and the comparator 13 issues, for example, a negative output signal, causing the motor 20 rotational speed to decrease.

In this way, the printer 2 can move the disk 1 to the normal speed ν.
It is controlled to rotate at O.

The above is the reference voltage of the reference voltage source 14 at the normal speed*? o
(Frequency of synchronization signal &)K corresponding voltage V.

This is an example in which the speed is set to 9, but in this case, 10 rotations of the disk is the normal speed υO). It cannot be detected until the reproduction period of the signal coincides with the period To (regular reproduction period of 22T). This is because the number d of pulses (inversions) per unit time outputted by the stray frame detection circuit 5 does not increase until the reproduction period of the signal of 21T coincides with the regular period T of 22T. In other words, unless the speed is reduced by about 4.5% (1/22) from the normal speed, the rotational speed of the disk 1 will not be increased.
During that time, it becomes a dead zone.

Therefore, the ninth step to further improve accuracy is to change the reference voltage to 1/2 of the normal speed [2/'' voltage corresponding to ″ru)
K can be set. In this way, the probability that the synchronization signal detection circuit 5 detects a frame synchronization signal becomes 1/2, and on average, a normal speed lI>. such that a frame synchronization signal is detected at a rate of one in two is obtained. The motor 2 is controlled as follows. If the rotational speed of the disk 10 becomes even slightly slower than the normal speed, the probability that the frame synchronization signal will be detected by the synchronization signal detection circuit 5 will be much greater than 1/2, so that it is detected that it is too slow. However, no dead zone occurs.

Of course, if the speed is even 4 earlier than the normal speed 2/-O, the probability that the frame synchronization signal will be detected by the synchronization signal detection circuit 5 will be much smaller than 172, so it is also possible to detect that the frame synchronization signal is too early. No dead zone.

FIG. 3 shows another embodiment of the synchronizing signal detection circuit 5. When the input signal line is supplied to the positive inversion detection circuit 15 and positive inversion is detected, the normally open switch 17 of the charging/discharging circuit 16 is instantaneously closed. The capacitor 19 is charged by the constant current source 18 from an initial state. (Of course, charging may be performed via a resistor using a constant voltage source.) The charging voltage of the capacitor 'II'' 19 is input to the comparator 21° of the comparator circuit 20, and is compared with the reference voltage of the reference voltage source 22. Kt is set so that the charging/discharging circuit 16 and the comparison circuit 20
This constitutes a tie 1 circuit compatible with MMV6.

When the charging voltage becomes equal to or higher than the reference voltage, an output is generated via the OR gate 8. The input signal is also supplied to a negative inversion detection circuit 23, so that when a negative inversion is detected, the circuit operates in the same way as when a positive inversion is detected as described above.
Switch 24. A charging/discharging circuit 27 having a constant current source 25, a conductor 26, and a reference voltage source 28. A comparison circuit 30 having a comparator 29 is provided.

Next, the operation will be described. When a positive inversion occurs in the input signal, the positive inversion detection circuit 15 detects it and outputs a pulse. The switch 17 is instantaneously closed by this pulse, and after the charge in the capacitor 19 is instantaneously discharged, the constant current source 18 charges the capacitor 19 again.

Is the reference voltage line of the reference voltage source 22 conductive? 19 is period T
・If the arrival of the positive inversion after the frame synchronization signal is within the interval T after the arrival of the previous positive inversion, the voltage of the condenser 19 is set to be approximately equal to the voltage when the voltage is charged to The charging voltage does not exceed the EEIi reference voltage and the output of the comparator 21 remains an L signal, but if it is after the period T, the EEIi reference voltage is exceeded and the output of the ratio @921 is reversed from an L signal to an H signal. mulberry. Further, when a negative inversion occurs in the input signal, the negative inversion detection circuit 23. The charging/discharging circuit 27 and the comparison circuit 30 operate in the same manner.

FIG. 4 shows an embodiment of the positive inversion detection circuit 15 in FIG. 3, in which an input signal is supplied to one input terminal of an AND gate 31, and an integrator circuit consisting of an inverter 32, a resistor 33, and a capacitor yf34. is supplied to the other input terminal via the input terminal.

The operation will be explained with reference to FIG. 5. When a positive inversion occurs at point P, a negative inversion occurs at point QK at the inverter 32. This negative inversion line resistance 33 and capacitor 3
Since point RKII is output according to a time constant determined by 4 and 4, an H signal is applied to the input terminal of the input gate 3102 when the positive inversion of the line input signal O arrives, and a pulse is output to point S. When a negative inversion occurs in the input signal, both inner inputs become L signals, and the AND gate 31 does not generate an output pulse.

FIG. 6 shows an embodiment of the negative inversion detection circuit 23 in FIG.
．． The signal is supplied to the other input terminal of the AND gate 36 via an integrating circuit made up of a conductor T38.

The operation will be explained with reference to FIG. 7i. When a negative inversion occurs at point P, a positive inversion appears at point Q by the inverter 35. -For force point R, resistance 37 and conduit t38
A positive inversion occurs according to a fixed time constant. Therefore, the AND gate 23 outputs a pulse to the conduction point 8 for a period determined by the time constant. If a positive inversion occurs at point PK, both inputs of the AND gate 36 become L signals, so no pulse is output.

As described above, in this case #4, each time an inversion (transition) of either the positive or negative of the digital signal is input, the synchronization signal is recorded in the form of two consecutive inversions of the maximum interval. is triggered to start the timing operation from the initial state, and when the next reversal does not arrive within a period approximately twice the maximum reversal interval, the timer circuit generates an output to detect a horizontal signal. However, since the rotation of the paper disk is controlled based on this output, the rotation of the disk can be controlled even if the clock is not extracted, so that there is little possibility that it will be difficult to extract zero cost. In particular, it is best to set the reference value to correspond to approximately 1/2 of the normal frequency of the synchronization signal, making it possible to accurately extract the clock.

[Brief explanation of the drawing]

The figures relate to the present invention; Fig. 1 is a waveform diagram of a signal format, Fig. 2 is a block diagram of a disk rotation servo device, Fig. 3 is a synchronization signal detection circuit diagram of another embodiment, and Fig. 4 5wA shows a detailed circuit diagram of the positive inversion detection circuit, 5wA shows its waveform diagram, FIG. 6 shows a detailed circuit diagram of the negative inversion detection circuit, and FIG. 7 shows its waveform diagram. 1...Disk 2...Motor 3...Pickup 5...Synchronization signal detection circuit 11...F-V conversion circuit 12... ... Comparison circuit patent applicant Pioneer Co., Ltd. Figure 5 Figure 6 Figure 7--L 305-

Claims (1)

[Claims] (A digital signal that is a digital signal that is inverted at a predetermined position by 11PCM etc. and includes a 9A/4G signal and a digital signal that is a synchronous signal that is inverted twice at the maximum interval) Each time one of positive or negative inversions is input, the tie-V circuit is triggered to start the timing operation from the initial state each time, and the next inversion is the maximum inversion interval O. If no input is received within a period of approximately 2〚, the timer @Ryuyoyo output is generated, the good signal is compared with a predetermined reference value in response to the output, and the rotation of the output disk is controlled according to the output of the comparison. A disk rotation sensor I device characterized in that: (2) the cough reference value corresponds to a frequency that is approximately 1/2 of the normal frequency of the armpit synchronization signal; The disk rotation servo device according to paragraph 1. (3) The signal corresponding to the output of the tie! circuit is
is a signal obtained by frequency/voltage conversion of the output of the circuit, and the armpit reference value is a predetermined reference voltage. (4) Frequency/voltage conversion is performed using a mono multivibrator triggered by the output of the timer circuit, a low-pass filter that integrates the 6 outputs of the mono multivibrator, and a K
A disk rotation servo device according to Patent Section 3, characterized in that it performs the following operations. (5) #Tie 1 circuit includes a first means for generating the output based on the reversal of the fault, a second means for generating the fault based on the negative reversal, and an output of both the means. Claim 1 above is characterized in that it has a means for calculating a logical sum. The disk rotating turbo device according to item 2, 3, or 4. (6) The disk rotation servo device described in Patent Items 3 and 4, X-ray ts, and 5, wherein the timer circuit is constituted by a retrigger pull mono multi-by-break. (7) The timer circuit is composed of a switch that controls the charging and discharging of the capacitor, a switch that controls the charging and discharging of the wrinkled capacitor, and a comparison circuit that compares the charging voltage of the capacitor with a predetermined reference voltage. The first claim characterized in
Section. The disk rotation servo device according to item 2, 3, 4, or 5.