JP2852052B2 - Decoding circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an automatic phase adjustment method for automatically adjusting a phase relationship between two signals to an optimum state.

[Conventional technology]

In a system such as a magnetic disk drive, a decoding circuit used when reproducing and decoding a recording signal is a conventional sixth-order decoding circuit.
The block configuration shown in the figure is general. The decoding circuit includes a phase synchronization circuit 1, a tapped delay line 8, a latch 1, and a decoder 3, and decodes a reproduced signal. Further, the phase synchronization circuit 1 includes a phase comparator 51, a charge pump 52, a loop filter 53, and a voltage controlled oscillator (hereinafter abbreviated as VC) 54. When reproducing and decoding a recording signal, the reproduction signal 11 is input to the phase synchronization circuit 1. The phase comparator 51 compares the phase of the reproduction signal 11 with the phase of the VC clock 13 and outputs a phase difference. The charge pump 52 outputs a current or a voltage 43 as compared with the phase difference. Loop filter 53
Integrates and smoothes the charge pump output 43 and VC control voltage 44
Generate The VC 54 changes the frequency of the output VC clock 13 in proportion to the VC control voltage 44. As described above, the phase synchronization circuit 1 operates to make the phase of the VC clock 13 coincide with the phase of the reproduction signal 11. Next, the operations of the tapped delay line 8 and the latch 1 will be described with reference to a timing chart shown in FIG. First, a case where the reproduction signal 11 and the VC clock 13 are completely matched by the phase synchronization circuit 1 will be described. The tapped delay line 8 delays the reproduction signal 11 by a half cycle time of the VC clock. As a result, latch 1
The setup time of the delayed reproduction signal 14 with respect to the VC clock 13 in FIG. Generally, in a magnetic disk device, a peak shift phenomenon of the reproduction signal 11 occurs due to interference due to magnetization reversal on a medium. The range in which this peak shift phenomenon can be tolerated is generally called a window margin, which is a major factor in determining the performance of the magnetic disk drive. In order to maximize this window margin, high accuracy is required for the setup time in the latch 1. As mentioned earlier, the playback signal
If the VC clock 13 completely matches the VC clock 13 and the delay line 8 with tapped delays exactly by the half cycle time of the VC clock, the window margin is maximized, but the phase margin is actually increased as shown in FIG. The phase difference between the reproduction signal 11 and the VC clock 13 may not become zero in a stable synchronization state due to the performance of the synchronization circuit 1. This phase shift may fluctuate depending on the temperature. In this case, even if the tapped delay line 8 accurately delays by a half cycle time of the VC clock, the window margin does not become maximum. Conventionally, the window margin loss has been corrected by leaving the window margin loss or adjusting the delay amount of the tapped delay line 8.
However, if the phase shift in the above-mentioned synchronous state fluctuates with temperature, or if the delay amount of the tapped delay line 8 fluctuates with temperature, the loss of the window margin is adjusted. I can't.

In order to solve this problem, in the invention described in Japanese Patent Application Laid-Open No. S59-166781, a delay amount adjustment circuit is provided, and data delayed by a known amount is input to a phase synchronization circuit to determine whether or not an error has occurred. The phase shift amount between the data pulse train and the window is measured by using the method, and the phase shift amount is adjusted to an appropriate value.

[Problem to be solved by the invention]

The above-mentioned prior art requires data delayed by a known amount, so that a high accuracy is required for the tapped delay line, and no consideration is given to temperature drift and aging of the tapped delay line. There is a problem in point.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an automatic phase adjustment circuit capable of adjusting a phase shift so that a window margin is always maximized without being affected by variations in delay amount accuracy of a delay line, temperature drift and aging.

[Means for solving the problem]

A tapped delay line is provided to obtain a delay amount necessary to maximize the window margin. A detection circuit is provided for detecting that the vehicle has deviated from the window. A calculation circuit is provided to select a tap having a required delay amount from the detection result.

[Action]

In the adjustment mode, the delay line with taps shifts the taps used and changes the delay amount before outputting. In the normal mode, the input data is delayed and output using the optimum tap restored as a result of the adjustment.

The detection circuit monitors the reproduction data signal and detects that an error has occurred outside the window.

The calculation circuit calculates the tap number with the required delay amount based on the tap number with the largest delay amount and the tap number with the smallest delay amount among the delay amounts that can be reproduced in the form of the internal division ratio. Make a tap selection.

The delay amount required by these operations is selected by a method of a relative internal division ratio, and thus does not particularly depend on the accuracy and temperature of the delay line.

〔Example〕

Hereinafter, configurations and embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram of an embodiment of the present invention. Reproduction signal 11 from magnetic recording device and test signal used for adjustment
An input signal changeover switch 6 for switching 12; a phase synchronization circuit 1; a delay line 8 with a tap; a latch 1; a decoder 3 for decoding the reproduction signal 11; a detection circuit 4 for detecting that the delay signal 14 has deviated from the window; It comprises a calculation circuit 5 for selecting an optimum tap based on the detection signal 17.

When the read gate signal 19 is negated, the adjustment mode is set, and the input signal changeover switch 6 selects the test signal 12. The calculation circuit 5 determines that the phase synchronization circuit 1
The operation starts after the phase synchronization of the clock 13 is completed and normal data is input to the shift register in the detection circuit 4. The test signal 12 is delayed by the tapped delay line 8, and the amount of delay is changed by shifting the tap by the calculation circuit 5. Latch 1 is VC
The delay signal 14 is latched by the clock 13, but when the delay amount is changed, the pattern of the latch data 15 which is the output of the latch 1 changes at a position outside the window. The detection circuit 4 detects the pattern change of the latch data 15 by the latch clock 16 and outputs a detection signal 17. When the detection signal 17 is input, the calculation circuit stores the tap number of the tapped delay line 8 at that time. The taps are further shifted, and when the test signal 12 is again out of the window, the operation is performed in the same manner as the first time, and the tap number at that time is stored. Thereafter, the calculation circuit calculates a tap number having a required delay amount in the form of an internal division ratio based on the two stored tap numbers. Then, the obtained tap number is selected and the adjustment operation is completed. After that, when the read gate is asserted, the input changeover switch 6 selects the reproduction signal 11, the phase synchronization circuit 1 synchronizes the phase of the reproduction signal 11 with the VC clock 13, and the latch 1 taps the tap with the optimal delay time set. The delay signal 14 of the attached delay line is latched by the VC clock 13, and the latch data 15 and the latch clock 16 are input to the decoder for decoding. In the above description, the adjustment mode is set when the read gate is negated.However, from a system standpoint, it is also possible to perform adjustment only when there is enough time in the time as long as the read gate is negated. . During adjustment, a flag 39 indicating a busy state can be output.

Next, a specific embodiment of the present invention will be described with reference to FIGS. FIG. 2 shows the configurations of the delay line 8 with taps required in the adjustment mode, the detection circuit 4, and the calculation circuit 5. The switch 6 is omitted to limit the operation to the phase synchronization circuit 1, the decoder 3, and the adjustment mode. In this embodiment, a 4T pattern (10001000...) Repeated signal is generated from the reference clock 20 by the signal generation circuit 19 as the test signal 12. Of course, a configuration other than the 4T pattern can be used. Further, in the decoding circuit, it is desirable that the delay signal 14 is located at the center of the window. Of course, it is also possible to use a microcomputer or the like to make a calculation that internally divides into l to m (l and m are natural numbers).

The tapped delay line 8 includes a tapped delay line and a selector 1 for selecting a tap. The calculation circuit 5 includes a counter that generates a tap selection address 37 for switching the selector 1 and a tap selection address when the detection signal 17 is input.
Latch 2 for latching 37, Latch 3, Full adder for adding values of Latch 2 and Latch 3, and output data of full adder 1
It comprises a shift register 2 for bit shifting, a tap selection address 37 output by a counter, a selector 2 for switching the output of the shift register 2, and a control circuit for controlling these blocks. The detection circuit 4 includes a shift register 1 and an ER gate. FIG. 3 shows an example of a specific configuration. The first and fifth bits of a 5-bit shift register constituted by five stages of D-type flip-flops are input to ER.

The signal generation circuit 9 outputs the test signal of the 4T pattern described above.
12 and an increment clock signal 21 for incrementing the counter are output every 4T pattern several periods.

 Next, the operation will be described with reference to FIG. 4 and FIG.

When the read gate signal 19 is negated, the adjustment mode is set, and the input signal changeover switch 6 selects the test signal 12. The control circuit outputs a control signal 36, and the selector 2 selects a tap switching address 37, which is the output of the counter. Then, the phase synchronization circuit 1 outputs the test signal 12
After the phase synchronization of the VCO clock 13 is completed and the normal value is input to the shift register of the detection circuit 4, the control circuit outputs the detection circuit enable signal 38 to make the detection circuit 4 operative, and A count enable signal 31 for enabling the counter to count up. Thereafter, the calculation circuit 5 starts a count-up operation and starts detection. The counter increments the tap switching address 37 according to the increment clock signal 21 when the count enable signal 31 is input. The tap switching address 37 passes through the selector 2 and is input as the tap select signal 18 to the tapped delay line 8. The tap delay line 8 switches the selected tap by the tap select signal 18. If the selected tap is an amount of delay within the window range, the first bit and the fifth bit of the shift register of the detection circuit 4 always have the same value, and the ER output is “0”. Then, it is assumed that when the tap selection address 37 becomes L, the delay amount deviates from the window. At this time, the latch data 15 deviates from the 4T pattern as shown in FIG.
5T or 3T pattern. Therefore, the output of the ER becomes “1” and a pulse is output as the detection signal 17. When this pulse is input to the control circuit, the control circuit outputs a latch enable signal 32, and the latch 2 stores the tap selection address "1" at that time. Further, it is assumed that the delay amount deviates from the window again when the tap selection address 37 is incremented and reaches “m”. At this time, a pulse is output as the detection signal 17 as in the previous case, and the control circuit outputs the latch enable signal 33. As a result, the latch 3 stores the tap selection address "m" at that time. Since the full adder always adds the latches 2 and 3, the control circuit outputs a parallel input latch enable signal 34 to the shift register 2 and then outputs a shift clock 35 for performing a one-bit shift. As a result, an intermediate address between the address “l” and the address “m” is output from the shift register 2. This intermediate address is “l”
And "m" are one-to-one addresses. Thereafter, the control circuit switches the control signal 36 and outputs the output of the shift register 2 from the selector 2 as a tap select signal. By operating as described above, the delay signal 14
Can be set in the center of the window.

If the read gate is asserted again during this adjustment operation, the adjustment operation can be stopped and the normal state can be restored before the parallel input latch enable signal 34 is output. Then, after the read gate is negated, the adjustment may be performed again from the beginning. When the read gate is asserted after the output of the parallel input latch enable signal 34, the shift clock 35 is output, and after the control signal 36 selects the output of the shift register 2, the operation returns to the normal state. This time loss can be reduced to a short time by a circuit configuration. During this time, the flag 39 indicating busy can be output to the outside.

〔The invention's effect〕

According to the present invention, since the optimum delay tap is selected by internally dividing two tap addresses corresponding to the window width, the reproduction data is always windowed without being affected by the delay time accuracy of the delay line and its temperature characteristics. , And reproduction and decoding can be performed with the window margin always maximized, and the reliability of the device can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention. FIG. 2 is a block diagram of a calculation circuit used in one embodiment of the present invention. FIG. 3 is a block diagram of a detection circuit used in one embodiment of the present invention. FIG. 4 is a timing chart showing the operation of one embodiment of the present invention. FIG. 5 is a timing chart showing the operation of one embodiment of the present invention. FIG. 6 is a configuration diagram of a conventional decoding circuit. FIG. 7 is a diagram for explaining the operation of a conventional decoding circuit. DESCRIPTION OF SYMBOLS 1 ... Phase synchronous circuit, 3 ... Decoder 4 ... Detection circuit, 5 ... Calculation circuit 6 ... Input signal changeover switch 8 ... Tap delay line, 9 ... Signal generation circuit 11 ... Reproduction signal, 12 ... Test signal 13 ... VC clock, 14 ... Delay signal 15 ... Latch data signal, 16 ... Latch clock signal 17 ... Detection signal, 18 ... Tap select signal 19 ... Read gate signal, 20 ... Reference clock 21 ... Increment clock signal 31 ... Count enable signal 32 ... Latch enable signal 33 ... Latch enable signal 34 ... Parallel input latch enable signal 35 ... Shift clock, 36 ... Control signal 37 ... Tap switching address 38 ... Detection circuit enable signal 39 ... Flag, 42 ... Phase difference 43 ... Charge pump output, 44 ... VC control Voltage 51… Phase comparator, 52… Charge pump 53… Loop filter, 54… VC

Continued on the front page (72) Inventor Kenichi Hase 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Microelectronics Device Development Laboratory, Hitachi, Ltd. (72) Inventor Toshiyuki Iseki 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock (72) Inventor Shinichi Kojima 111 Nishiyokote-cho, Takasaki City, Gunma Prefecture Hitachi, Ltd. Takasaki Plant, Hitachi, Ltd. (56) References JP-A-59-45615 (JP, A) JP-A-59-167813 (JP, A) JP-A-62-205578 (JP, A) JP-A-63-211831 (JP, A) JP-A-63-10824 (JP, A) (JP, U) (58) Field surveyed (Int. Cl. ⁶ , DB name) G11B 20/10-20/14

Claims (1)

(57) [Claims] 1. A decoding circuit used for reproducing and decoding a data signal recorded in a magnetic recording device, comprising: a delay amount adjusting circuit including a tapped delay line; and a data signal input to the tapped delay line. The delay amount adjusting circuit shifts the taps of the tapped delay line, and the reproduced signal or the decoded signal is deviated from the window using the data signal and the delayed data signal passed through the tapped delay line. A detection circuit that detects a tap having a maximum delay amount and a tap having a minimum delay amount in the delay line with taps by determining that the tap has occurred, a tap having the maximum delay amount and a tap having the minimum delay amount. Arbitrarily adjusting the amount of delay of the delayed data signal by having a calculation circuit that calculates so as to select taps that internally divide taps into an arbitrary ratio Decoding circuit according to claim.