JP3315134B2 - Multi-track phase synchronizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to reproduction of a magnetic recording / reproducing apparatus for recording / reproducing data on multiple tracks (hereinafter referred to as a multi-track magnetic recording / reproducing apparatus) such as a magnetic tape apparatus as an external storage device of a computer. The present invention relates to a multi-track phase synchronization circuit suitable for use in a system.

[0002]

2. Description of the Related Art Conventionally, a multi-track magnetic recording and reproducing system in which a plurality of tracks are formed on a magnetic tape such as a magnetic tape device as an external storage device of a computer, and a magnetic head is provided for each track to record and reproduce information. In a recording / reproducing device, a recording / reproducing circuit is provided for each track, and the increase in the circuit scale has been a problem with the recent increase in the number of tracks and the increase in capacity. In response to this, there has been a strong demand for a phase synchronizer for clock recovery in a recovery circuit to reduce the circuit size while stabilizing the recovered clock.

Conventionally, two types of phase synchronizers, an analog type and a digital type, are known. In the analog method, a phase comparator is a digital circuit, and a loop filter and a VCO (automatic gain control circuit) are each composed of an analog circuit, and controls a phase difference between a peak pulse and an output signal of the VCO. The control voltage of the VCO is set so that the phase difference becomes “0”. On the other hand, in the digital method, as disclosed in Japanese Patent Application Laid-Open No. 61-121530, for example, an inverting circuit, a clock generating circuit and a counter circuit are constituted by digital circuits, The reproduction clock is generated by detecting a change point and resetting the count of the reference clock at the change point.

[0004] All of these conventional phase synchronizers are:
Although provided for each track, the circuit configuration is devised to reduce the size of the circuit and reduce the circuit scale of the entire device.

[0005]

However, such a conventional multi-track phase synchronizer is provided for each track, and even if the circuit configuration is devised to reduce the size as described above. However, there is a limit to the reduction of the circuit scale of the entire device, and no consideration has been given to the problem of performance degradation due to the downsizing of the circuit scale.

A first object of the present invention is to provide a multi-track phase synchronizer which solves such a problem and reduces the circuit scale.

A second object of the present invention is to provide a multi-track phase synchronizer which suppresses peak shift errors and achieves high performance.

A third object of the present invention is to provide a multi-track phase synchronizer which shortens the pull-in time.

A fourth object of the present invention is to provide a multi-track phase synchronizer capable of generating a reproduction clock even when other track information is lost.

[0010]

In order to achieve the above first object, the present invention provides a method for reproducing one track i of N tracks reproduced simultaneously (where i = 1, 2,...). ,
N), a phase synchronization means for generating a reproduction clock i of the reproduction signal i from a peak pulse i of the reproduction signal i, and a track j other than the track i (where j = 1, 2,...,
N, and a peak pulse j of the reproduced signal j of j ≠ i) and at least one peak pulse i other than the peak pulse j
Phase difference detecting means for detecting a phase difference between the detected clock signal, a delay means for delaying the reproduced clock i to generate a plurality of pulses having different phases, and the reproduced clock signal according to a phase difference detection output of the phase difference detecting means. selecting means for selecting any one of i and the output pulse of the delay means as a reproduction clock j of the reproduction signal j.

In order to achieve the second object, the present invention provides a phase correcting means for correcting the phase of at least one peak pulse i in accordance with the phase of the peak pulse j, a pulse generating means, First phase difference detecting means for detecting a phase difference between an output pulse of the phase correcting means and an output pulse of the pulse generating means, and a first phase difference detecting means for detecting a phase difference between the peak pulse j and the output pulse of the pulse generating means. 2 phase difference detection means, and magnitude comparison means for selecting a smaller one of the phase difference detection outputs of the first and second phase difference detection means and using the selected signal as a control signal for the pulse generation means. The output pulse of the pulse generating means is used as a reproduction clock j of the reproduction signal j.

In order to achieve the third object, the present invention provides a phase correcting means for correcting the phase of at least one peak pulse i in accordance with the phase of the peak pulse j, and an output of the phase correcting means. Pulse and the above peak pulse j
, A pulse generator, a phase difference between an output pulse of the calculator and an output pulse of the pulse generator, and a phase difference detection output as a control signal of the pulse generator. A phase difference detecting means, and outputting an output pulse of the pulse generating means to a reproduced clock j of the reproduced signal j.
And

In order to achieve the fourth object, the present invention provides a phase difference detecting means for detecting a phase difference between a peak pulse i and a peak pulse j; Delay means for generating a pulse, and selection means for selecting any one of a reproduction clock i and an output pulse of the delay means as a reproduction clock j of a reproduction signal j in accordance with a phase difference detection output of the phase difference detection means In the above configuration, the abnormality detecting means for detecting an abnormality such as the disappearance of the peak pulse j due to the lack of the track j, and the selection state of the selecting means is determined by detecting the abnormal peak pulse by the abnormality detecting means. And holding means for holding as it is.

Further, in order to achieve the fourth object,
In the present invention, the peak pulse i due to the lack of the track i
Abnormality detecting means for detecting an abnormality such as disappearance of the pulse, and detecting at least one peak pulse j other than the peak pulse i instead of the peak pulse i by detecting the abnormal peak pulse by the abnormality detecting means. And a selection means for supplying the information to the user.

[0015]

According to the invention for achieving the first object, the reproduction clock i is generated from the peak pulse i by the phase synchronization means. The peak pulse j has a fixed time difference from the peak pulse i, and this time difference can be obtained by the phase difference detecting means. The pulse selected by the selection means is a peak pulse i or a pulse which is shifted from the peak pulse i of the output pulses of the delay means by this time difference. Become. As described above, the phase synchronization means is used for generating the reproduced clock, but a circuit having a simple configuration including the phase difference detecting means, the delay means, and the selecting means can be used for generating the other reproduced clocks j. The circuit size of the track phase synchronizer can be reduced.

In the invention for achieving the second object, even if the peak pulses i and j have a peak shift, the phase of the peak pulse i is corrected according to the phase of the peak pulse j. Since the pulse generation means is controlled by the smaller phase difference between the phase-corrected peak pulse i and the output pulse of the pulse generation means, the reproduced clock j obtained from the pulse generation means may fluctuate. And high performance can be achieved.

In the invention for achieving the third object, according to the phase of the peak pulse j, the pulse obtained by the logical sum processing of the peak pulse i and the peak pulse j whose phase has been corrected is the original peak pulse. Since the signal has a higher frequency than i and j, the time required for the phase synchronization means to pull in the pulse is shorter than that in the case of the peak pulse j.

In the invention for achieving the fourth object, when the peak pulse j is missing, the output means of the delay circuit selected immediately before is directly selected by the selection means without any change. Does not disturb the reproduced clock j. When unnecessary noise is mixed in the peak pulse i, there is a time difference with respect to the peak pulse i, but since the phase synchronization means operates with the peak pulse j, the reproduced clock i is not disturbed.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a multi-track phase synchronizer according to the present invention using a magnetic tape device as an example, wherein 1 is a magnetic tape, 2 is a magnetic head, and 3 and 4 are AGC.
(Automatic gain control) circuit, 5 and 6 are peak pulse generation circuits, 7 is a phase difference detection circuit, 8 is a filter, 9 is a VCO
(Voltage Controlled Oscillator) 10 is a phase difference detection circuit, 11 is an averaging circuit, 12 is a delay circuit, and 13 is a selection circuit.

In FIG. 1, two tracks, a track 1 and a track 2, are formed on a magnetic tape 1. Information signals are written and read by a magnetic head 2 on each track. Writing and reading of such an information signal will be described with reference to FIG.

In FIG. 1, an information signal (hereinafter, referred to as a track 1 write signal) written to a track 1 as shown in FIG.
It is written on track 1 of magnetic tape 1. An information signal (hereinafter, referred to as a track 2 write signal) written to the track 2 as shown in FIG. 3B, for example, whose phase of the clock coincides with the clock of the track 1 write signal is delayed by the delay circuit 15 by a predetermined time Δt. After that, it is supplied to the magnetic head 2 and written on the track 2 of the magnetic tape 1.
By this delay circuit 15, the track 2 write signal is written to the magnetic tape 1 with a delay of .DELTA.t from the track 1 write signal.

When the above information signals are read from the magnetic tape 1, as shown in FIG. 3C, the information signals read from the track 1 (hereinafter referred to as track 1 read signals) are also shown in FIG. As shown in FIG.
The information signal read from the track 2 (hereinafter, referred to as a track 2 read signal) also has a low band due to the frequency characteristics of the magnetic head 2, so that a signal having a gentle peak waveform at a change point of the write signal is generated. Become. The peak of the track 2 read signal is later than the peak of the track 1 read signal by time Δt.

In FIG. 1, a magnetic head 2
A track 1 read signal and a track 2 read signal having waveforms as shown in (c) and (d) are obtained. A peak is detected from the track 1 read signal and the track 2 read signal to form a peak pulse, and a reproduction clock is generated from the peak pulse. As a result, the voltage level fluctuates, the peak cannot be detected accurately, and a stable reproduced clock cannot be obtained. Therefore, the track 1 read signal and the track 2 read signal obtained by the magnetic head 2 are supplied to AGC circuits 3 and 4, respectively, and are converted into signals of a constant voltage level. That is, the peak voltage levels of the track 1 read signal and the track 2 read signal become constant.

The track 1 read signal output from the AGC circuit 3 is supplied to a peak pulse generation circuit 5, where the peak is detected and a peak pulse PKA is generated. Similarly, the track 2 read signal output from the AGC circuit 4 is supplied to a peak pulse generation circuit 6, where the peak is detected and a peak pulse PKB is generated. These peak pulse generating circuits 5 and 6 differentiate the input signal with a differentiating circuit to obtain the peaks (change points in FIGS. 3A and 3B).
Is detected, and the output signal of this differentiating circuit is supplied to a zero-cross comparator, whereby the peak pulses PKA, PKA
Form KB.

The peak pulse PKA output from the peak pulse generating circuit 5 is supplied to an analog type phase locked loop circuit including a phase difference detecting circuit 7, a filter 8, and a VCO 9 as known in the above-mentioned conventional example. You. In this phase synchronization circuit, the phase difference detection circuit 7 compares the position of the peak pulse PKA (FIG. 4B) of the track 1 read signal (FIG. 4A) with the output signal CKA of the VCO 9 (FIG. 4C). A phase difference is detected, and this phase difference (FIG. 4D) is supplied to the VCO 9 as a control signal (FIG. 4E) through the filter 8. When the peak pulse PKA lags behind the output signal CKA of the VCO 9, the phase difference detected by the phase comparison circuit 7 becomes negative. In this case, the output signal of the filter 8 increases and the oscillation frequency of the VCO 9 increases. As a result, the phase of the output signal CKA of the VCO 9 is advanced. In the opposite case, the output signal of the filter 8 decreases, the oscillation frequency of the VCO 9 decreases, and the phase of the output signal CKA of the VCO 9 delays. Thus, the peak pulse PKA and the output signal CKA of the VCO 9 are output.
The VCO 9 is controlled so that the phase difference between the VCO 9 and the VCO 9 becomes smaller.
And the output signal C of the VCO 9
KA will be synchronized with the peak pulse PKA. The output signal CKA of the VCO 9 is a reproduction clock of the track 1 read signal. Thus, the clock CKA of the track 1 read signal (hereinafter, referred to as the track 1 reproduction clock) is reproduced.

On the other hand, the phase of the peak pulse PKB output from the peak pulse generation circuit 6 is compared with the phase of the peak pulse PKA in the phase detection circuit 10, and the phase difference between them is detected. The phase differences detected in this way are sequentially supplied to the averaging circuit 11 and are averaged to generate an average phase difference between the peak pulses PKA and PKB. The track 1 reproduced clock CKA is supplied to the delay circuit 12 and the selection circuit 13. The delay circuit 12 delays the track 1 reproduced clock CKA, outputs pulses CKA1, CKA2, and CKA3 having different phases from each other, and supplies the pulses to the selection circuit 13. The selection circuit 13 selects one of the track 1 reproduced clock CKA from the VCO 9 and the output pulses CKA1, CKA2, and CKA3 of the delay circuit 12 according to the average phase difference from the averaging circuit 11. The track 1 reproduced clock CKA and the delay circuit 1
The phase of the output pulses CKA1, CKA2, and CKA3 with respect to the track reproduction clock CKA is in accordance with the average phase difference from the averaging circuit 11, and the pulse CKB output from the selection circuit 13 is the track 1 reproduction clock CK.
A pulse which is shifted from A by the time difference between the peak pulses PKA and PKB, and is a reproduction clock of the track 2 read signal synchronized in phase with the peak pulse PKB. In this manner, the clock of the track 2 read signal (hereinafter, referred to as track 2 reproduction clock) CKB is reproduced.

FIG. 5 is a block diagram showing a specific example of the phase difference detection circuit 10 in FIG.
EC (increment / decrement) signal generation circuit, 17 is a U / D (up / down) counter, 18 is an OR circuit, 19 is a falling edge detection circuit, and 20 is a DF
F (D-type flip-flop circuit). FIG. 6 is a diagram showing a timing relationship between signals of respective parts in FIG.
The same reference numerals are given to the signals corresponding to FIG.

5 and 6, the peak pulse PKA from the peak pulse generation circuit 5 (FIG. 1) and the peak pulse PKB from the peak pulse generation circuit 6 (FIG. 1) are IN.
It is supplied to the C / DEC signal generation circuit 16. INC / D
The EC signal generation circuit 16 detects a phase difference between the peak pulses PKA and PKB. When the phase of the peak pulse PKA is ahead of the peak pulse PKB, the EC signal generation circuit 16 generates an INC (increment) signal having a time width equal to the phase difference. When the peak pulse PKA is generated and the phase is delayed from the peak pulse PKB, a DEC (decrement) signal having a time width equal to the phase difference is generated.
As the INC / DEC signal generation circuit 16, Motorola MC4044 or the like can be used.

The INC signal and the DEC signal output from the INC / DEC signal generation circuit 16 are supplied to a falling edge detection circuit 19 via an OR circuit 18, and the falling edge (rear edge) is detected. The phase difference output clock CKφ is formed at the timing of the falling edge.
The U / D counter 17 is provided with the falling edge detection circuit 1.
9 for each phase difference output clock CKφ from
When the INC / DEC signal generation circuit 16 outputs the INC signal, the reference clock CK0 is counted up from the rising edge (front edge). When the INC / DEC signal generation circuit 16 outputs the DEC signal, the rising edge (front edge) is output. ), The reference clock CK0 is counted down. The count value N of the U / D counter 17 is D-FF2
It is latched to 0 at the timing of the phase difference output clock CKφ. The reset timing of the U / D counter 17 by the phase difference output clock CKφ is slightly delayed from the latch timing of the D-FF 20. Therefore, this D-
The phase difference Δφ between the peak pulses PKA and PKB is obtained from the FF 20. The phase difference output clock CKφ is D-FF
20 shows the output timing of the phase difference Δφ from the reference numeral 20.

FIG. 7 is a block diagram showing a specific example of the averaging circuit 11 in FIG.
Is an adder, and 23 is a multiplier. FIG. 8 shows the averaged output of the averaging circuit 11 and the delay circuit 12 in FIG.
FIG. 4 is a diagram illustrating a relationship with an output of a selection circuit 13;

In FIG. 7, the phase difference Δφ from the D-FF 20 in FIG. 5 is added to the latch data in the D-FF 21 by the adder 22, then multiplied by 0.5 by the multiplier 23 and averaged. The output ΔφA is supplied to the selection circuit 13 in FIG. The averaged output ΔφA is latched in the D-FF 21 by the phase difference output clock CKφ from the falling edge detection circuit 19 in FIG. And D-FF2
The averaged output ΔφA latched at 1 is added to the phase difference Δφ by the adder 22, and therefore, the D-FF 21
Stores the average value of the phase difference Δφ up to the previous time.

Here, in FIG. 8, the delay circuit 12 in FIG.
Pulses CKA1, CKA2, which are shifted in phase by nsec.
Assuming that CKA3 is output, for example, when the phase difference between the peak pulses PKA and PKB is 5 nsec, the averaged output ΔφA generated by the averaging circuit 11 in FIG. 7 becomes “2” or “3”, and FIG. The selection circuit 13 selects a signal obtained by delaying the track 1 reproduced clock CKA by 4 nsec or 6 nsec by the delay circuit 12 as the track 2 reproduced clock CKB. In FIG. 8, the averaging output ΔφA becomes “2” and the selection circuit 13
2 output signal CKA2 and then averaged output ΔφA
Becomes "1", the selection circuit 13 selects the output signal CKA1 of the delay circuit 12, and outputs the track 1 reproduced clock C
KB.

As described above, the track 2 reproduced clock CKB can be generated from the track 1 reproduced clock CKA, and the phase synchronization circuit for generating the track 2 reproduced clock CKB is not required. A reduction in scale can be realized.

In this embodiment, the track 2 reproduced clock CKB is generated only from the track 1 reproduced clock CKA. However, the track 2 reproduced clock CKB is generated.
Alternatively, the track 2 playback clock CKB may be generated from a plurality of other track playback clocks.

FIG. 9 is a block diagram showing another specific example of the phase difference detection circuit 10 shown in FIG. 1, wherein reference numeral 24 denotes a rising edge detection circuit, 251, 252,..., 25 (n-1).
, 262, 263,..., 26n are D-FFs, 27 is a majority logic circuit, 28 is an up counter, 29 is a multiplier, 30a and 30b are pulse width detection circuits, 31 is a selection circuit, 32 Is a multiplier, parts corresponding to those in FIG. 5 are denoted by the same reference numerals, and redundant description is omitted. FIG. 10 is a diagram showing the timing relationship between the signals shown in FIG.

The embodiment shown in FIG.
The phase difference between A and PKB is detected by counting the reference clock CK0. Therefore, it is basically impossible to detect a phase difference equal to or less than the cycle of the reference clock CK0. On the other hand, in this embodiment shown in FIG. 9, it is possible to detect the phase difference with an accuracy equal to or less than the cycle of the reference clock CK0, and to further improve the accuracy of the phase difference detection without making the cycle of the reference clock CK0 too short. Is made possible.

9 and 10, the INC signal formed from the peak pulses PKA and PKB by the INC / DEC generation circuit 16 is supplied to the pulse width detection circuit 30a, and the DEC signal is supplied to the pulse width detection circuit having the same configuration. 3
0b. The reference clock CK0 is also supplied to the pulse width detection circuits 30a and 30b.

In the pulse width detection circuit 30a, IN
The C signal is supplied as data to the D-FFs 261 to 26n. Further, the reference clock CK0 becomes a latch pulse of the D-FF 26n and the delay circuit 25 (n-1).
..., 252, 251 are sequentially delayed by Δt,
These delay circuits 25 (n-1), ..., 252, 251
The clock output from each is D-FF26 (n-1)
(Not shown),..., 263, 262, 261 are latch pulses Dn, D (n-1),..., D3, D2, D1. The latch pulse Dn has the same phase as the reference clock CK0. Therefore, the i (i = 1, 2,..., N) th D
The -FF 26i latches the INC signal by the latch pulse Di output from the i-th delay circuit 25i. The D-FF 26n latches the level of the INC signal at the timing of the reference clock CK0, and outputs the ith D-FF.
The FF 26i receives Δt × (n
-I) The level of the INC signal at the timing delayed by nsec is latched. That is, when the reference clock CK0 is input, the INC signal is sampled in order from the reference clock CK0 at time intervals of Δt, and the D-FF2
6n, 26 (n-1), ..., 263, 262, 261
In this order.

Here, the cycle of the reference clock CK0 is set to 60 nsec, and the delay circuits 251, 252,.
The delay amounts Δt of 25 (n−1) are all equal to 10 nsec.
And Therefore, n = 6, and when the reference clock CK0 is input, 10 ns
At time intervals c, the INC signal is output from the D-FFs 26n, 26 (n
-1),..., 263, 262, 261 are latched in this order.

D-FFs 261, 262, 263,...
The outputs Q1, Q2, Q3,..., Qn of the 26n are supplied to a majority logic circuit 27. These outputs Q1, Q2, Q
3,..., Qn become “H” when the INC signal rises.
(High level) and “L” when the INC signal falls
(Low level), but the latch pulses D1, D2, D
D-FF 26i latched by the latch pulse Di closest to the INC signal after the edge of the INC signal among 3,.
Q level inverts earliest after the edge of the INC signal.

The majority logic circuit 27 includes D-FFs 261, 2
, 26n are set with numbers “1”, “2”, “3”,..., “N” to identify them, and these outputs Q1, Q2 , Q3, ...,
The level change of Qn is monitored, and when it is determined that the D-FF 26i has the earliest inverted level of the output after the edge of the INC signal, the number “i” representing the D-FF 26i is selected.

Actually, the edge of the INC signal is not detected. After all the levels of the outputs Q1 to Qn become "H" or "L" before the edge of the INC signal is input, The output Q1 whose level is inverted first is INC
It is assumed that the level of the signal is inverted first and then the signal is inverted.

Now, when n = 6 and the pulse width of the INC signal is 1
00 nsec, and a reference clock CK0 having a period of 60 nsec is applied to this INC signal as shown in FIG.
Is input, D is detected after the rising edge of the INC signal.
-The output Q1 of the FF 261 rises first. Therefore,
The majority logic circuit 27 selects the number “1” for the D-FF 261 and stores it internally. Next, when the INC signal falls, the output Q3 of the D-FF 263 falls first. Therefore, from this, the majority logic circuit 27 determines the D-FF 263 and selects the number “3” corresponding to the D-FF 263, and compares the number “3” with the previously selected and internally stored number “1”. The difference “3” − “1” = “2” is obtained, and this is output as output information ΔN.

The time difference between the latch pulses Dj and Dk supplied to the D-FF 26j having the number "j" and the D-FF 26k having the number "k" stored therein is ｛(jk).
× 60 / n｝ nsec. When j = k,
The pulse width of the INC signal is not an integral multiple of the cycle of the reference clock CK0, but the above time difference differs from the integral multiple of the cycle of the reference clock CK0 by (j−k) × 60/6 nsec. That is, if j ≧ k,
The pulse width (nsec) of the INC signal is (integer multiple of the period of the reference clock CK0) − (j−k) ×
60/6. The second term of this equation is obtained by multiplying the output information ΔN by 1 / n (n = 6) by the multiplier 29.

The first term of the above equation is obtained when the up counter 28 counts up the reference clock CK0. The up counter 28 continues to be cleared during the period when the output signal of the OR circuit 18 is "L", and when this signal becomes "H", counts up the reference clock CK0. The count value N is subtracted by the output of the value of (j−k) / 6 from the multiplier 29 and supplied to the selection circuit 31. The count value N is an integer in the first term of the above equation, and the value obtained by multiplying the count value N by 60 nsec is the first term of the above equation.

The pulse width detection circuit 30b is similar to the pulse width detection circuit 30a for the DEC signal.
Information representing the pulse width of the EC signal is output. This information is multiplied by −1 by the multiplier 32 and supplied to the selection circuit 31. The selection circuit 31 starts selecting output information of the pulse width detection circuit 30b from the rising edge of the DEC signal, for example, and delays the pulse width detection circuit 30b by at least one cycle of the reference clock CK0 from the falling edge of the DEC signal.
Start selecting output information. When the DEC signal is "L", the selection circuit 31 selects the output information of the pulse width detection circuit 30a.

The information selected by the selection circuit 31 is a D-FF
20 and is latched by the falling edge pulse from the falling edge detection circuit 19. This falling edge pulse is slightly delayed from the falling edge of the output signal of the OR circuit 18, whereby the pulse widths of the INC signal and the DEC signal are correctly represented from the output information of the pulse width detection circuits 30a and 30b. Information is extracted and D-FF
Latched at 20. The delay time of the falling edge pulse from the falling edge detection circuit 19 only needs to exceed 10 nsec in the example shown in FIG.

Therefore, as shown in FIG. 10, when the pulse width of the INC signal is 100 nsec, j = “3”,
Since k = “1” and the count value N = 2, according to the above equation, 2 × 60 − (“3” − “1”) × 60/6
= 120-20 = 100 nsec.

As described above, in this embodiment, even if the cycle of the reference clock CK0 is long, the delay circuits 251 and 25
2,..., Peak pulse PK in units of 25n delay time
The phase difference between A and PKB can be detected, and the accuracy of phase difference detection increases.

The number of delay circuits used is not limited to the above, and can be set arbitrarily. Needless to say, the greater the number of used components, the higher the accuracy of phase difference detection. Further, the number of the delay circuits used is set to a power of 2, and the delay time and the period of the basic clock CK0 are appropriately selected, whereby the multiplication in the multiplier 29 can be performed by bit shift. Significant reduction in configuration is possible.

FIG. 11 is a block diagram showing a main part of another embodiment of the multi-track phase synchronizer according to the present invention.
3 is a phase correction circuit, 34a and 34b are phase difference detection circuits,
35 is a magnitude comparison circuit, 36 is a filter, and 37 is a VCO. In this embodiment, a reproduced clock can be obtained with high accuracy even if a reproduced signal of the magnetic head 2 has a peak shift due to intersymbol interference.

In FIG. 11, a phase difference detection circuit 34a,
34b is the same as the phase difference detection circuit 7 in FIG. 1, and the filters 35 and VCO 36 are also the same as the filters 8 and VCO 9 in FIG. The peak pulse PKB is supplied directly to the phase difference detection circuit 34b, and the peak pulse PKA is supplied to the phase difference detection circuit 34a after the delay between the tracks is corrected by the phase correction circuit 33 as shown in FIG. The phase difference detection circuit 34a compares the phase of the peak-corrected peak pulse PKA 'with the output signal of the VCO 37, and outputs the phase difference. In the phase difference detection circuit 34b, the peak pulses PKB and V
The output signal of the CO 37 is compared in phase, and the phase difference is output. The magnitude comparison circuit 35 outputs these phase difference detection outputs Δ
The magnitudes of φa and Δφb are compared, and the phase difference detection output having the smaller absolute value is selected and output. This phase difference passes through the filter 36 and is supplied to the VCO 37 as a control voltage.
Thus, the VCO 37 outputs the track 2 reproduction clock C synchronized with either the peak pulse PKA from the phase correction circuit 33 or the input peak pulse PKB.
KB is obtained.

The phase correction circuit 33 corrects the amount of delay between tracks, finds the amount of phase shift of the peak pulse PKA from the peak pulses PKA, PKB, and cancels the amount of delay between tracks. Assuming that the peak pulse PKB has a shift due to intersymbol interference, FIG.
As shown in FIG. 3, since the phase of the peak pulse PKA is corrected to become the peak pulse PKA ′, the peak pulse PKB is
In the portion shifted by the inter-symbol interference, when the phase difference detection output Δφa of the phase difference detection circuit 34a is, for example, “0”, the phase difference detection output Δφb of the phase difference detection The value increases, and the magnitude comparison circuit 35
Means to select the smaller phase difference detection output Δφa. Accordingly, there is no large change in the output Δφc of the magnitude comparison circuit 35, the VCO 37 operates stably, and the fluctuation of the track 2 reproduction clock CKB is suppressed to achieve high precision.
Conversely, there is a shift in the peak pulse PKA due to the intersymbol interference, and the phase correction circuit 33 similarly operates the peak pulse PKA.
If the KA is phase corrected, the phase difference detection circuit 34b
Since the absolute value of the phase difference detection output Δφb is smaller, the magnitude comparison circuit 35 selects this. Therefore, a similar effect can be obtained.

FIG. 12 shows the phase correction circuit 33 in FIG.
Is a block diagram showing one specific example, wherein 38 is a phase difference detection circuit, 39 is an averaging circuit, 40 is a delay circuit, and 41 is a selection circuit. In this specific example, the phase difference detection circuit 38, the averaging circuit 39, the delay circuit 40, and the selection circuit 4
Reference numeral 1 is the same as the phase difference detection circuit 10, the averaging circuit 11, the delay circuit 12, and the selection circuit 13 in FIG. 1, respectively, and the same effect as the circuit by these is obtained. However, in FIG.
KA is delayed, whereas in FIG.
Delay KA. Thus, the peak pulses PKA, P
Since the selection circuit 41 is controlled by averaging the phase difference between the KBs, the peak pulse PKA 'and the peak pulse PKA are controlled.
The peak pulse P is set so that the phase with the KB is substantially the same.
The phase of KA 'is set.

FIG. 14 is a block diagram showing a main part of still another embodiment of the multi-track phase synchronizer according to the present invention, wherein 42 is an OR circuit, 43 is a phase difference detecting circuit, and corresponds to FIG. The same reference numerals are given to the portions, and the duplicate description will be omitted. FIG. 15 is a diagram showing the timing relationship between the tape pattern and the signals of various parts in FIG.
The same reference numerals are given to the signals corresponding to FIG.

In the magnetic tape device, as shown in FIG. 15A, an IBG (Internal B
A gap called “lock gap” is provided. In the IBG, signals of specific frequencies different from each other are recorded on the respective tracks 1 and 2. Therefore,
When the recording signals of such a frequency are simultaneously reproduced from the tracks 1 and 2, this reproduction area is an IBG. For example, track 1 has an "ALL1" pattern,
Track 2 has a “TONE” pattern (6 of “ALL1”).
In the case of the combination of (frequency division), it indicates that the recording area of such a pattern is an IBG area. The peak pulses PKA and PKB shown in FIG. 15 belong to this IBG region.

In FIG. 14, the phase of the peak pulse PKA is corrected by the peak pulse PKB in the phase correction circuit 33, and the OR circuit 4 is added together with the peak pulse PKB.
The signal is supplied to the phase difference detection circuit 43 via the second circuit 2. In this phase difference detection circuit 43, the output pulse of the OR circuit 42 and the VCO
The output pulse of the 37 is compared with the phase, and the phase difference detection output is supplied to the VCO 37 via the filter 36.

Here, considering the pull-in of the phase-locked loop in the IBG area, the "ALL1"
Since the number of peak pulses to be compared is larger than that of the “NE” pattern, the pull-in time of the “ALL1” pattern is shorter than that of the “TONE” pattern, but the phase synchronization circuit having the configuration shown in FIG. Since the pulse PKA is phase-corrected by the phase correction circuit 33 as described above,
In the IBG area, the track 2 of the "TONE" pattern is completed with the same pull-in time as the track 1 of the "ALL1" pattern, so that the track 2 of the "TONE" pattern can be shortened.

If there is no defect in the magnetic tape 1 and no dropout occurs in the peak pulse PKA, as shown in FIG. 16, the phase correction circuit 33 corrects the phase of the peak pulse PKA.
Only KA may be supplied to the phase difference detection circuit 43. In this case, the configuration can be simplified as compared with the embodiment shown in FIG. 14, and the same effect can be obtained.

FIG. 17 is a block diagram showing a main part of still another embodiment of the multi-track phase synchronizer according to the present invention. Reference numeral 44 denotes a latch circuit, and 45 denotes a peak pulse detection circuit, corresponding to FIG. The same reference numerals are given to the portions, and the duplicate description will be omitted. FIG. 18 is a diagram showing the timing relationship between the signals of the respective units in FIG. 17, and the signals corresponding to FIG. 17 are denoted by the same reference numerals.

In this embodiment, a malfunction of the means for generating the track 2 reproduction clock CKB due to a track defect or the like of the magnetic tape 1 is prevented. In the embodiment shown in FIG. 1, if the peak pulse PKB is lost due to a track defect or the like on the magnetic tape 1 or an unnecessary pulse is generated due to the inclusion of noise or the like, the phase difference detection circuit 10 sets a long pulse. A phase difference between the time peak pulses PKA and PKB is not detected, and an erroneous phase difference detection output is generated by an unnecessary pulse. The embodiment shown in FIG. 17 solves such a problem.

In the figure, the latch circuit 44 normally supplies the average phase difference from the averaging circuit 11 to the selection circuit 13 as it is. The peak pulse detection circuit 45 detects an unnecessary pulse due to lack of the peak pulse PKB or noise by monitoring the cycle of the peak pulse PKB. Now, let the period of the peak pulse PKB be TB, and FIG.
As shown in FIG. 8, if the peak pulse PKB is input every time TB, the output of the peak pulse detection circuit 45 is kept at “H”. If the peak pulse PKB is not detected, or if the next peak pulse PKB is detected before the time TB has elapsed, the output of the peak pulse detection circuit 45 becomes “L”. When the output of the peak pulse detection circuit 45 becomes “L”, the average phase difference of the averaging circuit 11 at this time is held in the latch circuit 44. The selection circuit 13 is controlled by the held average phase difference. Again, at the interval of time TB, the peak pulse PKB
Is input, the output of the peak pulse detection circuit 41 becomes “H”.

Here, the averaging circuit 11 has the configuration shown in FIG. Also, as described above, the peak pulse PK
When an unnecessary pulse due to missing or noise is mixed in B, an erroneous phase difference output is generated from the phase difference detection circuit 10. Therefore, the averaging circuit 11 averages the phase difference output including the erroneous phase difference output. The average phase difference due to this is held in the D-FF 21 shown in FIG. Therefore, when the output of the peak pulse detection circuit 45 becomes “H” as described above, the D-FF 21 shown in FIG. 7 is cleared, and a mistake in the averaging circuit 11 due to missing in the peak pulse PKB or unnecessary noise. The average phase difference is cleared, and a new correct average phase difference is output from the averaging circuit 11.

As a result, if the peak pulse PKB has a lack or noise, the selection circuit 13 will continue to select the output pulse of the delay circuit 12 selected immediately before it, and the selection pulse in the peak pulse PKB. Performs correct operation without being affected by unnecessary noise.

FIG. 19 is a block diagram showing a main part of still another embodiment of the multi-track phase synchronizer according to the present invention, wherein 46 is a selection circuit, 47 is a peak pulse detection circuit, and corresponds to FIG. The same reference numerals are given to the portions, and the duplicate description will be omitted. In this embodiment, a malfunction of the means for generating the track 1 reproduction clock CKA due to a track defect or the like of the magnetic tape 1 is prevented. In the embodiment shown in FIG. 1, the peak pulse PKA is lost due to a track defect of the magnetic tape 1 or the like, or the peak pulse PKA is lost.
If unwanted pulses are generated due to noise or the like mixed into the
Long-term peak pulses PKA, PKB by the phase difference detection circuit 7
The phase difference between the tracks 1 and 2 is not detected, and an erroneous phase difference detection output is output due to an unnecessary pulse, so that the track 1 reproduced clock CKA cannot be generated. Cannot be generated. The embodiment shown in FIG. 19 solves such a problem.

In the figure, a selection circuit 46 is controlled by the output of a peak pulse detection circuit 47 and selects one of the peak pulses PKA and PKB. The peak pulse detection circuit 47 performs the same operation as the peak pulse detection circuit 45 in FIG. Set the period of the peak pulse PKA to TA
When the peak pulse PKA is input every time TA, the output of the peak pulse detection circuit 47 becomes “H”, whereby the selection circuit 46 selects the peak pulse PKA and supplies it to the phase difference detection circuit 7. I do. On the other hand, if the next peak pulse PKA is not detected even after the time TA has elapsed after the peak pulse PKA due to missing or unnecessary noise in the peak pulse PKA, or the next time before the time TA has elapsed, the next pulse TA is not detected. Peak pulse PKA
When (noise) is detected, the output of the peak pulse detection circuit 47 becomes “L”. Thereby, the selection circuit 4
6 is switched to select the peak pulse PKB and supply it to the phase difference detection circuit 7. Therefore, the VCO 9 operates so as to synchronize with the peak pulse PKB. However, in this case, as described above, since the phase of the peak pulse PKA is ahead of the peak pulse PKB, the track 1 reproduced clock CKA obtained at this time is delayed from the true phase. For this reason, it is necessary to advance the phase of the track 1 reproduced clock CKA at this time by a phase shift circuit (not shown).

As described above, in each embodiment, the reproduction clock of each track is generated only by using the phase difference detection circuit, the filter, and the phase synchronization circuit including the VCO for only one of the two tracks. Thus, the circuit scale of the multi-track phase synchronizer can be reduced, and the effect of the peak shift error can be reduced and the pull-in time can be reduced.

In each of the above embodiments, the case of a magnetic tape device using a two-track magnetic tape has been described, but the present invention is not limited to only these embodiments. For example, it may be a magnetic tape device having three or more tracks, or another data recording / reproducing device such as a parallel transfer system of a hard disk.

In reproducing data from such a recording medium having three or more tracks, when the magnetic head 2 as reproducing means reproduces two tracks simultaneously as shown in FIG. 1 and FIG. Each of the above embodiments is applied as it is, but when three or more tracks are to be reproduced simultaneously, the reproduction clock of the reproduction signal of one of the tracks is used as the reproduction clock CKA forming means in each of the above embodiments. The reproduction clock of the reproduction signal of each of the other tracks may be formed by the same means as the reproduction clock CKB forming means in each of the above embodiments.

[0070]

As described above, according to the present invention,
It is possible to greatly reduce the circuit scale, to improve the performance such as the peak shift and the pull-in time, and to prevent the malfunction due to the abnormality of the reproduction clock due to the defect of the medium or the like.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a multi-track phase synchronizer according to the present invention.

FIG. 2 is a configuration diagram illustrating an example of a data writing / reading unit using a magnetic tape in FIG. 1;

FIG. 3 is a timing chart showing a data write / read operation on a magnetic tape by a data write / read unit shown in FIG. 2;

FIG. 4 is a timing chart showing an operation of a generation means of a track 1 reproduction clock CKA in FIG. 1;

FIG. 5 is a block diagram illustrating a specific example of a phase difference detection circuit in FIG. 1;

FIG. 6 is an operation timing chart of the phase difference detection circuit shown in FIG. 5;

FIG. 7 is a block diagram illustrating a specific example of an averaging circuit in FIG. 1;

FIG. 8 is a timing chart showing an operation of a means for generating a track 2 reproduced clock CKB in FIG. 1;

FIG. 9 is a block diagram illustrating another specific example of the phase difference detection circuit in FIG. 1;

10 is an operation timing chart of the pulse width detection circuit in FIG.

FIG. 11 is a block diagram showing a main part of another embodiment of the multi-track phase synchronizer according to the present invention.

FIG. 12 is a block diagram showing a specific example of a phase correction circuit in FIG. 11;

FIG. 13 is an operation timing chart of the embodiment shown in FIG.

FIG. 14 is a block diagram showing a main part of still another embodiment of the multi-track phase synchronizer according to the present invention.

15 is an operation timing chart of the embodiment shown in FIG.

FIG. 16 is a block diagram showing a main part of still another embodiment of the multi-track phase synchronizer according to the present invention.

FIG. 17 is a block diagram showing a main part of still another embodiment of the multi-track phase synchronizer according to the present invention.

18 is an operation timing of the peak pulse detection circuit in FIG.

FIG. 19 is a block diagram showing a main part of still another embodiment of the multi-track phase synchronizer according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Magnetic tape 2 Magnetic head 5, 6 Peak pulse generation circuit 7 Phase difference detection circuit 9 VCO 10 Phase difference detection circuit 11 Averaging circuit 12 Delay circuit 13 Selection circuit 33 Phase correction circuit 34a, 34b Phase difference detection circuit 35 Size comparison circuit 37 VCO 38 Phase difference detection circuit 39 Averaging circuit 40 Delay circuit 41 Selection circuit 42 OR circuit 43 Phase difference detection circuit 44 Latch circuit 45 Peak pulse detection circuit 46 Selection circuit 47 Peak pulse detection circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-58-166520 (JP, A) JP-A-59-67731 (JP, A) JP-A-64-102780 (JP, A) JP-A-2- 226553 (JP, A) JP-A-53-63004 (JP, A) JP-A-59-180816 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11B 20/10 G11B 20 /14

Claims (5)

(57) [Claims] 1. M tracks (where M is an integer of 2 or more) in which data is recorded on a recording medium are formed.
In a data reproducing apparatus which reproduces data from N tracks (where N = 2, 3,..., M) of the M tracks simultaneously by the reproducing means, the reproduction signals of the N tracks are Detect sequential peaks,
First means for generating a peak pulse of each of the reproduction signals; and second means for generating a reproduction clock for each of the reproduction signals from each of the peak pulses , wherein the second means comprises: A specific track of the N tracks
Of the reproduced signal i of the block i (where i = 2, 3,..., N)
A reproduction clock i of the reproduction signal i is generated from the peak pulse i.
A third track, and the specific track i (with the exception of the N tracks).
And track j other than i = 2, 3,..., N (provided that
j = 2, 3,..., N, and the reproduced signal j of j ≠ i)
And the reproduced clock i of the reproduced signal i
To generate a reproduction clock j of the reproduction signal j from
Means, and the fourth means comprises the peak pulse i and the peak pulse
Phase difference detection means for detecting a phase difference between the pulse j, the reproduction click in response to the phase difference detection output of the phase difference detecting means
Phase correcting means for correcting the phase of the lock i.
The output signal of the correction means is converted to a reproduction clock j of the reproduction signal j.
A multi-track phase synchronizer, characterized in that: 2. The method according to claim 1 , wherein the third means includes:
A multi-track phase synchronizer, which is a phase synchronizer that operates in phase with the peak pulse i and generates the reproduction clock i. 3. The abnormal condition detecting device according to claim 1 , wherein the third means comprises: an abnormality detecting means for detecting an abnormal state of the peak pulse i; A multi-track phase synchronization system comprising: a selection unit that selects the peak pulse j upon detection; and a phase synchronization unit that operates in phase synchronization with an output pulse signal of the selection unit and generates the reproduction clock i. apparatus. 4. A means according to claim 1, 2 or 3, wherein said means for detecting an abnormal state of said peak pulse j , said means for detecting an abnormal state and said phase correcting means.
Fix the amount of phase correction for the reproduced clock i of the stage
Means for providing multi-track phase synchronization
Place. 5. The method according to claim 1, wherein
The phase correction means delays the reproduced clock i, and outputs a plurality of pulses having different phases.
Delay means for outputting a phase signal, and the reproducing means according to a phase difference detection output of the phase difference detecting means.
Either clock i or the output pulse signal of the delay circuit
Selecting means for selecting one , and an output of the selecting means
The pulse signal is used as a reproduction clock j of the reproduction signal j.
And a multi-track phase synchronizer.