JPS63217720A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To attain phase locking while setting the best quantity of delay by using a reference clock signal corresponding to a predetermined delay while a tapped delay element is selected. CONSTITUTION:A tapped element is used for a delay element 2 and a signal of a different delay is extracted from the selected tap by the control of a tap switching circuit 4. A read information signal or a reference signal 12 is selected from an input signal to the element 2 by a switch 1. The circuit 3 checks the state of the input signal 13 of the element 2 at the rise of the tap output signal 14 of the element 2 and the result is outputted as a check signal 15. The signal 15 controls the switch 1 and the tap changeover circuit 4. A phase comparator 6 in the PLL 5 uses a delay element input signal 13 as an enable signal to receive the tap output 14 of the element 2. The switch 1 selects the readout information signal 11 and in receiving the mode switching pulse 18, the check state selecting the optimum quantity of delay of the element 2 is transited and restored after the optimum value is selected.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a phase synchronization circuit used in magnetic disk drives, etc., and in particular, to suppress fluctuations in the frequency pull-in range and reduce data read error rate. This invention relates to a phase-locked circuit that can be used.

[Conventional technology]

In magnetic disk drives, data is encoded and recorded in order to perform high-density recording. (For example, the MFM method, RLL method, etc. are known as such encoding methods.) Therefore, at the time of reproduction, it is necessary to decode the read data signal from the magnetic disk device. For this decoding, a phase synchronization circuit is required that outputs a synchronized clock signal that is phase synchronized with the successive data signal.

Generally, a phase synchronized circuit has a read data signal 11 and a voltage controlled oscillator 9 (hereinafter referred to as VCO), as shown in FIG.
A phase comparator 6 that compares the phase with the VCO clock signal 17 which is the output of the VCO, a charge pump 7 that causes current to flow in or out depending on this output, and a loop filter 8 that converts this output current into a voltage. , and a VCO 9 whose oscillation frequency is controlled according to this output voltage.

As shown in FIG. 6, the phase comparator 6 operates by outputting a phase lead signal 19 when the phase of the read data signal 11 is ahead of the phase of the CO clock signal 17, and outputs a phase lag signal when it is behind the phase of the CO clock signal 17. Outputs 19.

Incidentally, since the successive signal 11 from the magnetic disk drive is a so-called pulse signal, it is necessary to avoid phase comparison in the toothless portion of the read data signal. For this reason, the phase synchronization circuit for magnetic disks uses a delay element 26, as shown in FIG.

In this phase locked circuit, the signal to be actually compared is the signal 14 that has passed through the delay element 26, and the signal 11 before passing serves as a control signal for determining whether or not to perform phase comparison. The phase comparator 6 is enabled at the rising edge of the pulse of the read data signal 11, and after a pulse is received at both input ends of the phase comparator 6 and a phase difference is detected, the phase comparator returns to the disabled state. The result of this comparison is transmitted through the charge pump circuit 7 to the output of the loop filter 8;
3. It is reflected in the pressure and the oscillation frequency of the VCO 9 is controlled. The output voltage of the loop filter 8 is then applied to the read data signal 11.
It is held until the next pulse arrives.

This pressure is applied to prevent the phase comparator 6 from performing erroneous phase comparison.

[Problem that the invention seeks to solve]

The amount of delay of a delay element used in a phase-locked circuit for a magnetic disk device is determined by the frequency pull-in range of the phase-locked circuit and the phase margin with the CO clock signal (temporal difference of the data signal) when decoding the read data signal. This affects the range in which misreading will not occur even if the position shifts. That is, when the delay amount of the delay element changes, the frequency pull-in range becomes narrower and the phase margin decreases.

This did not pose much of a problem when the transfer rate of the magnetic disk device was low, but as the transfer rate increased, the phase relationship between the continuous data signal and the clock signal for decoding changed by several nanometers. Nowadays, strict precision on the order of seconds is required, and it is essential to increase the precision of the amount of delay time.

, 4.

However, in the above conventional technology, the specified delay element is installed in the system without adjustment, or is adjusted only when installed, so it is not affected by variations in element characteristics, temperature changes, aging, etc. There were problems with reliability.

Therefore, an object of the present invention is to provide a phase locked circuit that can set the optimum amount of delay even after being incorporated into a system.

[Means for solving problems]

In order to achieve the above object, the present invention provides a phase-locked loop (PLL) which receives a data signal including a plurality of pulse periods through a delay element, and enables a phase comparison operation by the data signal before delay. ) circuit, and outputs a clock signal phase-synchronized with the data signal from the PLL circuit, wherein the delay element is a tapped delay element, and a reference clock signal corresponding to a predetermined amount of delay is used. The present invention is characterized in that a delay amount adjustment means is provided for adjusting the delay amount of the tapped delay element.

In one embodiment of the present invention, the delay amount adjustment means receives the reference clock signal before the delay by the tapped delay element and the clock signal after the delay, and checks the delay amount of the tap output. and a tap switching circuit that switches and sets the tap of the tapped delay element according to the check result of the delay amount check circuit, and produces the maximum delay amount that does not exceed the predetermined delay amount. Select the delay element taps. The predetermined amount of delay can be determined by the pulse width of the reference clock signal. This pulse width is the duty
In the case of a 50-inch reference clock signal, its period T is T/2. Further, the maximum delay iTd of the tapped delay element is the pulse width <T d <T, and in the case of a duty-50 reference clock signal, 'I'/2<Td<T.

As another embodiment of the present invention, the delay amount adjusting means includes:
The delay amount check circuit further includes a switch that selects one of the data signal and the reference clock signal and introduces the selected signal into the tapped delay element, and when the delay amount check circuit receives the mode switching pulse signal, the delay amount check circuit selects one of the data signal and the reference clock signal and inputs the selected signal to the tapped delay element. A signal is selected and a check operation is started, and after a target tap is selected, the switch is made to select the data signal and the check operation is stopped.

[Effect]

The present invention provides a phase synchronized circuit that uses a delay element for a data signal having a mixture of multiple pulse periods, enables a phase comparator with the data signal before delay, and uses the data signal after delay for phase comparison. By using a tapped delay element as the delay element, it is possible to select the tap with the optimal amount of delay based on the reference clock signal corresponding to the desired amount of delay, so the phase-locked circuit can be used regardless of variations in delay time. 1~22+! You can maintain the maximum number pull range.

〔Example〕

7. Hereinafter, the present invention will be explained in detail with reference to FIGS. 1 to 6.

FIG. 1 shows a block diagram of an embodiment of a phase locked circuit according to the present invention, and FIG. 2 shows a detailed circuit diagram of the main blocks of FIG. 1. In addition, the same components as those shown in Fig. 5 include:
They have the same reference numbers.

In FIG. 1, PLL 5 is the same as that shown in FIG. The delay element 2 is a tapped delay element having a plurality of taps, and under control by the tap switching circuit 4, signals with different delay amounts can be extracted from the selected taps. As the input signal to the delay element 2, the read data signal 11 or the reference clock signal 12 is selected by the switch 1. The delay amount check circuit 3 checks the state of the input signal 13 of the delay element 2 when the tap output signal 14 of the delay element 2 rises, and outputs the result as the delay amount check signal 15. This delay amount check signal 1
5 controls the switch 1 and the tap changeover circuit 4.

Phase comparison within PLL5, 8.

The device 6 receives the delay element input signal 13 as an enable signal and receives the delayed signal output signal 14 as a signal input.

The phase-locked circuit of the present invention is normally in a normal state in which the switch 1 selects the read data signal 11, and upon receiving the mode switching pulse signal 18, shifts to a check state in which the optimum delay amount of the delay element 2 is selected. . Once the optimal delay amount is selected in the checked state, the original normal state returns.

Next, a detailed circuit diagram of the tapped delay element 2 and the delay amount adjusting means (the delay amount t-extracting circuit 3, the tap switching circuit 4, and the switch 1) shown in FIG. 1 will be explained with reference to FIG.

First, the tapped delay element 2 is composed of a plurality of buffer gates 20 connected in series and a maltebrake f21 that receives signals at both ends of the buffer gates 20 and at each connection point. Since each buffer gate 20 has its own propagation delay time, by changing the tap from which the signal is taken out by the multiplexer 21, the delay time can be switched in minute unit time.

The switch 1 includes an AND gate 1b receiving a reference clock signal 12 and a delay amount check signal 15, an inverter 1c receiving the delay amount check signal 15, an AND gate 1a receiving a read data signal 11 and the output of the inverter 1C, and an AND gate 1b receiving a reference clock signal 12 and a delay amount check signal 15. ) 1 a + 1 b An OR game that receives the Ryokawa force) 1 d.

The delay amount check circuit 3 includes a D-type edge-triggered flip-flop (hereinafter referred to as DFF) 23 with a set/reset function and NAND gates 24 and 25.

The DFF 23 receives the mode switching pulse signal 1st as a reset signal, and receives the output of the NAND gate 25 as a set signal. Further, the DFF 23 receives the delay element input signal 1 at its D input terminal at the rising edge of the output pulse of the delay element 2.
3 and outputs the inverted signal as the delay amount check signal 15 to the inverted (possible) output terminal. This delay amount check signal 15 is input to the inverter 1C of the switch 1 and the tap switching circuit 4.

The tap switching circuit 4 includes a counter 22 with a count enable and an inverter 4a.

The counter 22 receives the chip enable terminal CBK delay amount check signal 15, the reset terminal R receives the mode switching pulse signal 18, and the clock terminal CK receives the delay element output signal 14 via the inverter 4a. The output of the counter 22 controls the multiplexer 21.

Next, the operation of the embodiment shown in FIG. 2 will be explained with reference to the timing chart shown in FIG.

In the phase locked circuit shown in FIG. 2, in the normal state, the DFF 25 is in the set state (the inverted output is low), so the switch 1 selects the read data signal 11 and the counter 22
The dice are enabled. In this state, when the mode switching pulse signal 18 is input, the DFF 23 is reset and the counter 22 is reset to 0. That is, it shifts to a checked state. When the DFF 25 is reset, the delay amount check signal 15 becomes valid. the result,
The counter 22 is enabled to count and the switch 1 selects the reference clock signal 12.

11 In this embodiment, the reference clock signal 12 is a 50-ch pulse signal having a period twice the desired amount of delay. Further, when the tap switching signal 16 which is the output of the counter 22 is 0, the multiplexer 21 selects the tap with the maximum delay amount of the delay element, and as the output of the counter 22 increases, the multiplexer 21 sequentially decreases the delay amount. ◇ After receiving the mode switching pulse signal 18, each pulse of the reference clock signal 12 is passed through the switch 1 to the delay element 2.
The state of the delay element input signal 13 is taken in at the rising edge of this delay pulse 14.

Since the maximum delay amount Td of the delay element 2 is selected to be T/2 < T d < T, where T is the period of the reference clock signal, the reference clock signal 12 at the time of the rise of the delay pulse 14 is low. . Therefore, the delay amount check signal 15 remains high, the counter 22 increments at the falling edge of the delay pulse 14, and the tap switching signal 16 becomes 1.

At the rising edge of the next delayed pulse 14, the reference clock signal 12 is still 12 degrees low, and at the falling edge of the delayed pulse, the counter 22 is again incremented and the tap change signal 16 becomes 2. In this way, the state of the reference clock signal 12 at the time of the rise of the delayed pulse 14 is checked while the counter 22 is sequentially incremented. In the example of FIG. 3, when the count value reaches 3, the state of the reference clock signal 12 at the rising edge of the delay pulse 14 becomes high for the first time, and the inverted output of the DPF 23 (
The delay amount check signal 15) becomes low. As a result, the counter 22 is disabled and the current count value (
In this case, 3) is held and the switch 1 is switched to the read data signal 11 side.

That is, the state returns to normal.

When the check state ends and the normal state returns, the tap with the maximum delay amount that does not exceed the desired delay amount, the above-mentioned time T/2, is selected as the delay amount of the delay element 2. .

Note that the check operation may be performed at any time, such as when the power is turned on, or before or after the read operation, but if it is performed periodically, it is possible to cope with short-term delay time fluctuations such as temperature changes.

In the embodiment described above, the taps are switched in order from the tap with the largest amount of delay, but if consideration is given to the adverse effects of burst signal generation when switching taps, it may be possible to force the taps to be switched in order from the tap with the smallest amount of delay. .

〔Effect of the invention〕

According to the present invention, it is possible to constantly compensate for variations in the amount of delay of the delay element due to variations in characteristics, temperature changes, secular changes, and equal pressure using the reference clock signal. Decrease in the phase margin for the clock signal can be suppressed. Therefore, it is suitable for use in a magnetic disk device with a high transfer rate, and the data error rate can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 1 is a detailed circuit diagram of the embodiment, FIG. 3 is a timing chart for explaining the circuit operation of FIG. 2, and FIG. 4 is a
The block diagram of a conventional general phase synchronization circuit, FIG. 5, is as follows.
FIG. 6, a block diagram of a conventional phase synchronization circuit installed in a magnetic disk drive, is a timing chart for explaining the operation of a phase comparator. DESCRIPTION OF SYMBOLS 1... Switch, 2... Delay element with tap, 3... Delay amount check circuit, 4... Tap switching circuit, 5... PLL. 6...Phase comparator.

Claims (1)

[Claims] 1. A phase-locked loop (PLL) circuit that receives a data signal having a mixture of a plurality of pulse periods via a delay element, and whose phase shift comparison operation is enabled by the data signal before the delay. In a phase-locked circuit that outputs a clock signal whose phase is synchronized with the data signal from the PLL circuit, the delay element is a tapped delay element, and the tap is set using a reference clock signal corresponding to a predetermined amount of delay. 1. A phase synchronization circuit comprising a delay amount adjusting means for adjusting a delay amount of a delay element. 2. The delay amount adjusting means includes a delay amount check circuit that receives the reference clock signal before the delay by the tapped delay element and the reference clock signal after the delay and checks the delay amount of the tap output; and a tap switching circuit that switches and sets the tap of the tapped delay element according to the check result of the quantity check circuit, and the tap of the tapped delay element that produces a maximum delay amount that does not exceed the predetermined delay amount. The phase synchronized circuit according to claim 1, characterized in that the phase synchronization circuit is selected. 3. The delay amount adjusting means further includes a switch for selecting one of the data signal and the reference clock signal and introducing it into the tapped delay element, and the delay amount check circuit receives the mode switching pulse signal. when the switch selects the reference clock signal and starts a check operation, and after the target tap is selected, the switch selects the data signal and stops the check operation. A phase locked circuit according to claim 2.