SU1615799A1 - Device for phase synchronization of disk storage of digital data - Google Patents

Abstract

The invention relates to the accumulation of information, namely, synchronization devices for digital data storage devices. The invention makes it possible to speed up the process of the initial establishment of synchronism in the process of reproducing data in a disk drive. The main synchronization mode is performed by a phase locked loop, which includes ringed phase comparator 6, charge pump 1, filter 2, and controlled oscillator 3. At initial synchronization, the signals sent to control buses 10, 12 replace phase comparator 6 loop on the frequency-phase comparator 5, and also connect an additional block 18 of the charge pump. This dramatically increases the speed of the phase self-tuning in the device. 3 il.

Description

The invention relates to a technique for accumulating digital data, in particular, to devices for synchronization when recording and reproducing data in magnetic disk drives.

The purpose of the invention is to increase the speed by reducing the time to establish synchronism.

Figure 1 shows a phase synchronization device for a digital storage disk; figure 2 - timing charts of signals in the process of fpex the device from one mode to another bots; in fig. 3 - timing charts of control signals. For convenience of description, the communication lines in Fig. 1 and the corresponding diagrams in Fig. 2, 3 are denoted by the letters A and P.

The device contains serially connected first charge pumping unit 1, filter 2, controlled generator 3 with output meander-type pulses, frequency divider 4 and frequency-phase, comparator 5. There are phase compiler 6, one input connected to the information bus 7, and others - to the inverted output of the controlled oscillator 3. and. (the device's bus 8, the first trigger 9, connected by the D input to the control bus 10 (mode control signal) and the second trigger 11, connected by the D input to the additional control bus 12 (signal y speed systematic way) In addition, the device includes elements OR 13 -. 15, AND gates 16, 17 and the second pump unit 18 charge.

Filter 2 can serve as an integrating capacitor connected between the input of the controlled generator 3 and the common bus. The frequency-phase comparator 5 is made on a pair of D-flip-flops 19 and 20 with a common reset circuit through the element And - 21. C-inputs

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flip-flops 19 and 20 serve as signal inputs of the frequency-phase comparator 5, and their combined D-inputs as the input of the prohibition of the frequency-phase comparator. Phase comparator 6 contains a dynamic trigger 22, the element And 23 and one-shot 24. Dynamic R-input trigger 22 and one of the inputs of the element And 23 serve as signal inputs of the phase comparator b, and the other input of the element And 23 - its input prohibition. The pulse duration of the one-shot 2-4 is chosen equal to half the nominal period of the output signals of the generator 3, which is equal to the so-called unit interval of the digital signal of the reproduced data. For example, if, when reproducing an MPM code, the instantaneous periods of the data signal (IT; 1.5T; 2T) are 100, 150, and 200 NS, then the unit interval, calculated as the largest common divisor of the instant periods, is 50 NS, and the duration the one-shot pulse you brat equal to 25 no. The dividers 4 frequencies in this particular exemplary embodiment, calculated on the MPM -data, are a frequency divider by two. Each of blocks 1 and 18 of pump for a row contains controlled (switched) generators of flowing 25 and 26 and flowing in 27 and 28 currents, respectively. In this case, in each charge pump the absolute values of the flowing and flowing currents are equal to each other, the absolute values of the currents in the second charge pump 18 are much better, for example an order of magnitude greater than the absolute values of the currents in the first charge pump 1. Each of the current generators 25 to 28 is preferably implemented as a differential current switch with a DC generator in the emitter circuit.

In describing the operation of the device, positive logic is used, i.e. a low voltage level is taken as a logic zero, and a high one as a logical unit. It is assumed that the input digital data signal is encoded by the IMF method and recorded by sectors in the track. Each sector consists of a synchronization field, where the zone of solid zeroes is located (the period is equal to two unit intervals) and the data field. The synchronization field captures the frequency and phase of the input signal by the timing device.

The device is capable of operating in three modes, depending on the control signals at the input terminals 10, 12: the speed capture mode at the levels of the logical unit at the output terminals 10 and 12;

the mode of frequency-phase self-tuning with a logical unit at terminal 10 and with logical zero at terminal 12; phase-locked state mode, when a logical zero level is present at both input-5 terminals 10 and 12, This is the main operation mode of the device,

In the high-speed acquisition mode, the logical level of the unit (Fig. 2B) is transmitted 10 through the trigger 11 to the combined inputs of the AND elements 16 and 17 (Fig. 2H), allowing the phase error signal to pass through them to the inputs of the charge pump 18. The output of the trigger 9 is held at the level of a logical zero (FIG. 2M), which is prohibited (the input signals pass through the AND 23 element and, therefore, prohibit the operation of the phase comparator 6. This same level allows the operation of the frequencies –– 0 HC – phase comparator 5 At one input of the frequency-phase comparatorz 5, from the input terminal 7, pulses A of the data array synchronization field are received, representing a sequence of zeros, i.e., a regular sequence of pulses with a period twice the unit time interval TQ (period 2) The second input of the frequency-phase comparator 0 from the output of the 4 frequency divider receives feedback pulses with a period also of the 2nd (FIG. 2D). 8. The initial state of the two trigger 19 and 20. Frequency-phase comparator 5 is cocked. Let the next input pulse 29 (Fig. 2A) be shifted from its nominal position shown by the dotted line and by time At to the advance direction. Then, with its front, it collects the P trigger 19, in the inverse output of which (FIG. 2E) a logical unit level of 30 appears. This impulse is a passage u through the element OR 13, on the other input of which there is a logical zero (FIG. 2I) from the output of the phase comparator 6, to the input of the generator 25 of the flowing current in the charge pump 1 and further through the element 16 to the input of the generator 26 of the flowing current in the block 18 charge pump. Thus, the total leakage current starts to flow to the input of the filter 2 (diagram 31, fit.2P), which leads to an increment (diagram 32) of its output voltage (Figure 2P). At the moment when the front of the feedback pulse 33 arrives from the output divider 4 frequency (fig.2D) D-flip-flop 20 is reset in the frequency-phase comparator 5 (fig.2ZH). In this case, two single logic levels at the inputs of the element And 21, the pulse

the logical zero from its output returns both triggers 19 and 20 to the initial cocked state. Thus, the formation of a pulse 31 of the flowing current at the input of the filter 2 is completed. Its duration is equal to the mismatch D t. The increment of the control voltage obtained after frequency-phase comparison made (Fig. 2P) corrects the frequency of the controlled oscillator 3 in the direction of compensating for the recorded phase error.

In the opposite case, when the input pulse (diagram 34, fig.2A) lags by time At from its nominal position a pulse 35 (figure 2G) of the phase error is formed at the other output of the frequency-phase comparator 5, which passed the elements OR 14 And, 17, causes the pulse 36 (fig.2P) to flow in at the input of the filter 2 and the corresponding negative increment (diagram 37, fig.2P) of the control voltage at the input of the generator 3.

Since in this mode, the amplitude of the current pulses at the input of the filter 2 is summed up from the amplitudes of the current pulses of both blocks 1 and 18 of the pumping charge (and the current of block 18 is an order of magnitude greater than the current of block 1), the voltage of filter 2 changes quickly, therefore, high capture speed.

The device enters a second mode of operation with a relatively slow frequency-phase-locked loop after the speed control signal is terminated at input terminal 12 and the voltage level is set to zero. At the same time, at the end of the next mismatch pulse by the decay of the pulse 38 at the output of the element OR 15, the voltage level at the output of the trigger (FIG. 2H) becomes zero and prohibits waiting for phase error signals through elements 16 and 17. From this point on, each phase error signal (for example, chart 39, fig.2E) is supplied only to the charge pumping unit 1 and the current pulse amplitude (chart 40, fig.2P) at the input of the filter 2 is sharply reduced. This leads to an increase in the inertia of the loop frequency-phase-locked loop.

When the unit level signal (Fig. 2B) at the input terminal 10 is terminated, then by the next pulse 41 (Fig. 2L), the output of the trigger 9 is set to a single voltage level, which prohibits the operation of the frequency-phase comparator b. Thus the device

goes into the third mode of operation - only phase-locked loop with high inertia. In this mode, the device is capable of operating with coded irregular input signals. Since the phase relation between the input and output signals is the same. as in the second mode, the transition from one mode to another is not accompanied

10 transition process.

In this basic mode of operation, the phase self-tuning of the output clock signals is performed as follows. Each output pulse at position 7, passing through element 23, triggers a one-shot 24 and sets trigger 22 at phase comparator 6. At both outputs (And, K) of phase comparator 6, logical 1 appears, which, having passed through elements OR 13 and 14 include both generators 25 and 27 in block 1 of the charge pump. Since the indicated currents are equal in absolute value and oriented relative to the output node in block 1

5 opposite, they compensate each other and to the input of the filter 2 then; does not flow. The result of phase comparison depends on what happens earlier: the one-shot pulse ends (after half

0 unit interval) or the front of the output clock signal will come from the inverted output of the controlled oscillator 3. In Fig. 2, this clock signal is not shown, its front corresponds to the decline of the signal G at the high end of the normal oscillator 3.

There are three cases. In the first case, the sync front (pulse decay, fig.2G) coincides with the moment of termination of the one-shot 24 pulse. Input signal 42, with its front, triggers trigger 22 (diagram 43, figure 24) and starts one vibration 24 (diagram 44, fig.2K) . Impulse44 single vibrator 24 ends up with a time of 0.5 Go. At the same moment, on a decline 45

5, the signal of the controlled oscillator 3 is reset to the initial state by trigger 22, i.e. pulse 43 ends. Current does not flow into filter 2, therefore, the voltage level reached earlier remains at its output

0 and the frequency of the controlled oscillator 3 does not change.

If the pulse h6 arrives at the input terminal 7 before the expected moment at At (the nominal position is shown by dashed lines), then at this time A t will become wider than the pulse 47 of the flip-flop 22, the pulse duration 48 of the one-shot 24 will remain unchanged. Therefore, as a result, the input of the filter 2 receives a pulse 49 of the following

current from the charge pump unit 1. The voltage (FIG. 2P) at the output of the filter 2 is incremented and the frequency of the controlled oscillator 3 is corrected in the direction of compensating the phase mismatch.

The device works in exactly the same way in the opposite case, when the next input pulse 50 is delayed relative to its nominal position by D t. In this case, the pulse 51 of the trigger 22 is shorter in duration than the pulse 52 of the single vibrator 24, which leads to the appearance of a current pulse 53 (FIG. 2P) at the input of the filter 2. The voltage at its output receives a negative increment (FIG. 2P), the frequency controlled generator 3 is adjusted in the desired direction.

Timing diagrams (FIG. 3) illustrate the effect of accelerated synchronization in the device by connecting the second charge pump 18 when the control signal of the speed control signal (B) arrives at the input terminal 12. In the data sector synchronization field (FIG. 3) by the signal By controlling the mode on the input terminal 10, the device switches to the frequency-phase comparison mode. wherein the capture band is equal to the hold band. If the speed control signal is not received in this case, then the transient capture process, which is judged by the voltage at the output of the filter 2 (Fig.ZR), will be long. If, however, the signal B of the speed control is received, then the time of the transition process is sharply reduced.

Claims (1)

Invention Formula A phase synchronization device for a digital data storage device containing a series-connected first charge pump, a filter, a controlled oscillator, a frequency divider and a frequency-phase comparator, as well as a phase comparator, a first trigger connected to the control bus by a D input, and a second trigger information bus and an output bus, where the phase comparator is designed as a dynamic trigger and a single vibrator, the outputs of which are the corresponding outputs of the phase comparator, the input of a single vibrator connected to one input of a dynamic trigger, the other input of which is one input of the phase comparator and connected to the output bus, which distinguishes - so that, in order to increase speed by reducing the time to establish synchronism, a second charge pump was inserted, connected by an output to the output of the first charge pump a, three OR elements, the first and second AND elements, an additional AND element in the phase comparator, connected by an output to one input of a dynamic trigger, an additional control bus connected to the D input of a second trigger, while the first and second elements OR are connected by one input to the corresponding outputs of the phase comparator, other inputs to the corresponding outputs of the frequency-phase comparator, the output of the first and the output of the second OR elements are connected to the corresponding inputs of the first pumping unit, with one of the inputs n The first and second elements And through the third element OR with the C inputs of the first trigger and the second trigger, the output of which is connected to the other inputs of the first and second elements AND, the outputs of which are connected to the corresponding inputs of the second charge pump, the inverse output of the first trigger connected to an additional input of the prohibition of the frequency-phase comparator and an additional input of the prohibition of the phase comparator, which is one input of the additional element AND, the other input of which is another input of the phase comparator and connected to the data bus and to another input of the frequency-phase comparator, and the additional inverting output of the controlled generator is connected to the output bus. 1 -L / -M FIG 2 Ceffmop S .З Senor L V