SU1501292A2 - Binary signal regenerator - Google Patents

Abstract

The invention relates to communication technology. The purpose of the invention is to provide automatic regeneration of the regenerator when the speed of the input information signal changes at a high noise immunity of the regenerator. The regenerator contains multiplier 1, narrowband filter 2 consisting of D-flip-flop 3, voltage adder 4, low-pass filter 5 and voltage controlled by r-g 6 and D-flip-flop 7. The goal is achieved by introducing an input signal simulator 9 and frequency detector 8, which is used to tune in frequency and phase of Mr. 6. If the clock frequency of the input information signal at a given time is higher than the frequency of Mr. 6, then the signal of frequency detector 8 will cause Mr. 6 to tune in frequency back side. This restructuring will continue until a signal with a duty ratio of two is at the output of Mr. 6. The further adjustment of the phase of g-6 is carried out by a phase-locked loop. When changing the transmission rate of the information signal, the regenerator restructuring mechanism described above is repeated. 2 hp ff, 2 ill.

Description

1 (61) 1125757

(21) 4280960 / 24-09

(22) 07/09/87

(46) 08/15/89. Bul No. 30

(72) V.F.Aleksandrov, D.P.Kischuk

and N.N. Marishichev

(53) 621.394.64 (088.8)

(56) USSR Author's Certificate No. 1125757, cl. H 04 J 3/06, 1981.

(54) BINARY SIGNAL REGENERATOR

(57) The invention relates to communication technology. The purpose of the invention is to provide automatic regeneration of the regenerator when the speed of the input information signal changes at a high noise immunity of the regenerator. The regenerator contains a multiplier 1, a narrowband filter 2 consisting of a D-flip-flop 3, a voltage adder 4, a low-pass filter 5 and controlled by a voltage r-6 and a D-flip-flop 7. The goal is achieved by introducing an input signal simulator 9 and frequency detector 8, which is used to tune in frequency and phase of Mr. 6. If the clock frequency of the input information signal at a given time is higher than the frequency of Mr. 6, then the signal of frequency detector 8 will cause Mr. 6 to tune in frequency back side. This restructuring will continue until a signal with a duty ratio of two is at the output of Mr. 6. The further adjustment of the phase of g-6 is carried out by a phase-locked loop. When changing the information signal transmission rate, the regenerator rebuilding mechanism described is repeated. 2 hp f-ly, 2 ill.

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The invention relates to the technique of BON-1I and can be used in communication systems with various types of modulation and, above all, in communication equipment intended for transmitting digital information with different speeds of digital flow, and is an improvement of the known invention by the author. St. No. 1125757.

The purpose of the invention is to provide automatic regeneration of the regenerator when the speed of the input information signal changes at a high noise immunity of the regenerator.

FIG. Figure 1 shows the structural electrical circuit of the proposed regenerator; in fig. 2 shows an embodiment of a frequency detector. The binary signal regenerator (Fig. 1) contains a multiplier 1, a narrowband filter 2 consisting of a D-flip-flop 3, a voltage adder 4, a low-pass filter 5, a voltage-controlled oscillator 6, a D-flip-flop 7, a frequency detector 8 , input 9 simulator. Frequency detector 8 contains (Fig. 2) first and second frequency dividers 10 and 11, RS-trigger 12.

The regenerator works in the following way.

The input signal (Fig. 1) through multiplier 1 is fed to a narrowband filter 2, where the clock frequency of the input signal is extracted. The selected clock signal arrives at the B-triprer 7 synchronous input and the time of changing the polarity of the clock signal from negative to positive sets the D-trigger 7 to the state corresponding to the polarity of the input signal that enters this mantin at its information input. As a result, a regenerated binary signal appears in the R-Trit-Hera 7 code, which arrives at the second input of the multiplier 1 and provides at its output a reduction of the positive polarity of the signal (at the input of the narrowband) filter 2) after each change of polarity signal, (lp n.tg from the output of multiplier 1 enters the synchronous input of the second B-flip-flop 3, and on its informational go, gtt- clock frequency from the output of the generator 6. Thus, P-trshp: p 3

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1 1 completes the phase detector function. Nai1P1e, proportional to the difference il aa of the input signal and the frequency TOBofi () 1, c in the D-flip-flop 3 is fed to the voltage adder 4, the second input of which is supplied by the voltage output from the frequency detector 8. These voltages are added and through the low-pass filter 5, to the control input of the generator 6, rearranging it in frequency and phase. This process continues until the input signal is synchronized completely and the clock frequency of the generator 6. At the same time, the input signal is fed to the first input of the frequency detector 8, and its second input is fed from the output of the input simulator 9, which forms a pseudo-random center. structure of the input signal. The input signal liMHTaTop 9 can be made in the form of a pseudo-random sequence generator (SRP), the input of which is supplied with a clock frequency from the output of the generator 6. The choice of the frequency detector circuit 8 is due to the appearance of O or G in the input information signal for a sufficient time interval tny. Poetog-riepebui and the second dividers 10 and 11 of the frequency (Fig. 2) have such a division factor that provides an approximate simultaneity of the appearance and mylc on 1 "output. For example, if an information signal has a pseudo-random sequence structure, i.e. the probability is 0 or 1 rv.vna 0.5 n-1 a sufficient time interval, the capacity of the counter of the first frequency divider 10 should be four times the capacity of the counter of the second de: n-1 body 1 1 frequency, which provides an approximate simultaneity of the appearance of pulses at the inputs of the RS flip-flop 12. If the information signal in this particular channel has a structure different from that of the memory bandwidth, then the division factors of one of the dividers 10 or 11 are pre-selected so that the frequency of occurrence of the pulses at the RS-flip-flop 13 was about about otherness at equal clock input signal frequency and the frequency of g-for generators 6. Further, at shtat5150

During the operation of the r-gimbal, its reorganization is carried out automatically.

If the clock frequency of the input information signal at a given time is higher than the frequency of the generator 6, then the first pulse at the output of the second frequency divider 11 resets the first frequency divider 10 to zero and turns the RS-

trigger 12. For example, to position 1. Voltage 1 is fed to the input of adder 4 and through the low-pass filter 5 tunes the frequency of generator 6, so that at the output of the first frequency divider 10 a pulse appears earlier than at the output of another frequency divider 11 . This pulse resets the second frequency divider 11 to zero, and the RS flip-flop 12 to the O position, forcing the generator 6 to tune in frequency in the opposite direction. This process continues until there is an equality of the frequencies of the appearance of pulses at the corresponding inputs of the RS flip-flop 12, i.e. At the output of generator 6, a signal appears with a duty ratio of 2 and the generator 6 stops in frequency, and its further j-phase is performed by the PLL when changing the transmission speed of the information signal, the specified regenerator tuning mechanism repeats.

Claims (3)

Invention Formula 1, Regenerator binary signal auth. St. No. 1125757. Characterized in that, in order to provide automatic adjustment 0 five 0 five 0 regenerator when changing the speed of the input information signal with a high noise resistance of the regenerator, input signal simulator connected in series and a frequency detector, the output of which is connected to the control input of a narrowband filter, the first input of the multiplier is connected to the second input of the frequency detector, and the output of the narrowband filter is connected to input simulator input. 2. The regenerator of claim 1, wherein the narrowband filter comprises a D-flip-flop connected in series, a voltage adder, a low-pass filter and a voltage controlled oscillator, the output of which is connected to the D-flip-flop information input The counting input of which is the information input of the narrowband filter, the control input and the output of which is, respectively, the second input of the voltage adder and the output of the voltage controlled oscillator. 3. The regenerator according to claim 1, characterized in that the frequency detector comprises a serially connected first frequency divider, a second frequency divider and an RS flip-flop, to the second input of which the output of the first frequency divider / t is connected, the first input of which is connected to the output of the second frequency divider The second input of which and the second input of the first frequency divider are respectively the first and second inputs of the frequency detector, the output of which is the output of the RS flip-flop.