JPH071869Y2 - Receiving clock signal regeneration circuit with clock signal switching circuit for digital communication device - Google Patents

Description

[Detailed Description of the Invention] (Industrial field of application) The present invention is compatible with data communication systems with different transmission speeds by switching the reception / reproduction clock signal frequency by setting an external terminal in a general-purpose digital communication device using a wireless line. The present invention relates to a device that can be used.

(Prior Art) FIG. 2 is a block diagram of an example of a received clock signal reproduction circuit of a conventional digital communication device.

In FIG. 2, 1 is an input terminal, 2 is a phase comparison circuit, 3 is a frequency division ratio control circuit, 4 is a master clock generator, 5 is a variable frequency divider, 8 is a fixed frequency divider, and 9 is an output terminal. .

The circuit shown in FIG. 2 constitutes a digital phase-locked loop, and the phase change signal extracted from the data by the NRZ code received in the receiving section of the digital communication device is applied to the phase comparison circuit 2 via the input terminal 1. . On the other hand, the output frequency of the master clock generator 4 is frequency-divided by the variable frequency divider 5 and the fixed frequency divider 8 and applied to the phase comparison circuit 2 as the received reproduction clock signal to obtain the phase change signal extracted from the data. The phase is compared with the phase, and the phase information based on the advance or delay of the phase between the two signals is output to the output of the phase comparison circuit 2. The phase information is applied to the frequency division ratio control circuit 3, and when the phase advance or delay phase information is repeatedly input a fixed number of times, the frequency division ratio control circuit 3 switches the frequency division ratio of the variable frequency divider 5. The variable frequency divider 5 can be switched to M-1 or M + 1 with reference to the frequency division ratio M, and if the phase information detected by the phase comparison circuit 2 is delay information, The frequency division ratio is set to M-1, and the output frequency of the variable frequency divider is increased. On the other hand, the frequency division ratio control circuit resets the frequency division ratio of the variable frequency divider to M after counting the output frequency of the variable frequency divider by a fixed number, so that the frequency divided by the fixed frequency divider 8 is received. The reproduction clock signal becomes short and the phase advances. Further, when the phase information is the information which continuously advances, the division ratio of the variable frequency divider is M
Set to +1. Therefore, the output frequency of the variable frequency divider becomes low, and after the output frequency is counted a fixed number as in the above, the frequency division ratio of the variable frequency divider is reset to M, so that the frequency is divided by the fixed frequency divider 8. In addition, the interval of the received reproduction clock signal becomes long and the phase is delayed. In this way, by switching the variable frequency divider 5 frequency division ratio for a short time, it is possible to reproduce the reception clock signal synchronized with the phase change signal extracted from the data.

(Problems to be solved by the invention) However, in a general-purpose digital communication device used for a data communication system having different transmission speeds, a reception / reproduction clock signal having a different frequency is required to support the transmission speed. . In such a case, it is necessary to change the frequency of the master clock signal generator of the reception clock signal regeneration circuit or change the frequency division ratio of the frequency divider, but if the transmission speed is high, simply change the master clock signal generator When the frequency is increased, there are problems that the operation becomes unstable beyond the operating range of the digital element that constitutes the digital circuit, and that it takes some time to change the frequency.

The present invention eliminates the above-mentioned problems and provides a device capable of instantly responding to different transmission speeds in a data communication system having different transmission speeds by easily switching the frequency of the reception / reproduction clock signal from the outside. The purpose is to do.

(Means for Solving the Problems) The present invention sets the output frequency of the master clock generator to 3 by using the phase information from the phase comparison circuit of the reception clock signal regeneration circuit configured by the digital phase lock loop.
A plurality of fixed frequency dividers having different division ratios between a variable frequency divider capable of frequency division in stages and a fixed frequency divider for dividing the output frequency of the variable frequency divider to obtain a reception clock signal. A frequency divider and a frequency switching circuit are provided, and the frequency switching circuit for switching between the output frequency of the variable frequency divider and the frequency divided by a plurality of fixed frequency dividers having different frequency division ratios is external. A terminal for connecting a changeover switch for more control is provided, and a plurality of received reproduction clock signals can be easily obtained by operating the changeover switch.

(Function) The present invention is a general-purpose digital communication device in which a changeover switch for changing over the received and reproduced clock signals of different frequencies is provided externally so as to correspond to the data communication system of different transmission speeds. .

The switching method is such that a plurality of fixed frequency dividers having different division ratios and a frequency switching circuit are provided in the reception clock signal regenerating circuit configured by the digital phase-locked loop as described above, and a plurality of frequency switching circuits are provided. Different frequencies from the fixed frequency dividers with different frequency division ratios are applied to the input terminals of, and the switching information is operated by operating the changeover switch provided outside through the frequency changeover circuit via the external terminals. The output of the switching circuit obtains different frequencies, and the subsequent fixed frequency divider obtains reception and reproduction clock signals of different frequencies.

(Embodiment) FIG. 1 is a block diagram of an embodiment of the present invention.

In FIG. 1, 1 is an input terminal, 2 is a phase comparison circuit, 3
Is a frequency division ratio control circuit, 4 is a master clock generator, 5 is a variable frequency divider, 6 is a fixed frequency divider, 7 is a frequency switching circuit, 8
Is a fixed frequency divider, 9 is an output terminal, 10 is an external terminal, and 11 is a changeover switch.

Although the present embodiment shows the case of switching between two types of received and reproduced clock signals, the fixed frequency divider 6 is a plurality of fixed frequency dividers having different frequency division ratios, and the frequency switching capable of switching the respective output frequencies. A container can be provided. The phase change signal extracted from the data signal by the NRZ code which is the reception output of the digital communication device is applied to the phase comparison circuit 2 via the terminal 1. On the other hand, the output frequency of the master clock generator 4 is divided by the reference frequency division ratio M in the variable frequency divider 5, a part of the output frequency is directly applied to the input terminal A of the frequency switching circuit 7, and the other The frequency division is performed by the fixed frequency divider 6 and applied to the input terminal B of the frequency switching circuit 7, and either frequency applied to the input terminal A or B according to the operating state of the frequency switching circuit 7 is Appearing at the output terminal D of the frequency switching circuit 7, the frequency is divided by the fixed frequency divider 8 and applied to the phase comparison circuit 2 as a reception reproduction clock signal. In the phase comparison circuit, the phase of the phase change signal extracted from the reception data is compared with the phase of the reception reproduction clock signal divided by the fixed frequency divider 8, and the output of the phase comparison circuit is output with both phases. Outputs phase information regarding lead and lag. The phase information is applied to the frequency division ratio control circuit 3, and when the phase advance or delay phase information is repeated a certain number of times, the frequency divider control circuit 3 switches the frequency division ratio of the variable frequency divider 5.

The variable frequency divider 5 uses the frequency division ratio M as a reference to divide the frequency division ratio M-1.
Alternatively, when the phase information indicates a delay, the output frequency of the variable frequency divider 5 is increased as the frequency division ratio M-1 of the variable frequency divider 5 and the output frequency is divided by the frequency. After the constant number is counted in the frequency ratio control circuit 3, the frequency dividing ratio of the variable frequency divider 5 is reset to M. Therefore, even if the number of pulses counted by the subsequent fixed frequency divider 8 is the same, the counting time becomes short, The phase of the received reproduction clock signal, which is the output frequency of the fixed frequency divider 8, advances. When the phase information indicates a lead, the frequency division ratio of the variable frequency divider is set to M + 1, the output frequency of the variable frequency divider is reduced, and the output frequency is fixed by the frequency division ratio control circuit 3. After counting, the frequency division ratio of the variable frequency divider 5 is reset to M, so that the phase of the received reproduction clock signal, which is the output frequency of the following fixed frequency divider 8, is opposite to the above-described phase delay. As a result, the received reproduction clock signal operates in synchronization with the phase change signal extracted from the received data.

In the present invention, the variable frequency divider 5 is used in the embodiment shown in FIG.
Part of the output frequency is directly applied to the input terminal A of the frequency switching circuit 7, and the other part of the output frequency is applied to the fixed frequency divider 6 for frequency division, and then input to the input terminal B of the frequency switching circuit 7. Is being applied. Further, the frequency switching circuit 7 is provided with a terminal E, and is connected to the external terminal 10 via the terminal E.

The frequency switching circuit of the embodiment shown in FIG. 1 is constituted by a logic circuit as an example. 7a and 7b are 2-input AND gates, 7c is an inverter, and 7D is a 2-input OR gate. Since the pull-up voltage + V is applied to the terminal E, the AND gate 7b operates and the input terminal B operates in accordance with a known logical operation when the changeover switch 11 connected to the external terminal 10 is opened.
Output frequency of the fixed frequency divider 6 applied to the OR gate 7d
Is applied to the fixed frequency divider 8 from the output terminal D via the output terminal D, and a low-speed reception reproduction clock signal is obtained at the output of the fixed frequency divider 8 and output from the output terminal 9.

Also, when the changeover switch 11 is closed, the AND gate 7a operates,
The output frequency of the variable frequency divider 5 applied to the input terminal A is OR
It is applied to the fixed frequency divider 8 via the gate 7d, a high-speed reception reproduction clock signal is obtained at the output of the fixed frequency divider 8, and is output from the output terminal 9. FIG. 3 is a diagram showing the time relationship between two different clock signals obtained at the output terminal 9 when the dividing ratio of the fixed frequency divider 6 is halved. Indicates that it is possible to externally switch and obtain two types of received and reproduced clock signals of low speed and high speed that are in a doubling relationship. Further, the output frequency of the master clock generator is increased to near the upper limit of the operating range of a general-purpose digital element, and instead of the fixed frequency divider 6, a plurality of fixed frequency dividers having different frequency division ratios and corresponding It is also possible to obtain a plurality of low-speed to high-speed reception / reproduction clock signals by providing a frequency switching circuit and an external switch.

As the frequency switching circuit, other than the embodiment, a relay,
It can be selectively used according to the structure, scale, etc. of the device such as an analog switch.

(Effect of the Invention) As described in detail above, according to the present invention, the phase of the phase change signal extracted from the received data and the output frequency of the master clock generator are controlled by the variable frequency divider and the fixed frequency divider. In the digital phase-locked loop circuit that compares the phase of the received regenerated clock signal obtained by frequency division, detects and adjusts the phase difference to send and receive, and synchronizes the reception, the component provided after the variable frequency divider By switching a plurality of fixed frequency dividers with different division ratios from the outside, you can use general-purpose digital elements without changing the output frequency of the master clock generator. The effect of economically manufacturing and supplying general-purpose digital communication devices compatible with communication systems can be expected.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of an example of a conventional received clock signal regeneration circuit, and FIG.
The figure shows the time relationship when the frequency division ratio of the fixed frequency divider 6 in FIG. 1 ... Input terminal, 2 ... Phase comparison circuit, 3 ... Division ratio control circuit, 4 ... Master clock generator, 5 ... Variable divider, 6 ... Fixed divider, 7 ... Frequency Switching circuit, 8 ...
… Fixed frequency divider, 9 …… Output terminal, 10 …… External terminal, 11…
… Changeover switch.

Claims (1)

[Scope of utility model registration request] 1. A master clock generator, a variable frequency divider, a fixed frequency divider, a phase change signal extracted from received data, and an output frequency of the master clock generator fixed to the variable frequency divider. A phase comparison circuit that compares the phases of the received regenerated clock signals obtained by frequency division by a frequency divider, detects a phase difference, and outputs phase information, and after counting the phase information a certain number of times, according to the phase information A digital phase constituted by a frequency division ratio control circuit for increasing or decreasing the frequency division ratio of the variable frequency divider, counting a constant number of output frequencies of the variable frequency divider, and resetting the frequency division ratio to the original frequency division ratio. In a received clock signal regeneration circuit by a lock loop, a plurality of frequency dividers having different division ratios and frequencies for dividing the output frequency of the variable frequency divider between the variable frequency divider and the fixed frequency divider. Variable circuit provided with switching circuit The output frequency of the frequency divider and the output frequencies of the plurality of frequency dividers having different frequency division ratios are externally controlled by the frequency switching circuit, and a changeover switch for obtaining a plurality of different received reproduction clock signals is connected. A reception clock signal regenerating circuit with a clock signal switching circuit for a digital communication device, which is provided with an external terminal for.