RU1774497C - Automatic phase locking unit - Google Patents

Abstract

The invention relates to wired communications. The purpose of the invention is to increase the noise immunity of the device. To achieve the goal, four D-flip-flops 3-6, element НН 8, element И 10, Т-flip-flop 9, delay unit 12 are introduced. Using D-flip-flops 3, 4 and frequency divider 11, the presence and sign of mismatch are determined on the other - not divided clock frequency, relate to the leading edge of the pulses of the digital signal}. The absence of a mismatch corresponds to the falling edge of the input signal pulses falling between the trailing edge of the delayed and the rising edge of the uncontrolled clock voltage. In this case, the leading edge of the voltage of the delayed clock frequency is the gate of the pulses of the digital signal in the regenerator. The delay time is chosen so that the matching interval is wider than the maximum level of temporal fluctuations of the pulses of the input signal, but less than half the clock period. 3 ill. fe

Description

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The invention relates to wired communication and is intended for use in the equipment of linear paths of digital transmission systems (DSPs).

A device for automatically adjusting the frequency of a digital signal is known (US patent NS 3420956, class Н 04 L 7/00), comprising a time detector, an adder, a low-pass filter (LPF), a voltage-controlled oscillator (VCO), and a compensating signal shaper, and implementing a method of reducing temporary fluctuations of pulses by compensating for the high frequency components in the VCO control voltage spectrum.

The implementation of such a compensation method is possible only for temporary fluctuations that occur when the recording speed and reading of the digital signal in the temporal grouping equipment are matched, and does not compensate for the temporary fluctuations introduced into the signal by the transmission path.

Also known is a device for phase synchronization of a signal (ed. No. 1401630, class H 04 L 7/02), which contains blocks for isolating and delaying signal edges, a highly stable frequency generator, a switch, a converter, a mismatch register, an integrator, a VCO, a frequency divider and a clock counter.

The device is intended to solve the problem of phase synchronization of the clock frequency and the incoming signal by filling the mismatch interval with high frequency pulses and counting these 1 pulses.

The voltage of the clock frequency, phased with the frequency of the signal, can be used to regenerate phase fluctuating signal pulses. In this case, due to the presence of an integrator at the VCO input, a decrease in the level of high-frequency components of time fluctuations in the regenerated signal is achieved, however, low-frequency components of temporary jitter falling in the passband of the integrator remain unchanged.

As a prototype of the proposed device, the most similar in phase structure to the phase locked loop (PLL) (US patent No. 4596937, CL H 03 L 7/00, H 03 D 3/24) is selected, containing the input signal bus connected to the information input of the regenerator pulses, a high frequency generator and a frequency divider, and providing stepwise phasing of the divided (clock) frequency with a leading edge of the signal pulses recorded in the buffer memory unit. For phasing the signal and the clock frequency, the prototype uses a reset pulse generator connected to the installation inputs of the buffer memory unit, the frequency divider and the pulse regenerator.

The prototype device provides suppression of temporary fluctuations of pulses

0 in the regenerated signal only if the level of temporary fluctuations of the pulses in the input signal does not exceed half the period of the high frequency coming from the generator. At more

At a significant level of temporary fluctuations in the input pulses, a phasing failure occurs, leading to erroneous character regeneration.

The aim of the invention is to increase the noise immunity of the device.

To achieve this goal, a phase-locked loop containing a frequency divider, a pulse regenerator, an information input

5 of which is the input of the device and the high-frequency generator, four D-flip-flops, a delay unit, an And element and series-connected NO element and a T-trigger, the output of which is connected, are introduced

0 to the input of the frequency divider, the output of which is connected to the input of the delay unit and to the information input of the first D-trigger, the synchronizing input of which is connected to the synchronizing input of the second

5 D-flip-flop and with the information input of the pulse regenerator, the synchronizing input of which is connected to the output of the delay unit, with the information input of the second D-flip-flop and with the installation input

0 of the third D-flip-flop, the information and synchronizing inputs and the output of which are connected respectively to the output of the first O-flip-flop, with the inverse output of the high-frequency generator and with the inhibit

5 by the input of the NO element, the signal input and the inverse output of which are connected respectively to the direct output of the high-frequency generator and to the first input of the And element, the second input and output of which are connected respectively to the output of the fourth D-trigger, to the information input of which the output of the second D -trigger, and with the installation input of the T-trigger, which is connected to the installation input of the fourth D-trigger, to the synchronizing input of which the output of the T-trigger is connected, and with the installation input of the second D-trigger, q third D-flip-flop is connected to the mounting input of the first D-flip-flop.

The essence of the proposed invention is as follows.

1. Using the first and second D-flip-flops and a frequency divider connected directly and through a delay unit to the information inputs of the D-flip-flops, the presence and sign of the voltage mismatch of the divided clock frequency relative to the leading edge of the digital signal pulses are determined. The absence of a mismatch (both D-flip-flops are in zero state) corresponds to the falling edge of the input pulse in the interval between the trailing edge of the delayed and the rising edge of the uncontrolled clock voltage. In this case, the leading edge of the delayed clock frequency is gated the generation (regeneration in time) of the pulses of the digital signal in the regenerator.

The delay time t3 is chosen so that the matching interval (zero zone) A (T / 2 - G3) is wider than the maximum level of temporal fluctuations of the input signal pulses, but less than half the clock frequency period. From this, in particular, it follows that the proposed device provides the possibility of error-free pulse regeneration (i.e., restoration of the temporary positions of the pulses in the sequence) at the level of temporary fluctuations in the input signal N times (N is the frequency division coefficient) greater than in the device prototype. Therefore, the proposed device has a higher noise immunity to temporary fluctuations of the input signal in comparison with the prototype.

2. If there is a mismatch of type 10 (i.e., at levels 1 and 0 at the outputs of the first and second D-flip-flops, respectively) using the third D-flip-flop and the NO circuit, one period of high-frequency voltage oscillation taken from the generator output is prohibited high frequency (GHF). The forbidden period of the high frequency is that discrete interval by the amount of which, during the matching process, a time shift of the divided clock frequency is performed until it is phased with the signal. The same value determines the maximum possible level of displacement of the temporal position of the regenerated pulses. Therefore, in the proposed device is achieved N-fold decrease in temporary fluctuations of the regenerated pulses in

compared with the level of temporary fluctuations in the pulses of the input signal.

3. If there is a mismatch of type 01 (ie, at levels 0 and 1 at the outputs of the first and

the second D-flip-flops, respectively) by means of the fourth D-flip-flop, the element I and the T-flip-flop, a reset pulse is generated, which additionally switches the T-flip-flop, which

0 leads to a temporary shift of the divided clock frequency in the opposite direction.

Due to the possibility of determining the sign of mismatch and changing the direction of the time shift, an increase in the noise immunity of the proposed device to the effects of temporary fluctuations of the input signal is achieved, since an increase in their level and a change in sign

0 mismatch between the clock signal of the generator does not, unlike the prototype, disrupt the phasing, and only causes a shift in the moments of regeneration (and therefore the temporary position

5 of one of the regenerated pulses of the signal) for one period of high frequency. Thus, the introduction of new nodes and functional connections in the proposed device provides a significant increase in the noise immunity of the device to the effect of temporary fluctuations in the pulses of the input signal. No other known technical solutions with features similar to those distinguishing the claimed technical solution from the prototype were found during the search; therefore, the claimed technical solution has significant differences. In FIG. 1 shows the functional

0 diagram of the proposed device; in FIG. 2 and 3 are time diagrams explaining its operation.

In FIG. 1 is indicated: 1 - input signal bus; 2 - pulse regenerator; 3-6 5 D-flip-flops; 7 - high frequency generator; 8 - scheme NO; 9 - T-trigger; 10 - element And; 11 - frequency divider; 12 - Lok delay.

In FIG. 2 and 3 are indicated: T - period

0 high frequency; t is the current time; D is the matching interval.

The input signal bus 1 is connected to the information input of the pulse generator 2 and to the clock inputs

5 of two D-flip-flops Z and 4. The outputs of the D-flip-flops 3 and 4 are connected to the information inputs of the D-flip-flops. eras 5 and 6. The direct and inverse outputs of the high-frequency generator 7 are connected respectively to the signal input of the circuit NO 8 and to the synchronizing

the input of the D-flip-flop 5, the output of which is connected to the inhibitory input of the circuit NO 8 m installation input D-flip-flop Z. The direct and inverse outputs of the circuit NO 8 are connected respectively to the counting input of the T-flip-flops 9 and to the input of the element And 10, the other input of which connected to the output of the D-flip-flop 6. The output of the And 10 element is connected to the installation inputs of the D-flip-flops 4 and b and the T-flip-flop 9 whose output is connected to the input of the frequency divider 11 and to the synchronizing input of the D-flip-flop 6. The output of the frequency divider 11 connected to the information input of the D-trigger Z s with the input of the block for holder 12, the output of which is connected to the information input of the D-trigger 4, the installation input of the D-trigger 5 and with the clock input of the pulse generator 2, the output of which is the output of the device.

The device operates as follows,

The pulses of the input signal (Fig. 2a, Fig. 3a) with temporary fluctuations of the leading and trailing edges of the pulse (shaded areas in Figs. 2a and 3a) from bus 1 are fed to the information input of regenerator 2 and to the synchronizing inputs of two D-flip-flops Z and 4. The information of the first D-flip-flop 3 is supplied with the voltage of the divided clock frequency directly from the output of the frequency divider 11 (Fig. 26. 36). A delayed clock sequence (Fig. 2c, Sv} from the output of delay unit 12 is supplied to the information input of the second D-flip-flop 4, to the gate input of the regenerator 2 and to the installation input of the D-flip-flop 5.

In the further description of the operation of the device, it is necessary to take into account various cases of the mutual arrangement of the leading edge of the signal pulses and the voltage of the clock frequency:

1. Impact of the leading edge of the pulses, i.e. the shaded region of its possible positions, in the interval A between the trailing edge of the voltage of the delayed clock frequency and the leading edge of the voltage of the uncontrolled clock frequency, which corresponds to the absence of a mismatch of the signal and the clock frequency. In the absence of a mismatch in the pulse front of the signal, zeros are recorded in both D-flip-flops 3 and 4.

2. The shift to the right (delay) of the region of possible positions of the pulse front of the signal relative to the interval Д "which corresponds to the presence of a mismatch of type 10, i.e. by the edge of the signal pulse, one is recorded in the D-trigger 3, and zero is recorded in the D-trigger 4.

3, Left shift (leading) is the region of possible positions of the pulse front of the signal relative to interval A, which corresponds to the presence of a mismatch of the form 01, t, e. the front of the pulse in the D-flip-flop Z is written zero, and in the D-flip-flop 4 - one,

4. Hit the leading edge of the pulse in the interval between the leading edge of the delayed clock frequency and the trailing edge of the delayed clock frequency, which corresponds to the presence of a mismatch

type 11, i.e. the front of the pulse ensures the recording of units in both D-flip-flops Z and 4. The absence of a mismatch in FIG. 2 and 3 takes place if the leading edge of the signal pulse is in that part of the shaded area (Figs. 2a and 3a) that is aligned in time with interval A. However, there is no time shift of the divided clock frequency (Figs. 26 and 36) and therefore, the position does not change

the voltage front of the delayed clock frequency (Fig. 2B and Sv), performing the gating of the signal pulses in the regenerator 2, If there is a mismatch of type 10 (in Fig. 2, this corresponds to

the position of the leading edge of the pulse on the right side of the shaded area) by the leading edge of the pulse of the signal, 1 is written in the D-trigger 3 (Fig. 2d), and in the D-trigger 4-0. By the high-frequency voltage from the inverse output of the generator 7 (Fig. 2e), this unit is recorded in the D-flip-flop 5, at the output of which a pulse is generated (Fig. 2e), which, using the NO 8 circuit, prohibits one pulse in the high-frequency sequence (Fig. .2g), as well as resetting to the zero state of the D-flip-flop Z. From the direct output of the circuit NO 8, a sequence with a forbidden pulse (Fig. 2g) is supplied to the counting input of the T-flip-flop 9,

from the output of which a periodic sequence is removed (Fig. 2h) with a violation of the double pulse type (or its inverse sequence, depending on the initial state of the T-flip-flop 9).

This sequence is applied to the frequency divider 11, in which division is performed to the clock frequency. In FIG. 2c, for clarity, sequential division is shown with a small division coefficient (). Comparison of the phase of the clock frequency voltage in the presence (Fig. 2k) and the absence (Fig. 26) of a mismatch shows in which direction the clock frequency is shifted

relative to the signal at a mismatch of type 10.

The clock frequency voltage is supplied to the information input of the D-flip-flop 3 and to the input of the delay unit 12. The voltage of the delayed clock frequency (Fig. 2l) from the output of the delay unit 12 is supplied to the information input of the D-flip-flop 4, to the installation input D- trigger 5 and to the synchronizing input of the regenerator 2, with the help of which the restoration of the temporary positions of the signal pulses is provided (Fig. 2m).

The time shift of the clock frequency obtained in the process of matching (Fig. 2k) makes it possible to ensure that the entire shaded region of the possible positions of the leading edge of the signal pulses falls into the zero zone A, i.e. phasing of a signal and clock frequency. If there is a mismatch of type 01 (in Fig. 3, this corresponds to the position of the leading edge of the pulse (Fig. 3a) in the zero part of the shaded region that does not coincide with the interval A (Fig. 36c)), the leading edge of the pulse of the signal in D-trigger 3 is written zero, and in the D-trigger 4 - one (Fig. Zg). When the D-flip 3 and the D-flip 5 connected to it are at zero, there is no inhibit pulse at the inhibit input NO 8, and the high-frequency sequence (Fig. Zd) from the direct output of the high-frequency generator 7 goes to the counting input T without changes -trigger 9, forming at its output a periodic sequence (Fig. Ze). From the output of the T-flip-flop 9, this sequence is supplied to the frequency divider 11 and to the synchronizing input of the D-flip-flop 6, thereby ensuring recording in the D-flip-flop b of the unit (Fig. 3g) coming from the output of the D-flip-flop 4. A single state D-flip-flop 6 allows a pulse to pass through element I 10 (Fig. 3C) from the inverse high-frequency sequence, which is supplied simultaneously to the setup inputs of the T-flip-flop 9 and D-flip-flops 4 and 6, setting them to zero states. Resetting the T-trigger 9 (Fig. Ze) introduces a violation in the periodic sequence at its output, which is equivalent to the effect of an additional pulse on the counting input of the T-trigger 9 (unnecessary switching of the T-trigger 9). This violation leads, during the further process of frequency division in the divider 11, to a temporary voltage shift of the divided frequencies (Fig. Zi, k) by one period of high frequency oscillation.

The reset of the D-flip-flops 4 and 6 to the zero state (phi (. Zr, g) ensures the closure of the And element 10 and the end of the reset pulse (Fig. 3c).

Comparison of the phase of the clock voltage voltages in the presence (Fig. 3c) and absence (Fig. 36) of the mismatch shows in which direction the clock frequency is shifted relative to the signal during the mismatch of type 01.

The voltage of the clock frequency (Fig. ZK) is supplied to the information input of the D-flip-flop 3 and to the delay unit 12. The voltage of the delayed clock frequency (Fig. Zl) from the output of the delay unit 12 is supplied to the information input of the D-flip-flop 4, setting input D -triggers 5 and to the synchronizing input of the regenerator 2, which provides the regeneration of signal pulses (Fig. 3m).

The time shift of the clock frequency obtained as a result of coordination (Fig. 3c) allows, as before, to ensure that the entire shaded region of the possible positions of the leading edge of the signal pulses falls into the zero zone D.

The operation of the device is also reduced to the case considered in the presence of a mismatch of type 11 (i.e., when the front of the pulse records the signal of units in both D-flip-flops 3 and 4). Indeed, with a mismatch of type 11, as with a mismatch of type 01, in D -trigger 5 provides a zero state by applying a delayed clock voltage to its installation input from the output of delay unit 12. It should be noted that a mismatch of type 11 can appear almost only at the initial moment of switching on the signal and during further operation device does not occur.

Thus, the proposed device provides a significant increase in the noise immunity of the device to the effects of temporary fluctuations in the pulses of the input signal.

Claims (1)

SUMMARY OF THE INVENTION A phase locked loop device comprising a frequency divider, a pulse regenerator, the information input of which is the input of the device, and a high frequency generator, characterized in that, in order to increase the noise immunity, four D-flip-flops, a delay unit, an element And - subsequently connected element NO and T-trigger, the output of which is connected to the input of the frequency divider, the output of which is connected to the input of the delay unit and to the information input of the first D-trigger, the synchronizing input is connected to the synchronizing input of the second O-trigger and to the information input of the pulse generator, the synchronizing input of which is connected to the output of the delay unit, to the information input of the second D-trigger and to the installation input of the third O-trigger, the information and synchronizing inputs and output of which connected respectively to the output of the first D-flip-flop, with the inverse output of the high-frequency generator and with the inhibiting input of the NO element, the signal input and whose inverse output is connected respectively to the direct output of the high-frequency generator and to the first input of the And element, the second input and output of which are connected respectively to the output of the fourth D-trigger, to the information input of which the output of the second D-trigger is connected, and with the installation input T- trigger, which is connected to the installation input of the fourth D-trigger, to the synchronizing input of which the output of the T-trigger is connected, and to the installation input of the second D-trigger, while the output of the third D-trigger is connected to the installation full-time entrance of the first D-flip-flop. FIG. 2 FIG. 5