JPH1131364A - Recording and reproduction control method and recording and reproducing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speeding-up the operation of a read circuit and to make the circuit highly integrable by allowing a data synchronizer to generate a read clock by referring to the clock of a frequency in which the frequency of a write clock is shifted by a prescribed value in a reading data to prevent the margin of the rear circuit from being lowered. SOLUTION: At first, a capture range Δf' being a range within which a data synchronizer 3 is synchronizable with data even when the oscillation frequency of a write synthesizer 5 and the oscillation frequency of the data synchrinizer 3 are deviated when the data synchronizer 3 becomes to be in a read mode is measured by changing the frequency of the write synthesizer 5. During the read mode, the frequency of the synchronizer is set to a frequency lower than the capture range Δf' by changing the frequency dividing ratios of frequency dividers 52, 53 with a frequency changeover signal (d). Thus, the read circuit whose reliability is high and whose size is small and whose operating speed is high is obtained without lowering the margin at the time of the read mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data recording / reproducing control method and a recording / reproducing circuit for an information recording medium, and more particularly to a data synchronizer and a write synthesizer for a recording / reproducing circuit of a hard disk drive.

[0002]

2. Description of the Related Art One embodiment of a conventional recording / reproducing circuit will be described with reference to FIG.

This recording / reproducing circuit is a disk enclosure (hereinafter referred to as DE) comprising a magnetic disk medium and a head.
1) a peak pulse demodulation circuit 2 for demodulating a peak pulse a from an output waveform o, a data synchronizer 3 for generating a read clock b, and a decoder 4 for inputting the peak pulse a and the read clock b and outputting read data p. , A write synthesizer 5 for generating a write clock c, and a write clock c
And an encoder 6 that generates write data q in synchronization with the data DE and outputs the write data q to the DE 1.

The data recording operation is as follows. The interface write data r input to the encoder 6 is converted into the write data q synchronized with the write clock c, and the data DE1 is written.
And written on the medium. The write clock c output from the write synthesizer 5 is generally generated in synchronization with the servo information written on the medium, or in synchronization with the clock generated by the crystal oscillator, and by a multiple thereof. It is generated as a clock converted to that frequency.

At the time of data reproduction, the read waveform o read from the DE 1 is demodulated by the peak pulse demodulation circuit 2 to become a peak pulse a, which is input to the data synchronizer 3 and the decoder 4. The peak pulse a input to the decoder 4 is decoded by the read clock b input from the data synchronizer 3 and output to the interface as read data p. The data synchronizer 3 that generates the read clock b is synchronized in advance with the write clock c output from the write synthesizer 5 during the idle mode, but when the read mode is entered, the input is quickly switched to the peak pulse a, A read clock b synchronized with the pulse a is output.

[0006]

However, in the conventional recording / reproducing circuit, the oscillation frequency of the data synchronizer for generating the read clock and the write synthesizer for generating the write clock are the same as described above, With the integration, the data synchronizer and the write synthesizer are placed close to each other on the same chip, so that the two oscillators interfere with each other, and the other clock is synchronized with the noise generated on one side, or the oscillation frequency is shifted. Thus, there has been a problem that jitter occurs in the write and read clocks, and the margin of the read circuit is reduced.

Here, FIG. 5 shows that the margin of the read system, that is, the read clock b of the output of the data synchronizer 3 and the read data o of the peak pulse demodulation circuit.
The relationship with the peak pulse a demodulated from the above will be described.

In FIG. 5, the horizontal axis represents time, and the vertical axis represents the frequency of a clock or pulse generated at each time. The read clock b has exactly the same distributions 28a and 28 with a time width t3 at both ends thereof at intervals of a period T.
b, and the peak pulse a is equal to 2 of the read clock b.
A distribution 27 having a width t4 generated by a shift on the time axis such as a peak shift of a read signal written on the medium is formed at approximately the center of the two distributions 28a and 28b. If the width t4 of the peak pulse a is shorter than the period T, the remaining time, that is, the readout system margin tm is expressed by the following equation.

Tm = T−t4−t3 = t1 + t2. . . . (1) Here, when jitter occurs in the clocks of the write system and the read system, the distribution t3 of the data window 28 increases to t3 ', and the margin of the read system decreases to tm'.

An object of the present invention is to solve the above-mentioned problems,
Prevents a decrease in the margin of the read circuit and speeds up the circuit.
An object of the present invention is to provide a recording / reproducing control method and a recording / reproducing circuit which can be highly integrated.

[0011]

According to the recording / reproducing control method of the present invention, a clock having a frequency obtained by shifting the frequency of a write clock by a predetermined value to a data synchronizer at the time of data reading is input, and the data synchronizer shifts the frequency. A read clock is generated with reference to the clock of the input frequency.

The value of the frequency to be shifted from the clock at the time of writing is a frequency to which the peak pulse generated from the information on the read information recording medium can be synchronized even if the oscillation frequency of the data synchronizer deviates from the frequency of the write clock. It is desirable to be within the range, that is, within the capture range.

The recording / reproducing control circuit according to the present invention comprises: a means for generating a second write clock in which the frequency of the generated write clock is shifted by a predetermined value to the write synthesizer; Clock switching means for outputting the second write clock to the data synchronizer.

Further, the write synthesizer includes an oscillator having a stable oscillation frequency, and an oscillator having an oscillation frequency of 1 /
First frequency dividing means for dividing and outputting one of N and 1 / N 'and a write clock to be outputted and dividing the frequency to one of 1 / M and 1 / M' A phase-locked loop including a second frequency dividing means for inputting an output of the first frequency dividing means and outputting a write clock; and a dividing ratio of 1 / N and 1 for the first and second frequency dividing means. / M combination or 1
It is desirable to have clock switching means for switching to any of the combinations of / N 'and 1 / M'.

[0015]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a system configuration of an embodiment of a recording / reproducing circuit according to the present invention, FIG. 2 is a diagram showing a clock frequency in a read / write mode, and FIG. It is a figure which shows the relationship of quantity.

In FIG. 1, a recording / reproducing circuit 1 according to this embodiment is shown.
0 denotes a peak pulse demodulation circuit 2 for demodulating a peak pulse a from the output waveform o of the DE 1, a data synchronizer 3 for generating a read clock b, and a decoder 4 for inputting the peak pulse a and the read clock b and outputting read data p. , A write synthesizer 5 for generating a write clock c, and a write clock c
And an encoder 6 that generates write data q in synchronization with the data DE and outputs the write data q to the DE 1.

The data synchronizer 3 has a changeover switch 31 for switching the input j to the phase comparator 32 to either the peak pulse a or the write clock c output from the write synthesizer 5 according to the signal n from the read gate. The phase comparator 32 outputs a phase error signal k having a width corresponding to the phase difference by comparing the phase of the output j of the changeover switch 31 with the phase of the read clock m, and converts the phase error signal k into a current and outputs the current. A charge pump (B) 33,
A filter (B) 35 that cuts a high-frequency signal and converts the current output of the charge pump (B) 33 into a control voltage l;
A voltage controlled oscillator (hereinafter referred to as VCO) that outputs a read clock b whose frequency is determined according to the control voltage l
(B) 34 and a frequency divider (C) 36 that divides the read clock b output from the VCO (B) 34 by 1 / M and outputs a read clock m.

The light synthesizer 5 includes a crystal oscillator 51
And frequency divider (A) 52, frequency divider (B) 53, phase / frequency comparator 54, charge pump (A) 55, VCO
(A) 56 and a phase locked loop (PLL) composed of a filter (A) 57.

The write synthesizer 5 includes a crystal oscillator 51 having a stable oscillation frequency, a frequency divider (A) 52 for dividing a clock e output from the crystal oscillator 51 by 1 / N and outputting a clock f, and a VCO (A) A frequency divider (B) 53 that divides the write clock c output from 56 by 1 / M and outputs a clock i, two frequency dividers (A) 52, and a frequency divider (B)
A phase / frequency comparator 54 that compares the phase and frequency of the clock f and the clock i output from 53 and outputs a phase / frequency error signal g of a pulse having a width corresponding to the phase difference and the frequency difference; Charge pump (A) 55 that converts phase / frequency error signal g, which is a pulse, into current
And the high-frequency signal of the current output from the charge pump (A) 55 is cut, and the control voltage h of the VCO (A) 56 is cut off.
And a voltage controlled oscillator (A) 56 that outputs a read clock c having a frequency corresponding to the control voltage h.

Here, the frequency divider (A) 52 and the frequency divider (B)
The frequency division ratio N and M of 53 are set by a frequency switching signal d from outside the circuit, and the oscillation frequency of the VCO (A) 56 is M / N times the oscillation frequency of the crystal oscillator 51.

Next, the operation of the recording / reproducing circuit of this embodiment will be described with reference to FIGS.

First, by changing the frequency of the write synthesizer 5, the data synchronizer 3 is synchronized with the data even if the oscillation frequency of the write synthesizer 5 and the oscillation frequency of the data synchronizer 3 are shifted when the data synchronizer 3 enters the read mode. A possible range, the capture range (Δf ′) is measured.

FIG. 2 shows the relationship between the channel mode and the oscillation frequency of the write synthesizer 5.

When the channel is in the idle mode, that is, when the device is neither writing nor reading, the oscillation frequency of the write synthesizer 5 is set to M / N times the oscillation frequency of the crystal oscillator 51.

When writing data, the oscillation frequency of the write synthesizer 5 is set to be the same as in the idle mode. Therefore, the crystal oscillator 5 is provided on the medium.
Data is written in synchronization with a clock that is M / N times the oscillation frequency of 1.

The frequency at which data is read is determined by changing the frequency division ratios N and M of the frequency divider (A) 52 and the frequency divider (B) 53 according to the frequency switching signal d.
M ′ is a frequency shifted from the frequency in the idle mode by Δf smaller than the capture range (Δf ′), that is, M ′ / the oscillation frequency of the crystal oscillator 51.
Set to N 'times. Thus, the oscillation frequency of the write synthesizer 5 is shifted by Δf between the time of writing data and the time of reading data.

As a result, it is possible to prevent the distribution t3 of the data window 28 in FIG. 5 from becoming t3 'and consequently the read margin tm' from becoming tm '= T-t4-t3'≤tm. .

FIG. 3 shows the frequency of the write clock c of the write synthesizer 5 on the horizontal axis and the jitter of the write clock cycle T at that time on the vertical axis. The jitter amount is shifted by Δf from the center frequency. It can be seen that it is reduced.

[0030]

As described above, according to the present invention, the frequency of the write clock input from the write synthesizer to the data synchronizer is shifted from the frequency at the time of data read at the time of data read to thereby improve the read clock output from the data synchronizer. Jitter can be reduced, and there is an effect that a small, high-speed device with high reliability can be provided without reducing a margin at the time of data reading.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a system configuration of an embodiment of a recording / reproducing circuit according to the present invention.

FIG. 2 is a diagram showing a clock frequency in a read / write mode.

FIG. 3 is a diagram illustrating a relationship between a write clock frequency and a jitter amount of a period T.

FIG. 4 is a block diagram showing a system configuration of one embodiment of a conventional recording / reproducing circuit.

FIG. 5 is an explanatory diagram of a read margin.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Disk enclosure, DE 2 Peak pulse demodulation circuit 3 Data synchronizer 4 Decoder 5 Write synthesizer 6 Encoder 10 Recording / reproduction circuit 31 Changeover switch 32 Phase comparator 33, 55 Charge pump 34, 56 Voltage control oscillator, VCO 35, 57 Filter 36 , 52, 53 divider 51 crystal oscillator 54 phase frequency comparator

Claims (5)

[Claims] 1. An information recording apparatus comprising: a write synthesizer for generating a write clock for writing information on an information recording medium; and a data synchronizer for generating a read clock for reading information from the information recording medium with reference to the write clock. In a recording / reproducing control method for writing information to a medium and reading information from the information recording medium, a clock having a frequency obtained by shifting the frequency of the write clock by a predetermined value to the data synchronizer is input to the data synchronizer. A read / write control method, wherein a read clock is generated with reference to a clock having a shifted frequency. 2. A value of a frequency shifted from the write clock is a peak range generated from information on an information recording medium read even when an oscillation frequency of a data synchronizer deviates from a frequency of the write clock, also referred to as a capture range. 2. The recording / reproducing control method according to claim 1, wherein the value is within a range of a synchronizable frequency. 3. A write synthesizer for generating a write clock for writing information to an information recording medium, an encoder for outputting data of input write information in synchronization with the write clock, and information read from the information recording medium. A peak pulse demodulation circuit for generating a peak pulse from the data of the data, a data synchronizer for generating a read clock for reading information from an information recording medium with reference to the peak pulse and the write clock, and A recording / reproducing circuit including a decoder for outputting in synchronization with a read clock; wherein the write synthesizer generates a second write clock in which the frequency of the generated write clock is shifted by a predetermined value; and an information recording medium. When reading information from the second Reproducing circuit; and a clock switching means for outputting a byte clock. 4. A write synthesizer comprising: an oscillator having a stable oscillating frequency; and a first oscillator which divides the oscillating frequency of the oscillator to 1 / N or 1 / N ′ and outputs the frequency.
, A phase-locked loop for inputting an output of the first frequency-dividing means to generate and output a write clock, and inputting a write clock output from the phase-locked loop and setting the frequency to 1 Second frequency dividing means for dividing the frequency into one of / M and 1 / M 'and inputting the divided frequency to the phase locked loop;
Clock switching means for switching the frequency division ratio of the first and second frequency dividing means to a combination of 1 / N and 1 / M at the time of writing and to a combination of 1 / N 'and 1 / M' at the time of reading. Item 4. The recording / reproducing circuit according to Item 3. 5. The difference between the value of the frequency division ratio M / N and M ′ / N ′ is generated from the information on the information recording medium read out even if the oscillation frequency of the data synchronizer deviates from the frequency of the write clock. 5. The recording / reproducing circuit according to claim 3, wherein the peak pulse has a value within a frequency range that can be synchronized.