JPH0440671A - Pll device - Google Patents

Abstract

PURPOSE:To execute recording having no error in a recording format and digital reproduction preventing the generation of jitter by fixing the output of a DIN control circuit constituted of a NAND gate even in the case of asynchronous PLL and suppressing the variation of VCO frequency. CONSTITUTION:At the time of inputting a digital signal, a PLL low pass filter is asynchronized, the output of the DIN control circuit 16 is fixed at a high or low level, the frequency control voltage of a VCO voltage control oscillator 1 is held, and a system controller 3 switches the mode of the circuit 16. When a reference clock is switched to a crystal oscillator, the output of the circuit 16 goes DIN digital input data, and the PLL is synchronized, the circuit is switched to the digital input mode again. Thereby, even if the PLL is asynchronized, the frequency variation of the reference clock is removed, so that recording having no error in a recording format is attained and jitter is removed from digital reproduced data obtained by demodulating the digital input signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an R-DAT capable of recording digital input signals.
PL that is effective for use in digital recording or playback devices such as digital amplifiers that can play back digital input signals.
This relates to the L device.

Conventional technology FIG. 3 shows a configuration diagram of a PLL for digital input of R-DAT using this conventional PLL device, in which 1 is a VCo whose output signal is the reference clock at the time of DIN input;
6 is a phase comparator that uses the output signals of DIN and VCOL as input signals and the error signal as an output signal; 2 is a phase comparator that uses the output signals of DIN and VCOL as an output signal;
7 is a PLL synchronization detection circuit which uses the output signal of the phase comparator 6 as an input signal and the synchronization detection signal of the PLL as an output signal; 7 is an LPF which uses the output signal of the phase comparator 6 as an input signal and uses the frequency control voltage of the VCOL as an output signal; PLL, a system controller including a function of using the output signal of the synchronization detection circuit as an input signal and a system control signal as an output signal; 8 is a crystal oscillator; 9 is an output signal of the crystal oscillator 8;
A selector 10 selects and outputs one human-powered signal from the two human-powered signals of the output signals of the COI, and a selector 10 uses DIN, the output signal of the selector 9, and the output signal of the system controller 14 as input signals, and the selection signal of the selector 9 and the digital signal. This is a DAT signal processing block whose output signals are a recording signal and a source monitor signal. 15 is an AD converter that converts an analog input signal into a digital signal and supplies it to the DAT signal processing block 10.

The operation of the conventional PLL device configured as described above will be described below. When recording a digital input signal, a phase comparator 6 compares the phases of DIN and a clock signal obtained by dividing the output signal of the VCOI, and the error voltage is converted to L.
After the high frequency is removed and integrated by PF7, it is returned to an error voltage, and the error voltage controls the oscillation frequency of the VCOL, and the PLL is synchronized. When PLL synchronization is detected by the PLL synchronization detection circuit 2 using the VCOL output signal and DIN as input signals, the system controller 14 changes the processing mode of the DAT signal processing block 10 from analog input signal recording to digital input signal recording. By switching to , the DAT signal processing block 10 controls the selector 9 to select the output signal of the VCOL as the reference clock and start recording. Conversely, if the DIN sampling frequency changes and the PLL goes out of synchronization, the system controller 14 switches the processing mode of the DAT signal processing block 10 from digital recording to analog recording. , controls the selector 9 to select the output signal of the crystal oscillator 8 as a reference clock and starts recording.

Problems to be Solved by the Invention However, in the above configuration, the DAT signal processing block 10 does not perform the DAT signal processing block 10 when in the digital input signal recording mode.
Due to changes in the IN sampling frequency, etc., the PLL
After the synchronization is lost until the DAT signal processing block 10 switches to the analog input signal recording mode,
Since the output clock of the VCOl which is out of synchronization is input as the reference clock of the DAT signal processing block 10,
The frequency of the reference clock fluctuates. Therefore, P.L.
After the synchronization of L is lost, the DAT signal processing block 10
The problem is that a signal different from the DA pre-recording format is recorded for several frames until the DIN switches to the analog input signal recording mode, and the jitter of the recording monitor signal demodulated from DIN becomes large. was.

In view of this point, the present invention provides that even if the PLL is out of synchronization due to a change in the DIN sampling frequency, the VC
By fixing the frequency of the O output clock to the frequency at the moment when synchronization is lost, it is possible to record without errors in the pre-DA recording format, and it is possible to eliminate jitter in the source monitor signal demodulated from DIN. The purpose is to provide a PLL device.

Means for Solving the Problems In order to achieve the above object, the PLL device of the present invention has V
a system controller that receives a PLL synchronization detection signal indicating whether the co and the PLL are synchronized or out of synchronization and outputs a DIN control signal; a system controller that receives the PLL synchronization detection signal, the DIN control signal, and the DIN as input;
When the PLL synchronization detection signal indicates PLL synchronization, the DIN is output as an output signal, and when the PLL is out of synchronization, a signal fixed at either high level or low level is output, and then the system a DIN control circuit that outputs the DIN as an output signal by receiving a DIN control signal that is an output signal of a controller;
a phase comparator that receives the output signal of the DIN control circuit and the reference clock of the VCO and outputs a phase comparison signal of the PLL; P with a low-pass filter that outputs 1. It is an L device.

Effects The present invention has the following effects due to the above-described configuration.

With the above-described configuration, the PLL device of the present invention allows the PLL to become out of synchronization when a digital signal is input, and at the same time
When the output of the control circuit is fixed at high level or low level and the VCO frequency control voltage is held, the system controller switches the mode of the DIN control circuit and the reference clock is switched to crystal oscillation. When the output becomes DIN and the PLL is synchronized, the DIN control circuit switches to digital input mode again.

Therefore, even if the PLL is out of synchronization, the frequency fluctuation of the reference clock can be eliminated, and the recording format can be recorded without errors and the jitter of the digital reproduction data obtained by demodulating the digital input signal can be eliminated.

Embodiment FIG. 1 shows a configuration diagram of a PLL for digital input of an R-DAT using a PLL device according to a first embodiment of the present invention.

1 is a VC whose output signal is the reference clock when DIN is input.
O12 is a PLL synchronization detection circuit that detects PLL synchronization;
3 is the system controller of R-DAT, and 4 is the PLL synchronization detection signal output from the PLL synchronization detection circuit 2 and the first control signal (DIN control signal) of the system controller 3.
2-person NAND gate with input, 5 is DIN and NA
It is a two-man powered NAND gate that takes the output of ND gate 4 as input, and the D
An IN control circuit 15 is configured. 6 is an edge detection type phase comparator which uses the output signal of the NAND gate 5 and the clock output of the VCO 1 as input signals and an error signal as an output signal; 7 uses the output signal of the phase comparator 6 as an input signal;
LPF outputs the frequency control voltage of COl, 8 is a crystal oscillator, 9 is an output clock signal of the crystal oscillator 8 and VCO 1
A selector 10 selects and outputs one human power signal from two human power signals of the output signals of the selector 9; This is a DAT signal processing block whose output signals are a selection signal, a recording signal which is a digital signal, and a source monitor signal. 15 is an AD converter that converts an analog input signal into a digital signal and supplies it to the DAT signal processing block 10. The operation of the PLL device of this embodiment configured as described above will be explained below. When the DAT signal processing block 10 is in the digital input signal recording mode, if the PLL synchronization detection circuit 2 detects a PLL out of synchronization due to a change in the DIN sampling frequency, the PLL
Since the synchronization detection signal changes from low level to high level and the first control signal is at high level, AND gate 4
The output of NAND gate 5 becomes low level, and the output of NAND gate 5 is fixed at high level.

When the output of the NAND gate 5 is fixed at a high level, the level of the input signal of the phase comparator 6 does not change, so the output of the phase comparator 6 becomes high impedance, and the LPF
Since the output voltage (frequency control voltage) of 7 is held at the potential at the moment when the PLL synchronization is lost because there is no change in the input signal, VCO1 sets the output clock frequency to the frequency at the moment the PLL synchronization is lost. Fix it. At the same time, the system controller 3 switches the mode of the DAT signal processing block 10 to analog input signal recording, and when the mode is switched and the DAT signal processing block 10 controls the selector 9 to change the reference clock from the VCOL output to the crystal oscillator output. , the system controller 3 sets the first control signal to a low level when the output of the NAND gate 4 becomes high level and sets the output of the NAND gate 5 to DIN, and when the PLL is synchronized, the system controller 3 again sets the mode of the DAT signal processing block 10 to the second mode. Set the digital input signal recording mode by the control signal. Therefore, the DAT signal processing block 1° uses the reference clock as the output clock of the VCOL, demodulates the DIN, and outputs the recording signal and the source monitor signal. As described above, according to this embodiment, at the time of digital input, the PLL
At the same time as the synchronization of the DAT signal processing block 10 is lost,
until the reference clock of N is switched to the crystal oscillator 8.
The output of AND gate 5 is fixed at high level, and the VCO
By holding the frequency control voltage that is input to L, VC
By fixing the frequency of the OL to the frequency before the synchronization of the PLL is lost, even if the synchronization of the PLL is lost, recording without error in the DAT recording format and jitter of the source monitor signal can be eliminated.

FIG. 2 shows a configuration diagram of a PLL for digital input of an R-DAT using a PLL device according to a second embodiment of the present invention.

1 is a VC whose output signal is the reference clock when DIN is input.
O12 is a PLL synchronization detection circuit that detects PLL synchronization;
3 is the R-DAT system controller, 12 is the PLL
A delay circuit delays the PLL synchronization detection signal output from the synchronization detection circuit 2 for a certain period of time; 13 is an inverter gate that inverts and outputs the output signal of the delay circuit 12;
V, 4 is a two-man NA that inputs the PLL synchronization detection signal which is the output of the PLL synchronization detection circuit 2 and the output signal of INV13.
NAND gate 1.5, which is an ND gate, has DIN and NA
This is a two-man powered NAND gate that receives the output of the ND gate 4 as an input. 6 is an edge detection type phase comparator that uses the output signal of the NAND gate 5 and the output of the VCO1 as input signals and an error signal as the output signal; 7 uses the output signal of the phase comparator 6 as an input signal and uses the frequency control voltage of the VCOI. 8 is a crystal oscillator, 9 is a selector that selects and outputs one human-powered signal from two human-powered signals: the output clock signal of the crystal oscillator 8 and the output signal of the VCOI, and 10 is the output signal of the NAND gate 5. This is a DAT signal processing block whose input signals are the output signal of the selector 9 and the third control signal of the system controller 3, and whose output signals are the selection signal of the selector 9, a recording signal which is a digital signal, and a source monitor signal. 15 is an AD converter that converts an analog input signal into a digital signal and supplies it to the DAT signal processing block 10.

The operation of the PLL device configured as above will be described below. Regarding the contents of the operation, the blocks having the same functions as those in the embodiment shown in FIG. 1 are given the same numbers and the explanation thereof will be omitted, and the differences will be explained. As soon as the DIN PLL gets out of synchronization during digital input,
The PLL synchronization detection signal changes from low level to high level, and NAND gate 5 is fixed at high level. At the same time, the system controller 11 switches the DAT signal processing block 10 to analog input recording mode. NAN
Since the D gate 4 is at a low level for the delay time of the delay circuit 12 and the NAND gate 5 is fixed at a high level, the frequency of the VCO 1 is maintained at the frequency at the moment when the PLL is out of synchronization during the delay time. be done. When the delay time has passed, DIN is output to the NAND gate 5 and P
When LL is synchronized, the system controller 11 again switches to D.
The AT signal processing block 10 is switched to digital input signal recording mode. Note that the delay time is longer than the time from when the system controller 11 sets the processing mode of the DAT signal processing block 10 to analog input recording rather than digital input recording until the processing mode of the DAT signal processing block 10 changes to analog input recording. Set to time.

As described above, according to this embodiment, even if the PLL is out of synchronization at the time of digital input, as in the embodiment of FIG.
It is possible to record without errors in the recording format and eliminate jitter in the source monitor signal. Note that in the above embodiment, in the synchronized state of the PLL, the NAND gate 5
N is inverted and output to the phase comparator 6, but the phase comparator 6 is configured with an AND gate without changing the polarity of DIN.
Needless to say, it is okay to output to .

As described in detail, according to the configuration of the present invention, when a reference clock for recording and reproducing a digital input signal is generated by a PLL using a VCO, even if the PLL is out of synchronization, the NAND gate 4 The output of the DIN control circuit 16 consisting of the NAND gate 5 is fixed at a high level, and V
By preventing the frequency of the CO from changing, it is possible to perform recording without errors in the recording format and digital reproduction without any chics.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a PLL for digital input of R-DAT using a PLL device in one embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a PLL in a second embodiment of the present invention.
FIG. 3 is a block diagram showing the configuration of a PLL for digital input of an R-DAT using a conventional PLL device. 1...VCO12...PLL synchronization detection circuit, 3.11.14...System controller, 4...NAND gate, 5... N
AND gate, 6... Phase comparator, 7...
...LPF, 10...DAT signal processing block, 12...Delay circuit, 16...DIN
control circuit.

Claims (1)

[Claims] A PLL device that receives digital input data (hereinafter abbreviated as DIN), and a voltage controlled oscillator (hereinafter abbreviated as VCO) that outputs a reference clock, and PLL synchronization that indicates whether the PLL is synchronized or out of synchronization. a system controller that receives a detection signal as an input and outputs a DIN control signal; and a DIN that receives the PLL detection signal and the DIN control signal and outputs the DIN as an output signal.
a control circuit; a phase comparator which receives the reference clock of the VCO and the output signal of the DIN control circuit and outputs a PLL phase comparison signal; and a phase comparator which receives the phase comparison signal and removes high frequency components; The DIN control circuit includes a low-pass filter (hereinafter abbreviated as LPF) that outputs a frequency control voltage that is input to the DIN control circuit. A PLL device, characterized in that when the synchronization of the PLL is lost, the PLL device outputs a signal fixed at either a high level or a low level for a certain period of time, and then outputs the DIN as an output signal.