JPH0832071B2 - Video signal chroma phase correction method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video device such as a VTR or a video disc, which detects and corrects discontinuity of a chroma signal component included in a reproduced video signal to obtain a high quality video. The present invention relates to a chroma phase correction method of a video signal for obtaining a signal.

2. Description of the Related Art In a magnetic recording / reproducing apparatus such as a VTR or an image reproducing apparatus such as a video disk, a reproduced video signal is generated due to a center of gravity or deviation of a rotary recording medium such as a disk or rotation unevenness of a motor for driving the same. A discontinuity occurs in the chroma signal component of.

Further, in VTRs, video discs, etc., it is necessary to pay attention to the continuity of the chroma phase of the video signal when performing special speed reproduction or still reproduction using a field memory or the like. This will be described with reference to FIG. 3 by taking the case of NTSC as an example.

FIG. 3 shows the phase relationship of the chroma of the NTSC system video signal, and has a 4-field sequence configuration in which the chroma phase makes one round in 4 fields. In the figure, waveforms 1 to 3 show the phase relationship of the chroma at each time point with the start position of the first field and the first line as a reference. Considering that double-speed reproduction is performed by thinning out fields using a 1-field memory, for example, in the 4-field sequence shown in the figure, for example, the video signal of the third field is reproduced after the first field. become. That is, considering the continuity of the horizontal synchronizing signal, the signal at the point in FIG. 9C is reproduced after the point in FIG.
Eventually, the phase of the chroma will be inverted as shown by the waveforms in the figure. Similar inconvenience also occurs in slow playback and the like. Such a discontinuity in the phase of chroma has a great influence on the hue of the reproduction screen, and there is a problem that a color different from the original hue is reproduced.

As a method for correcting this discontinuity of the chroma phase (for example, Japanese Patent Laid-Open No. 61-171295), a memory as shown in FIGS. 4 and 5 is used.
The chroma phase correction method of the APC method has been conventionally known.

In FIG. 4, 10 is an input terminal for a video signal having a discontinuity in chroma phase, and 20 is an output terminal for a video signal with a corrected chroma phase. In addition, 1 is an A / D conversion circuit (A / D) that converts an analog input video signal into a digital signal, and 2 is
A memory composed of RAM and the like. Reference numeral 4 denotes a burst separation circuit, and the color burst signal having discontinuity extracted from the burst separation circuit is input to a write clock generation circuit (W.clk) 50.

The write clock generation circuit 50 generates a write clock synchronized with the chroma phase of the input video signal from the terminal 10 in synchronization with the color burst signal. Input terminal 30
Is an input terminal of a burst gate control signal necessary for generating this write clock. Further, the write address control circuit 60 outputs a write address according to the write clock.

Therefore, the analog video signal having the discontinuity of the chroma phase input from the terminal 10 is synchronized with the write clock output from the write clock generation circuit 50.
It is converted into a digital signal by the A / D conversion circuit 1 and written in the memory 2 according to the address of the write address control circuit 60.

On the other hand, a stable reference signal (for example, a horizontal synchronization signal) with no time axis fluctuation is input from the terminal 40, and a read clock generation circuit (R.clk) 80 generates a read clock synchronized with the reference signal. It The read address control circuit (R.add) 70 generates a read address in synchronization with the read clock and controls the read address of the memory 2.

Therefore, the data of the video signal stored in the memory 2 is sequentially read in synchronization with the reference signal, and the D / A conversion circuit (D / A) 3 synchronizes with the read clock to generate an analog signal. Is converted to.

Therefore, if the write clock is synchronized with the chroma phase of the input video signal, it will be stored in the memory 2 as a video signal with continuous chroma phase.
From the output terminal 20, a continuous video signal with a chroma phase is obtained.

As is clear from the above description of the operation, the performance of this chroma phase correction method depends on the method of generating the write clock, and how to generate the write clock that accurately follows the chroma phase of the input video signal. Is important.

Regarding the configuration of the write clock generation circuit 50,
A method is known in which a so-called APC circuit shown in FIG. 5 is used. The configuration of the write clock generation circuit 50 of FIG. 4 will be described below with reference to FIG.

In FIG. 5, the color burst signal from the burst separation circuit 4 of FIG.
Is input to one side. 56 is a voltage controlled oscillator (VCO),
The center frequency is set to the same frequency as the frequency of the read clock in FIG. The output of the voltage controlled oscillator 56 shown in FIG. 5 is divided by the frequency divider 57 to have the same frequency as the color burst signal of the input video signal and the phase comparator 53.
Is input to The phase comparator 53 outputs a signal corresponding to the phase difference between the two authors and sends it to the burst gate circuit 54.
On the other hand, the input terminal 30 is the same as the input terminal 30 in FIG. 4, and a burst gate control signal capable of identifying only the color burst portion of the input video signal is input. Therefore, in the burst gate circuit 54, the phase difference signal of the phase comparator 53 is gated and output only during the period when the color burst exists in the input video signal, and fixed at a specific potential during the period when the color burst does not exist. And output. That is, the phase comparison between the color burst signal separated from the input video signal and the signal obtained by dividing the oscillation frequency of the voltage controlled oscillator (VCO) 56 is performed only during the period when the color burst exists in the input video signal. . Thereafter, the output of the burst gate circuit 54 is sent to a low pass filter (LPF) 55, where it is converted into a voltage level according to the phase difference and becomes a control voltage of a voltage controlled oscillator (VCO) 56.

With the above configuration, the APC circuit is configured, and by the negative feedback control action of the APC circuit, the output that follows the fluctuation of the color burst signal included in the input video signal is the voltage controlled oscillator (VC
O) 56, and this output is output from the terminal 52 as a write clock.

Problems to be Solved by the Invention This conventional method is based on negative feedback control. Therefore, in the case where the phase of the chroma is suddenly inverted as described above.
There is a problem that the tracking error of the APC system occurs and the chroma phase remains uncorrected. Attempts have also been made to increase the response speed of the APC system in order to improve its correction capability, but the system operation may become unstable due to the increased sensitivity to noise.

The present invention has been made in view of the above circumstances, and provides a chroma phase correction method capable of stably and reliably removing a discontinuity in chroma phase without being affected by noise or the like contained in a video signal. is there.

Means for Solving the Problems The present invention is a system configured without using the negative feedback control by the APC circuit or the like described above, and a color burst signal included in a video signal for an integer n of at least 2 or more. Is equipped with a delay circuit of (n-1) stages that can sequentially delay by 2π / n with respect to the period of 2π, and one of the phase comparators has a color burst signal included in the input video signal and a frequency-controlled oscillator frequency divider. When a phase error occurs between the color burst signal and the frequency-divided output of the voltage-controlled oscillator, that is, the input video is provided with a circuit that selectively controls the output of the delay circuit according to the phase relationship of the output. When discontinuity occurs in the color burst signal included in the signal, the phase error is 2πk / n (k = 0.1, for the period 2π of the color burst signal,
... n), and using the detection result, the output of the n-stage delay circuit is selectively switched to correct the chroma phase of the video signal.

Function The present invention appropriately corrects the chroma phase by the above-mentioned configuration.

That is, when discontinuity occurs in the color burst signal included in the input video signal, the phase error is immediately detected, and the output of the (n-1) th stage delay circuit makes the phase of the color burst signal continuous. As described above, the correction is performed by selectively switching, and even a rapid discontinuity in the chroma phase that causes a residual error in the APC circuit or the like can be quickly and surely removed.

Embodiments A chroma phase correction method for video signals according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and particularly shows a case where n = 2 for simplicity in the integer n described in the claims. In the figure, 10 is a video signal input terminal, 20 is a video signal output terminal, 200 is a delay circuit that can delay the video signal by π (180 °) with respect to the cycle 2π of the color burst signal, and 201 is It is a selector. Further, 4 is a burst separation circuit, 110 and 111 are binarization circuits, 112 is an inverter, 113
And 114 are exclusive OR circuits, 115 is a switch, 116 and 117 are hold circuits for holding at a specific potential when the switch 115 is released, 118 and 119 are integrators composed of resistors and capacitors, 120 is a comparator. Further, 30 is an input terminal of the burst gate control signal,
Further, reference numeral 100 is an input terminal for a reference color burst signal. Especially for this standard color burst signal,
For example, since the reference color burst signal is generated by frequency conversion of the color signal at the time of VTR or control of the servo system in a video disk or the like, this can be used. In FIG. 1, the parts denoted by the same reference numerals as those in FIGS. 4 and 5 indicate the same configurations.

FIG. 2 is a signal diagram showing the operation of the signals in the capital letters in the chroma phase correction circuit according to the embodiment of the present invention shown in FIG. The signal name indicates that the signal is a signal in the same capital letters in FIG.

The operation of the chroma phase correction circuit according to the present invention configured as described above will be described below.

The video signal input from the input terminal 10 is input to the delay circuit 200 and the selector 201, and also to the burst separation circuit 4, where the color burst signal A is extracted. The color burst signal A becomes a binary signal B which can be logically operated by the binarizing circuit C, and the exclusive OR circuit 113.
And sent to 114. Similarly, the reference color burst signal B from the input terminal 100 is also binarized by the binarization circuit 111.
Is binarized into a signal D, which is sent to the exclusive OR circuit 113, and at the same time, sent to the inverter 112 to become a signal C'in which the phase is inverted. The exclusive OR circuit 113 outputs the signal E as the exclusive OR of the signals C and D. Similarly, the exclusive OR circuit 114 outputs the signal F. On the other hand, a burst gate control signal capable of identifying the period in which the color burst of the input video signal exists is input to the input terminal 30, and the switch 115 is short-circuited only during the color burst period and is open otherwise. Therefore, the signal E
And the signal F has a waveform like the signal G and the signal H shown in FIG. Next, the hold circuits 116 and 117 are configured to hold the values immediately before the selector 115 is opened except for the color burst period. The signals G and H shown in FIG. 2 are shown in FIG. The waveforms are similar to the signals I and J shown. Further, the integrators 118 and 119 are configured to have a time constant of several burst periods, and as a result, the signals I and J shown in FIG. 2 are the same as the signals P and Q shown in FIG. 2, respectively. It becomes a waveform.

Here, since the signals P and Q are both integrated by the exclusive OR of the reference color burst signal and the color burst signal included in the input video signal, they have a voltage level corresponding to the phase difference between the two signals. Become. However, the reference color burst signals are input to the inputs of the exclusive OR circuits 113 and 114 in opposite phases to each other, and as a result, the voltage levels of the signal P and the signal Q are different from each other as shown in FIG. The voltage levels are complementary. Therefore, the color burst signal included in the input video signal becomes discontinuous and π
When a phase error of only (180 °) occurs, the waveforms of the signal A and the signal C in FIG. 2 have inverted phases. At this time, the signal E and the signal F shown in FIG. 2 have waveforms just replaced with each other, and as a result, the voltage levels of the signal P and the signal Q shown in FIG. 2 are opposite to each other. That is, π that occurred in the color burst signal included in the input video signal
The (180 °) discontinuity is detected as the difference between the voltage levels of the signal P and the signal Q. Thereafter, the comparator 120 compares the voltage levels of the signal P and the signal Q shown in FIG.
The signal R is output according to the magnitude relationship.

On the other hand, an input video signal is directly connected to one input of the selector 201, and a signal obtained by delaying the input video signal by π (180 °) at the cycle of the color burst signal is input to the other input. Therefore, if this selector is switched using the above-mentioned detection signal R, the phase shift of π (180 °) in the color burst signal of the input video signal can be removed quickly and reliably.

In addition, although the time constants of the integrators 118 and 119 are set to several burst periods in the above-described embodiments, when higher speed response is required, this can be realized by shortening this time constant.

Further, in the above embodiments, the discontinuity of the color burst signal included in the input video signal is simply expressed by a phase error of π (180 °), and the detection result is used to convert the input video signal of the system to the color burst signal. Although it was controlled whether the phase is shifted by π (180 °) in the cycle, if more stable phase correction is required, the cycle of the color burst signal is 2π.
On the other hand, (n-1) delay circuits that can phase-shift the input video signal by 2π / n (n = 2,3,4, ...) are cascaded to obtain the color burst signal included in the input video signal. The discontinuity is detected as a phase difference of 2πk / n (0 ≦ k <n), and the detection result is used to selectively switch the outputs of the (n−1) delay circuits to achieve more stable operation. A chroma phase correction circuit can be configured.

As described above, according to the present invention, even if a color burst signal included in an input video signal causes a large phase error, it can be immediately detected and the phase can be corrected.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a chroma phase correction method for a video signal according to the present invention, and FIG. 2 is a signal showing the operation of each part of the chroma phase correction circuit according to the present invention shown in FIG. 3 is a diagram showing one of the problems of the conventional technique, FIG. 4 is a block diagram showing the configuration of the conventional chroma phase correction system, and FIG. 5 is the conventional write clock in FIG. It is a block diagram which shows the detail of a generation circuit. 1 ... A / D conversion circuit (A / D), 2 ... memory, 3 ... D / A
Conversion circuit (D / A), 4 ... Burst separation circuit, 10 ... Circuit input terminal, 20 ... Circuit output terminal, 30 ... Burst gate control signal input terminal, 40 ... Reference signal input terminal , 50 ... write clock generation circuit, 60 ... write address control circuit, 70 ... read address control circuit,
80 ... Read clock generation circuit, 51 ... Write clock generation circuit input terminal, 52 ... Write clock generation circuit output terminal, 53 ... Phase comparator, 54 ... Burst gate circuit, 55 ... Low pass Filter (LPF), 56 ... Voltage controlled oscillator (VCO), 57 ... Divider, 100 ... Reference color burst signal input terminal, 110, 111 ... Binarization circuit, 112 ... Inverter, 113, 114 ... Exclusive OR circuit, 115 ... Switch, 116,117 ... Hold circuit, 118,
119 ... integrator, 120 ... comparator, 200 ... delay circuit, 201
……selector.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kojiro Matsumoto 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) Reference JP-A-53-60517 (JP, A) JP-A-61-171295 (JP, A)

Claims (1)

[Claims] 1. A chroma phase correction circuit for removing discontinuity of a chroma signal component included in a composite video signal, wherein a period 2π of a color burst signal included in the composite video signal is at least 2 or more n. For 2π
The amount of delay of the composite video signal can be varied sequentially by n / n
-1 stage of delay means and the change in the phase of the chroma signal component contained in the composite video signal are expressed as 2πk / n with respect to n.
A video signal comprising a phase difference detecting means for detecting a phase difference of (1k <n, k is an integer), and controlling a delay amount of the delay means by using a detection result of the phase difference detecting means. Chroma phase correction method.