JPH0413280A - Phased lock loop circuit for recording and reproducing information - Google Patents

Abstract

PURPOSE:To prevent the starting of a PLL operation from an erroneous frequency or phase when using a subjected sample-and-hold value as a reference and releasing a missing part by converting the output of a lowpass filter means to the output of a sample-and-hold means when missing a reproduced information signal. CONSTITUTION:This circuit is provided with a voltage controlled oscillation means 3, a phase comparator means 1, a lowpass filter means 2, a sample-and- hold means 5, and a switch means 6. In this case, when the reproduced signal from an information recording medium is missed, the frequency and phase of the reproducing clock is subjected to sample-and-hold in the stable state not just after but just before the reproducing signal is missed. When a data missing signal from a reproducing signal missing detection circuit 4 occurs, the switch circuit 6 suitably converts a direct output from the lowpass filter 2 to a sample-and-hold output by the sample-and-hold part 5. Thus, the synchronization after the reproducing signal is recovered can easily be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phased-lock loop circuit for information recording and reproduction that creates a reproduction clock for reproducing information from an information recording medium.

[Prior Art] Generally, when reproducing digitally recorded information, it is necessary to create a clock called a reproduction clock in order to reproduce data from a reproduction signal. The reproduced clock is generally created using a phased lock loop (hereinafter abbreviated as PLL) circuit based on a signal (detection signal) obtained by binarizing the reproduced signal.

FIG. 11 shows a block diagram of a PLL circuit. This PLL circuit has a series circuit of a phase comparator 1, a low-pass filter (hereinafter referred to as LPF) 2, and a voltage controlled oscillator (hereinafter referred to as VCO) 3, and the output of the VCO 3 is fed back to the phase comparator 1. The structure is as follows. The phase comparator 1 receives a detection signal obtained by binarizing a reproduction signal from an information recording medium (not shown) and a VCO.
It compares the output of B and outputs the phase difference as a voltage. Further, the LPF 2 allows only the low frequency component of the output of the phase comparator 1 to pass through and supplies it to the VCOB. Further, the VCOB is designed to generate an output signal having a frequency corresponding to the output voltage of the LPF 2 as a recovered clock.

In this way, the PLL circuit feeds back the output signal of the VCOB to the phase comparator 1, and detects the phase difference so that its output frequency and phase always match the frequency and phase of the detection signal that is input to the PLL circuit. The structure is such that feedback is provided.

Generally, when the gain or cutoff frequency of the open loop transfer function of the PLL circuit is increased, the sensitivity of the PLL increases, and it becomes easier to follow fluctuations in the frequency and phase of the detection signal. For example, even if there is a lot of jitter in the moving speed of the information recording medium and the frequency and phase of the detection signal move significantly,
It is possible to follow the fluctuations. On the other hand, if the sensitivity of the PLL is high, synchronization is likely to occur when the reproduced signal is lost due to defects such as scratches or dust on the information recording medium.

FIG. 12 is a block diagram of a conventional PLL circuit designed to reduce synchronization of the PLL due to missing reproduction signals. In this figure, the same parts as in FIG. 11 are given the same reference numerals.

In the PLL circuit configured as shown in FIG. 12, in addition to the circuit shown in FIG. 11 described above, there is also a reproduction signal loss detection circuit 4 that detects loss of the reproduction signal and generates a data loss signal S1; It is connected between LPF2 and VCOB.
Normally, the output of LPF2 is output directly to VCOB,
The configuration includes an additional sample and hold section 5 that samples and holds the output of the LPF 2 when the data missing signal S1 is generated. In other words, the sample and hold section 5 prevents the PLL circuit from following the loss of the reproduced signal.

Furthermore, FIG. 13 shows another conventional example, in which a sample-and-hold signal generation section 5A is connected between the reproduced signal loss detection circuit 4 and the sample-and-hold section 5 of the PLL circuit shown in FIG. ing.

That is, each output from the reproduced signal loss detection circuit 4, the LPF 2, and the sample hold section 5 is supplied to the five sample and hold signal generation sections, and the sample and hold signal is supplied to the sample and hold section 5 from the sample and hold signal generation section 5A. Output. The other configuration is similar to the circuit configuration shown in FIG.

In the PLL circuit of FIG. 13, the data missing signal S1
is supplied from the reproduced signal loss detection circuit 4, when VC
The output of LPF2, which was applied as it is to the OB's manual power, is sampled and held by the sample and hold section 5,
Applied to VCOB. As a result, the output of the VCOB, that is, the frequency and phase of the recovered clock, is maintained.
This prevents synchronization from occurring due to omissions. Then, at the time when the missing part of the signal is removed, the LP
Since the hold operation of the sample and hold section 5 is released when the output of F2 falls within a certain range determined from the output of the sample and hold section 5, there will be no large change in the input of VCOB when the signal is lost and when the signal is restored. This change prevents loss of synchronization and makes it easy to lock the PLL again. Furthermore, these P
The LL circuit is referred to in Japanese Patent Laid-Open No. 64-234613 and Japanese Patent Laid-Open No. 64-23467.

[Problems to be Solved by the Invention] The conventional reproduced signal loss detection circuit 4 outputs a data loss signal S1 for sampling and holding the frequency or phase state immediately after a signal is lost. In other words, at the time when this data missing signal S1 is output,
Since a dropout has already occurred, there is a possibility that the frequency or phase value has shifted.

Therefore, if the sampled and held value is used as a reference, the PLL operation will start from the wrong frequency or phase when the missing part is released, resulting in unnecessary time being spent until synchronization or loss of synchronization. There was a problem.

This invention has been made in view of the above points, and provides a PLL for reproducing recorded information that can extremely reduce synchronization of the PLL when the missing portion of the reproduced signal is canceled.
The purpose is to provide circuits.

[Means for Solving the Problems] That is, the present invention provides voltage-controlled oscillation means for generating a reproduction clock for reproducing information recorded on an information recording medium, and an output of the voltage-controlled oscillation means and a reproduction clock for reproducing information recorded on an information recording medium. In a phased lock loop circuit comprising a phase comparison means for comparing the phase with an information signal, and a low-pass filter means for extracting a low frequency component of the output of the phase comparison means and applying it to the voltage-controlled oscillation means, the low-pass filter It is characterized by comprising sample-hold means for sampling and holding the output of the means, and switching means for switching the output of the low-pass filter means to the output of the sample-hold means when a dropout occurs in the reproduced information signal. do.

[Function] The phased-locked loop (PLL) circuit for reproducing recorded information according to the present invention is configured such that when a reproduction signal from an information recording medium is lost, the reproduction signal is not immediately after the reproduction signal is lost, but when the reproduction signal is lost. Sample and hold the frequency and phase of the reproduced clock in the previous stable state. When a data loss signal is generated from the reproduced signal loss detection circuit, the switching circuit appropriately switches the direct output from the low-pass filter to the output sampled and held by the sample and hold section. Thereby, synchronization can be easily performed after the reproduction signal is restored.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram schematically showing a PLL circuit for recording and reproducing information according to the present invention, and the same parts as in FIGS. 11 to 13 are given the same numbers.

For example, in the case of a magneto-optical reproducing device, an information signal reproduced from an information recording medium (e.g., a magneto-optical disk) amplifies the output of a photodetector that detects reflected light with a preamplifier, and passes through a waveform equalization circuit and an AGC circuit. Along with the above processing, the signal is converted into a binary signal by a binarization means. A binary signal is supplied to the phase comparator 1, and the output of this phase comparator 1 is supplied to the LPF 2. The output voltage of the LPF 2 is then output to a sample hold section 5 and a switching circuit 6, which will be described later. A data missing signal -81 is outputted to the sample hold section 5 from the reproduced signal missing circuit 4 which detects the missing of the reproduced signal. The switching circuit 6 includes:
The outputs of the LPF 2, the reproduced signal dropout circuit 4, and the sample hold section 5 are supplied. Furthermore, the VCO 3 receives the output of the switching circuit 6 and outputs the controlled voltage to the outside and to the phase comparator 1.

FIG. 2 shows a detailed circuit diagram of the reproduced signal loss detection circuit 4. As shown in FIG.

The RF multiplied signal, which is input to the playback signal loss detection circuit 4 and is the output of the preamplifier, a rectifier circuit 41, and a resistor 42
The signal is input to the negative terminal of the comparator 48 via the signal. Further, the negative terminal of this comparator 43 is grounded via a capacitor 44. On the other hand, the positive terminal of the comparator 43 is connected to the +5V power supply via a resistor 45 and grounded via a resistor 46.

The output end of the comparator is connected to a +5VW source via a resistor 47 of Ω to, for example, 4 and 7, from which a data loss signal is output to the sample hold section 5 and the switching circuit 6. .

Here, the operation of the reproduced signal loss detection circuit 4 will be explained with reference to the timing charts of each waveform shown in FIGS. 3(a) to 3(d).

After the RF multiplied signal shown in FIG. 3(a) is rectified by a rectifier circuit 41 (see FIG. 3(b)), it is integrated by an integrating circuit consisting of a resistor 42 and a capacitor 44.

As a result, the RF multiplied signal has an RF multiplied signal envelope as shown by the solid line in FIG. 3(C), and is input to the negative terminal of the comparator 43. Then, in this comparator 43, the voltage is divided by the resistors 45 and 46, and the third
It is compared with a predetermined potential shown by a dotted line in Figure (c). Suppose now that the potential input to the negative terminal of the comparator 43 has fallen below the potential of the positive terminal (time t1 to t2). Then, a data missing signal S1 representing the missing RF signal is generated.
is outputted to the sample hold section 5 and the switching circuit 6 (see FIG. 3(d)).

FIG. 4 shows a schematic configuration example of the sample hold section 5. As shown in FIG. The output voltage VIN of the LPF 2 is supplied to one input terminal of an operational amplifier 52 via a switch 50 and a resistor 51 that control on/off of this voltage V1N. switch 5
0 is connected to the capacitor 53 to be charged when the switch 50 is turned on, and is also connected to the other input terminal of the operational amplifier 52. operational amplifier 52
The output of is supplied to the one input terminal and is also output to the switching circuit 6. The switch control signal S2 for controlling the opening and closing of the switch 50 is supplied with a reset signal and a clock for initializing the device at startup, respectively, from the reset generation circuit 54 and the oscillator 55, and the flip-flops 56° and 5B. It is created by a periodic shift register 58 configured by □, 56°. In this case, the shift register 56 is composed of three stages of flip-flops, but the present invention is not limited to this, and any number of stages of flip-flops may be used.

Next, the operation of the sample and hold circuit 6 will be explained with reference to the timing charts of each waveform shown in FIGS. 5(a) to 5(e).

The switch control signal S2 is output as a sample period from time tll to t1□ from the shift register 56 to which the reset signal and clock as shown in FIGS. 5(a) and 5(b) are supplied. (See Figure (c)) Then, in response to this switch control signal S2, the switch 50 is controlled, and the output voltage VIN of the LPF2 is changed to the capacitor 53.
is charged to.

Then, at time t12, the switch control signal S2 is turned off and the switch 50 is turned off, and the voltage held in the capacitor 53 during the sample period is output. Then, the voltage VI actually increases during the hold period t+2 to t+3.
It can be seen that even if N changes (see FIG. 5(d)), the output of the sample period is outputted as the output of the sample-and-hold circuit 5, and there is no change (see FIG. 5(e)).

FIG. 6 shows the output of the LPF 2 and the sample hold section 5 as a data missing signal S1 which is the output of the reproduced signal missing detection circuit 4.
FIG. 2 is a circuit diagram showing the configuration of a switching circuit 6 that switches according to the following.

The output of the LPF 2 and the output of the sample hold section 5 are as follows:
Each signal is supplied to the VCO 3 via an analog switch 61. The analog switch 6I is
Data missing signal S which is the output of the reproduced signal missing detection circuit 4
1. In this case, the data missing signal S1 is supplied as is to the output side of the LPF 2, and an inverted signal is supplied to the output side of the sample hold circuit 5 via the inverter 62. Depending on the positive/negative state of this data missing signal S1, the outputs of the LPF 2 and the sample hold section 5 are appropriately switched and outputted to the VCO 3.

FIG. 7 shows a more detailed block diagram of the sample hold section 5 in the information recording/reproducing PLL circuit shown in FIG. 1. In addition, in FIG. 7, the same parts as in FIG. 1 are given the same numbers, and the explanation thereof will be omitted.

In FIG. 7, the data missing signal S1, which is the output of the reproduced signal missing detection circuit 4, is supplied to the switching circuit 6, and is also sent to the shift register 56 as a gate signal for sampling and holding via the inverter 7. Supplied.

From this shift register 56, sample and hold circuits 57 and 58 are connected to D-flip-flops 56. and 563 Q signals are output as output 1 and output 2. The sample and hold circuits 57 and 58 include an LPF.
2 outputs are also provided. The identification circuit 59 selects the sample and hold circuits 57 and 5 in response to the data missing signal S1.
This is for supplying any one of the outputs of 8 to the switching circuit 6 as the output S3.

The identification circuit 59 has a block configuration as shown in FIG. That is, the data loss signal S1 is input to the flip-flops 8 and 9 together with the outputs of the sample and hold circuits 57 and 58. Then, the Q outputs of the flip-flops 8 and 9 and the data missing signal S1 are input to AND gates 10 and 11. Then, switches 12 and 13 are turned on and off by the outputs of AND gates 10 and 11, thereby selecting whether or not to supply the outputs of sample and hold circuits 57 and 58 to switching circuit 6.

According to such an output path 59, the output S3 is supplied to the switching circuit 6 upon receiving the output from one of the sample and hold circuits 57 and 58. for example,
When the data loss signal S1 becomes "high",
control input level of sample and hold circuits 57 and 58;
That is, output 1 and output 2 of the shift register 5B are monitored, and the output of the sample hold circuit whose level is "low" is set as the output S3. As a result, if the sample-and-hold circuit on the hold period side is used when the data missing signal S1 is in a "high" state, a stable one will be output.

Next, the overall operation of the phased-lock loop circuit for reproducing recorded information according to the second invention will be explained with reference to FIGS. 9(a) to 9(i).

As shown in FIGS. 9(a) and 9(b), when the RF multiplied signal and the binarized signal are supplied and the PLL circuit operates, the L
The output of PF2 is in the state shown after time t21 in FIG. 9(c). In this state, the inputs of the sample and hold circuits 57 and 58 are repeatedly held and reset by output 1 and output 2 of the shift register 56, respectively, as shown in FIGS. 9(f) and (g). There is. In this case, Sl (see FIG. 9(e)), which is an inversion of the data missing signal S1 in FIG. 9(d), is used as a reset signal for the shift register 5B. In this case as well, the output of the reset generation circuit 54 is used as a reset signal.

Here, from time t22 to t23, the reproduced signal (RF
Suppose that a dropout occurs in the double signal. Then, as shown in FIG. 9(d), the data missing signal S1 changes from "low" to "
The state changes to "high" to indicate that a loss has occurred. This data missing signal S1 causes the sample hold circuit 58
The output is outputted to the switching circuit 6 as the output S3 via the Hawkbetsu circuit 59 (see FIG. 9(h)).

The switching circuit 6 supplies the output S3 to the VCO 3 as the output of the LPF 2. Here, the sample and hold circuits 57 and 58 always take in a state before the current state (for example, 1 time α time ago) by the shift register 56. That is, at the time when the data missing signal S1 changes from "low" to "high" state (time t2□), the sample hold 58 has taken in the state from a time ago.

This becomes even clearer if we consider that the data loss signal S1 changes in synchronization with the switch timing of the sample and hold circuit 57. Therefore, the switching circuit 6
The output is maintained at a stable level even during the time period t2□ to t23 when the above-mentioned dropout occurs (see FIG. 9(i)).

By the way, in the embodiment described above, the output S2 of the shift register 56 in FIG. 4 is used as the Q output of the third stage. However, as the output of the shift register 56, it is not necessary to use the Q outputs of the first and third stages, for example, the Q and Q outputs of the third stage.
It can also be used as output. In other words, if the input signals of the sample and hold circuits 57 and 58 in FIG. 7 are inverted from each other as shown in FIGS. 10(a) and (b), the state one clock ago is Since the sample is held, it is possible to obtain the same effect as in the embodiment described above.

Furthermore, in the above-described embodiment, the sample-and-hold section 5 has two sample-and-hold circuits, ie, the sample-and-hold circuits 57 and 58, but the present invention is not limited to this. For example, a single sample and hold circuit may be used, with a short sample period and a long hold period.

In this case, the circuit configuration can be more simplified than the circuit of the embodiment shown in FIG.

In this way, even if a loss occurs in the reproduced signal, the LPF output of the PLL circuit can hold the LPF output in a stable state without maintaining the unstable state immediately after the loss. It is possible to perform a stable PLL operation with respect to

[Effects of the Invention] As described above, according to the present invention, even if the sample-held value is used as a reference, when the missing part is removed,
PLL operation will not start from the wrong frequency or phase, and unnecessary time will be spent until synchronization.
It is possible to provide a PLL circuit for reproducing recorded information that can greatly reduce the problem of out-of-synchronization.

Furthermore, by holding the output of the low-pass filter means for a predetermined time immediately before a data missing signal occurs in the reproduced signal missing detecting means, even if a missing data signal occurs in the reproduced signal, the PL
The LPF output of the L circuit can hold the LPF output in a stable state rather than in an unstable state immediately after a dropout, and stable PLL operation can be performed in response to the dropout.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of a PLL circuit for recording and reproducing recorded information according to the present invention, and is a block diagram schematically showing the PLL circuit for recording and reproducing information, and FIG. 2 is a detailed circuit configuration diagram of the reproduced signal missing detection circuit of FIG. 1. , FIGS. 3(a) to 3(d) are timing charts showing each output waveform of the reproduced signal loss detection circuit 4 of FIG. 2, FIG. 4 is a schematic circuit configuration diagram of the sample hold section of FIG. 1, 5(a) to (e) are timing charts showing each output waveform of the sample and hold section in FIG. 4, FIG. 6 is a circuit diagram showing the configuration of the switching circuit in FIG. 1, and FIG. A block diagram schematically showing a PLL circuit for information recording and reproducing in which the sample hold section shown in the figure is shown in more detail. (i) is a timing chart showing each waveform of the recorded information reproducing PLL circuit in FIG. 7, and FIGS. 10(a) and (b) are timing charts showing waveforms of different input examples of the sample hold circuit in FIG. 7. , Figures 11 to 13
Both figures are block diagrams of conventional PLL circuits. 1... Phase comparator, 2... Low pass filter (LP
F) 3... Voltage controlled oscillator (VCO), 4...
Playback signal loss detection circuit, 5... sample hold section,
6...Switching circuit, 5B...Shift register, 57
．． 58...Sample hold circuit, 59...Identification circuit. Figure 1

Claims (1)

[Claims] Voltage controlled oscillation means for generating a reproduced clock for reproducing information recorded on an information recording medium, and a phase comparison between the output of the voltage controlled oscillation means and the reproduced information signal. In a phased lock loop circuit comprising a comparison means and a low-pass filter means for extracting a low frequency component of the output of the phase comparison means and applying it to the voltage-controlled oscillation means, a sample for sampling and holding the output of the low-pass filter means is provided. A phased-locked loop for reproducing recorded information, comprising: a holding means; and a switching means for switching the output of the low-pass filter means to the output of the sample-hold means when a dropout occurs in the reproduced information signal. circuit.