JPH0340266A - Controller for oscillation circuit - Google Patents

Abstract

PURPOSE:To acquire an n-fold output frequency of a video frame frequency Fv and to reduce output jitter only by passing through two PLL circuits by switching the frequency dividing ration of a second frequency divider corresponding to a sampling frequency. CONSTITUTION:The frequency dividing ratio of a second frequency divider 5 is switched corresponding to the sampling frequency so as to select one frequency to satisfy a condition that an output frequency B of a frequency dividing block 3 is 30.K times to an n FV fold output frequency C composed by a PLL circuit 6 and 1/2<j> to the greatest common measure between the output frequency C and a 2<m>.fs fold frequency to an output A of a voltage control oscillator. Accordingly, the n-fold output frequency of the video frame frequency Fv synchronous to a PCM audio can be acquired only passing through two PLL circuits 2 and 6. Thus, the output jitter can be reduced to the video frame frequency Fv.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an oscillation control device capable of synchronizing a PCM audio sampling frequency fs and a video frame frequency Fv.

Conventional technology, for example, the Dinotal audio tape recorder (hereinafter referred to as
As the system frequencies for the DAT (referred to as DAT), two minimum frequencies are required: the 2-fs multiplication wave number for the PCM audio system and 9.408 MHz, which is necessary for recording and reproducing the DAT. Furthermore, when it is necessary to play PCM audio in synchronization with images such as video, it is common to use SMPTE time code as a time management means.
A frequency n times the video frame frequency Fv is also required.

At least these three frequencies can be used with PCM if variable pitch playback function or external clock synchronization is required.
9.40 for audio system 2II fs multiplication wave number
Synchronization is required between 8 MHz and a frequency n times the video frame frequency Fv. Here, fs is the sampling frequency of PCM audio.

The configuration of a conventional oscillation control circuit is shown in FIG. 3, and will be explained below.

Two, sampling frequency fgl=48KHz1fs
2=44. An output frequency of 1 KHz is input to the PLL circuit 2 via a selection circuit 1 that can be switched by an fs switching control signal S (hereinafter referred to as control signal S). PLL
One of the output frequencies of the voltage controlled oscillator of circuit 2 is P
The system frequency for commercial audio is supplied to signal processing circuits, A/D conversion circuits, D/A conversion circuits, etc., and the other is 9.408MH, which is necessary for DAT recording and playback.
In order to obtain the output frequency of z, the PLL circuit 1 is
2 is input. Further, the output frequency of the voltage controlled oscillator of the PLL circuit 12 is input to the PLL circuit 6 via the frequency divider 5 in order to obtain a frequency n times the video frame frequency Fv synchronized with PCM audio.

The operation of the apparatus configured as described above will be explained below.

Two sampling frequencies of PCM audio fsl=
48 KHz, fs2=44.1 KHz is input to the selection circuit 1, and its output is a control signal S to select either fsl or fs2. Now, if fsl is selected by the control signal S, 48 KHz is input to the PLL circuit 2. As shown in FIG. 2, the PLL circuit 2 has a configuration that uses the output frequency D = 48 KHz of the selection circuit 1 as a reference input, a phase comparison circuit 7 that compares the phase with the reference frequency E, and a difference signal of the phase comparison circuit. A smoothing low-pass filter 8, a voltage-controlled oscillator 10 that generates a frequency according to the output voltage of the low-pass filter, and a frequency divider 9 that divides the frequency of the output A of the voltage-controlled oscillator to a frequency 2−·fs times.
A closed loop is constructed by using the frequency divider output as the reference frequency E of the phase comparator circuit 7. The output frequency A of the voltage controlled oscillator of the PLL circuit 2 is supplied to a signal processing circuit, an A/D conversion circuit, a D/A conversion circuit, etc. as a PCM audio system frequency.

9.408 MHz required for recording and reproducing the DAT shown in Figure 3
In systems that require a variable pitch playback function or external clock synchronization, the output frequency F of is a PLL that generates a frequency of 9.408 MHz from a frequency multiplied by 2-fs in order to synchronize with the fs frequency of the PCM audio system. circuit 1
2 is required, and its configuration is the same as PLL circuit 2, and the reference input frequency and low-pass filter 8 in Fig. 2 are required.
characteristics, the output frequency A of the voltage controlled oscillator 10, and the frequency divider 9
The only difference is the values of the frequency division ratio, etc.

Between the output A of the PLL circuit 2 and the input of the PLL circuit 12,
A frequency dividing circuit block 11 that can be selected by the control signal S is inserted, and its output frequency is 9.408 MHz and 2
A frequency is set that is 1000 times the greatest common divisor of the wave number for "fs1 times" and "2"*fs2 times the wave number. Specifically, in FIG. 3, the output frequency of the frequency divider block 11 is fsl=
In the case of 48KHz, it is 192KHz, fs2=44.
In the case of 1KH frequency, the division ratio is 1 which becomes 235.2KHz.
/82-4 times and 1/32.3 times are set by switching with respective control signals S. At the same time, the set value of the frequency divider 9 of the PLL circuit 12 is also fsl=48K) (l/4 in the case of z)
9 times, f sl = 44. For 1 K H, l/4
Set to 0x.

With the above frequency division ratio setting value, the frequency of the output F of the PLL circuit 12 is 9.408 MHz even if the control signal S is switched.
becomes a constant value.

Furthermore, in order to obtain a wave number C for n times the video frame frequency Fv that is synchronized with the fs frequency of the PCM audio system, 9,408 MHz is divided by the frequency divider 5 regardless of the control signal S mentioned above, and the frequency is P as reference input
When generated by the LL circuit 6, the wave number C for n times the video frame frequency Fv is obtained at the output of the PLL circuit 6 in synchronization with the fs frequency of the PCM audio system.

Problems to be Solved by the Invention However, in the conventional configuration described above, at least three PLL circuits 2. , 12. 6, three frequency jitters of the PLL circuit are accumulated, and there is a problem that the output shift of the SMPTE time code with respect to the video frame frequency Fv becomes large.

The present invention provides f' from fs frequency input of PCM audio.
An object of the present invention is to provide a control device for an oscillation circuit that can obtain an output frequency n times the video frame frequency Fv by simply passing through two PLL circuits until the output frequency is n times the video frame frequency Fv synchronized with s. .

Means for Solving the Problems To achieve this object, the control device of the present invention provides
A frequency divider that can switch the output frequency A of the voltage controlled oscillator of the L circuit according to the sampling frequency fs, and a frequency divider that can switch the output frequency of the frequency divider according to the video frame frequency (29.97...Hz in the case of NTSC color). With the configured divider,
The output frequency of the frequency divider is multiplied by 30 times the output frequency C which is n·Fv times, in order to obtain the output frequency C which is n·Fv times.
In addition, the frequency division of the second frequency divider is performed so as to select one frequency that satisfies the condition that the output frequency is 172J times the greatest common divisor of the wave number for multiplying the output A of the voltage controlled oscillator of the PLL circuit 2 by 2a·fs. The ratio is changed according to the sampling frequency.

According to the present invention, with the above-described configuration, in order to obtain an output frequency n times the frame frequency Fv synchronized with the sampling frequency fs of PCM audio, the present invention passes through two PLL circuits, compared to the conventional device that passes through three PLL circuits. It is only possible.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a control device for an oscillation circuit in an embodiment of the present invention. In Fig. 1, two sampling frequencies of PCM audio, fsl = 48KHz, fs
The output frequency of the selection circuit 1 which can switch the input of 2=44.1KHz using the control signal S, and the PLL circuit 2 which outputs the frequency 2II·fs times as shown in Fig. 2 with its output as the reference input. The frequency divider circuit block 3, which can switch A according to the sampling frequency f s "48 KHz+44.1 KHz, is set to 1/x times in the case of f sl and 1/Y times in the case of f's2. At this time The values of 1/x and 1/V of PLL circuit 6
30 times the output frequency C obtained by n e Fv times, and 1/ of the greatest common divisor of the output frequency C and the frequency within 2/fs times the output A of the voltage controlled oscillator of the PLL circuit 2.
It is set to select one frequency that satisfies the condition of multiplying by 2.

The output frequency A of the PCM audio system is 2a fs times the control signal S than each frequency division ratio set under the above conditions.
Regardless of whether fsl or fs2 is selected in , it is fixed to one frequency.

Furthermore, 1. To obtain the n-times wave number C of the video frame frequency Fv that is synchronized with the fs frequency of the PCM audio system,
PL4. which divides one frequency by the frequency divider 5 regardless of the control signal S described above and uses the frequency as a reference input.
When generated by the circuit 6, a wave number C for n times the video frame frequency Fv is obtained at the output of the P, LL circuit 6 in synchronization with the fs frequency of the PCM audio system.

Effects of the Invention As described above, according to this embodiment, the output frequency B of the frequency dividing circuit block 3 is changed to the n11 F
+/ times the output frequency C and 2Il@ of the output frequency C and the output A of the voltage controlled oscillator of the PLL circuit 2.
Since the frequency division ratio of the second frequency divider was configured to be switched according to the sampling frequency of 48 KHz to 144.1 KHz so as to select one frequency that satisfies the condition of 172 J, which is the greatest common divisor of the fs multiplication wave number, the PCM When obtaining an output frequency that is n times the video frame frequency Fv synchronized with audio, it is possible to obtain an output frequency that is n times the video frame frequency Fv by going through two PLL circuits, compared to the conventional device that goes through three PLL circuits. It is possible to reduce the output of the SMPTE time code relative to Fv.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a control device for an oscillation circuit in an embodiment of the present invention, FIG. 2 is a block diagram showing the internal configuration of a PLL circuit, and FIG. 3 is a block diagram showing a conventional control device for an oscillation circuit. be. 1.4...Selection circuit, 2,6...PLL circuit,
3... Frequency divider circuit block, 5... Frequency divider 7.
...Phase comparator circuit, 8...Low pass filter,
9... Frequency divider, 10... Voltage controlled oscillator.

Claims (1)

[Claims] Two sampling frequencies of PCM audio fsl=
A first selection circuit whose output frequency is 48KHz, f_s2=44.1KHz can be switched by a sampling frequency switching control signal, a phase comparison circuit that compares the phase of the output frequency of the selection circuit and a reference frequency, and a phase comparison circuit. A low-pass filter that smoothes the difference signal of the circuit, a voltage-controlled oscillator that generates a frequency according to the output voltage of the low-pass filter, and an output frequency of the voltage-controlled oscillator that is 2^
(1) A first frequency divider that divides the frequency by f_s times, a first PLL circuit for frequency multiplication that configures a closed loop using the first frequency divider output as the reference frequency, and the voltage control circuit. Oscillator output frequency sampling frequency 48KH
z, 44, 1KHz, a third frequency divider that divides the output of the second frequency divider into a video frame frequency, and the third frequency divider. A second PLL circuit having the same configuration as the first PLL circuit which inputs the output frequency of
The second PLL circuit has an output of n
・In order to obtain a frequency times Fv, the frequency of the second frequency divider output is set to 30·K times the frequency multiplied by n·Fv, and n
・1 of the greatest common divisor of the frequency Fv times and the output frequency of the voltage controlled oscillator of the first PLL circuit is 2^■・fs times
Just like selecting a frequency that satisfies the condition of multiplying by /2^J,
The frequency division ratio of the second frequency divider is set to a sampling frequency of 48K.
Switched according to Hz, 44.1KHz,
An oscillation circuit control device characterized by: