JPS63100837U - - Google Patents
Info
- Publication number
- JPS63100837U JPS63100837U JP19563186U JP19563186U JPS63100837U JP S63100837 U JPS63100837 U JP S63100837U JP 19563186 U JP19563186 U JP 19563186U JP 19563186 U JP19563186 U JP 19563186U JP S63100837 U JPS63100837 U JP S63100837U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- internal circuit
- mos type
- check
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Weting (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Description
第１図は本考案の第１の実施例の平面図、第２
図は本考案の第２の実施例の平面図、第３図は従
来のチエツクトランジスタの平面図である。
１……拡散領域、２……ゲート電極、３ａ〜３
ｆ，４ａ，４ｂ……ダミーゲート、５ａ〜５ｃ…
…コンタクト、６ａ〜６ｃ……電極パツド。
Figure 1 is a plan view of the first embodiment of the present invention;
This figure is a plan view of a second embodiment of the present invention, and FIG. 3 is a plan view of a conventional check transistor. 1... Diffusion region, 2... Gate electrode, 3a-3
f, 4a, 4b...dummy gate, 5a-5c...
...Contact, 6a to 6c...Electrode pad.
Claims (1)
部回路トランジスタの特性検査用のチエツクトラ
ンジスタが同一基板上に形成されたＭＯＳ型半導
体装置において、前記チエツクトランジスタのゲ
ートパターンを前記内部回路トランジスタ列と同
等のゲートパターンならしめるようなダミーゲー
トパターンを前記チエツクトランジスタのゲート
の両側に配置したことを特徴とするＭＯＳ型半導
体装置。 In a MOS type semiconductor device in which a MOS type internal circuit transistor and a check transistor for testing the characteristics of the internal circuit transistor are formed on the same substrate, the gate pattern of the check transistor is the same as the gate pattern of the internal circuit transistor array. 1. A MOS type semiconductor device, wherein dummy gate patterns are arranged on both sides of the gate of the check transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19563186U JPS63100837U (en) | 1986-12-18 | 1986-12-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19563186U JPS63100837U (en) | 1986-12-18 | 1986-12-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63100837U true JPS63100837U (en) | 1988-06-30 |
Family
ID=31153692
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19563186U Pending JPS63100837U (en) | 1986-12-18 | 1986-12-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63100837U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005303089A (en) * | 2004-04-13 | 2005-10-27 | Nec Electronics Corp | Semiconductor device |
-
1986
- 1986-12-18 JP JP19563186U patent/JPS63100837U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005303089A (en) * | 2004-04-13 | 2005-10-27 | Nec Electronics Corp | Semiconductor device |
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