JPS61192459U - - Google Patents
Info
- Publication number
- JPS61192459U JPS61192459U JP1985076636U JP7663685U JPS61192459U JP S61192459 U JPS61192459 U JP S61192459U JP 1985076636 U JP1985076636 U JP 1985076636U JP 7663685 U JP7663685 U JP 7663685U JP S61192459 U JPS61192459 U JP S61192459U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- semiconductor
- semiconductor device
- lower electrode
- showing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 13
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
Description
第１図は本考案の一実施例による半導体装置を
示す平面図、第２図は第１図に示す半導体装置に
実装されるパワーＭＯＳトランジスタを示す平面
図、第３図は第１図に示す半導体装置におけるパ
ワーＭＯＳトランジスタの実装構造を示す断面図
、第４図は従来の半導体装置の一例を示す平面図
、第５図は半導体装置を用いたモータの駆動回路
を示す回路図、第６図は第５図に示す駆動回路の
動作を説明するタイミングチヤート、第７図は従
来の半導体装置の他の例を示す平面図である。
１０ａ，１０ｂ，１０ｃ，１０ｄ…パワーＭＯ
Ｓトランジスタ、１１…実装基板、１２…ソース
パツド、１３…ゲートパツド。
1 is a plan view showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a plan view showing a power MOS transistor mounted on the semiconductor device shown in FIG. 1, and FIG. 3 is a plan view showing the power MOS transistor shown in FIG. 4 is a cross-sectional view showing a mounting structure of a power MOS transistor in a semiconductor device; FIG. 4 is a plan view showing an example of a conventional semiconductor device; FIG. 5 is a circuit diagram showing a motor drive circuit using the semiconductor device; FIG. 5 is a timing chart explaining the operation of the drive circuit shown in FIG. 5, and FIG. 7 is a plan view showing another example of the conventional semiconductor device. 10a, 10b, 10c, 10d...Power MO
S transistor, 11... Mounting board, 12... Source pad, 13... Gate pad.
Claims (1)
方の半導体素子が実装基板上に装着されるととも
に、他方の半導体素子が一方の半導体素子上に装
着され、かつ前記一方の半導体素子の上部電極と
、他方の半導体素子の下部電極とが接続されたこ
とを特徴とする半導体装置。 comprising a plurality of semiconductor elements connected to each other, one semiconductor element is mounted on a mounting board, the other semiconductor element is mounted on one semiconductor element, and an upper electrode of the one semiconductor element; A semiconductor device characterized in that a lower electrode of another semiconductor element is connected to the lower electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985076636U JPS61192459U (en) | 1985-05-23 | 1985-05-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985076636U JPS61192459U (en) | 1985-05-23 | 1985-05-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61192459U true JPS61192459U (en) | 1986-11-29 |
Family
ID=30618956
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985076636U Pending JPS61192459U (en) | 1985-05-23 | 1985-05-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61192459U (en) |
-
1985
- 1985-05-23 JP JP1985076636U patent/JPS61192459U/ja active Pending
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